diff options
63 files changed, 4169 insertions, 7721 deletions
@@ -1,3 +1,173 @@ +commit e6615ecf4eaf4dd52696934aed8f5c6474cfd286 +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 21 14:54:29 2007 +0100 + + ppc4xx: Fix file mode of include/configs/acadia.h + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit d5f4614c9350d9333e575100fb250aab774d0258 +Author: Markus Klotzbuecher <mk@denx.de> +Date: Wed Mar 21 14:41:46 2007 +0100 + + SPC1920: fix small clock routing bug + + Signed-off-by: Markus Klotzbuecher <mk@denx.de> + +commit 16c0cc1c82081a493ab87c51980b28336ce1bce8 +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 21 13:39:57 2007 +0100 + + [PATCH] Add AMCC Acadia (405EZ) eval board support + + This patch adds support for the new AMCC Acadia eval board. + + Please note that this Acadia/405EZ support is still in a beta stage. + Still lot's of cleanup needed but we need a preliminary release now. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit e01bd218b00af73499331a1a701625a852cd286f +Author: Stefan Roese <sr@denx.de> +Date: Wed Mar 21 13:38:59 2007 +0100 + + [PATCH] Add AMCC PPC405EZ support + + This patch adds support for the new AMCC 405EZ PPC. It is in + preparation for the AMCC Acadia board support. + + Please note that this Acadia/405EZ support is still in a beta stage. + Still lot's of cleanup needed but we need a preliminary release now. + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 07e82cb2e284a893df6693f2a1337ab2c47bf6a1 +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Wed Mar 21 08:45:17 2007 +0100 + + [PATCH] TQM8272: dont change the bits given from the HRCW + for the SIUMCR and BCR Register. + Fix the calculation for the EEprom Size + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 389b6bb50f745bf5038ce030300d8a8512e96f79 +Author: Wolfgang Denk <wd@denx.de> +Date: Mon Mar 19 13:10:08 2007 +0100 + + Remove obsoleted POST files. + + Signed-off-by: Wolfgang Denk <wd@denx.de> + +commit 8423e5e31a7235d05a482627315fb11d49c17bd7 +Author: Stefan Roese <sr@denx.de> +Date: Fri Mar 16 21:11:42 2007 +0100 + + [PATCH] Use dynamic SDRAM TLB setup on AMCC Ebony eval board + + Define CONFIG_PROG_SDRAM_TLB so that the TLB entries for the + DDR memory are dynamically programmed matching the total size + of the equipped memory (DIMM modules). + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit 76d1466f918b881cda2d259254761e73885093c2 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Tue Mar 13 13:38:05 2007 +0100 + + [PATCH] renamed environment variable 'addcon' to 'addcons' for PCI405 + boards in terms of unification. + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit a7090b993d3d4d2221ac3f33e6cb1d1b2ccc6bf0 +Author: Wolfgang Denk <wd@denx.de> +Date: Tue Mar 13 16:05:55 2007 +0100 + + Make SC3 board build with 'make O='; use 'addcons' consistently + (SC3 and Jupiter used to use 'addcon' instead). + + Signed-off-by: Wolfgang Denk wd@denx.de + +commit 8502e30a28e492c756ea2d7df0ace026388fce4b +Author: Heiko Schocher <hs@pollux.denx.de> +Date: Tue Mar 13 09:40:59 2007 +0100 + + [PATCH] update board config for jupiter Board: + added Hush Shell, + CONFIG_CMDLINE_EDITING, + CFG_ENV_ADDR_REDUND activated + + Signed-off-by: Heiko Schocher <hs@denx.de> + +commit 992423ab43c2bcf6b704853bd00af77450915e20 +Author: Stefan Roese <sr@denx.de> +Date: Thu Mar 8 23:00:08 2007 +0100 + + ppc4xx: Fix file mode of sequoia.c + + Signed-off-by: Stefan Roese <sr@denx.de> + +commit eb92f613556800f7483666db09d9a237ad911d4a +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Thu Mar 8 22:52:51 2007 +0100 + + Minor cleanup. + +commit 8ce16f55c7b9752af3d8bed84521aec5337e2de1 +Author: John Otken john@softadvances.com <john@softadvances.com> +Date: Thu Mar 8 09:39:48 2007 -0600 + + ppc4xx: Clear Sequoia/Rainier security engine reset bits + + Signed-off-by: John Otken john@softadvances.com <john@softadvances.com> + +commit 650a330dd2539130c8c324791e2f9f75aed79d4e +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Thu Mar 8 16:26:52 2007 +0100 + + [PATCH] I2C: add some more SPD eeprom decoding for DDR2 modules + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit d9fc703246840c4b268debf48c334ba55c597dc0 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Thu Mar 8 16:25:47 2007 +0100 + + [PATCH] I2C: disable flat i2c commands when CONFIG_I2C_CMD_TREE is defined + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit ced5b9029043397348cdc88e0cfcd6b1f629250b +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Thu Mar 8 16:23:11 2007 +0100 + + [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUS + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit d8a8ea5c476d37006fc7f85b7f903142795c8b14 +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Thu Mar 8 16:20:32 2007 +0100 + + [PATCH] I2C: Add missing default CFG_SPD_BUS_NUM + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit f9fc6a5852a6335840882fa2111925010eea1abe +Author: Matthias Fuchs <matthias.fuchs@esd-electronics.com> +Date: Wed Mar 7 15:32:01 2007 +0100 + + fixed ethernet phy configuration for plu405 board + + Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> + +commit 769104c9356594deb2092e204a39c05b33202d6c +Author: Wolfgang Denk <wd@pollux.denx.de> +Date: Thu Mar 8 21:49:27 2007 +0100 + + Minor cleanup + commit 00cdb4ce5e1b42248e7e6522ad0da3421b988afa Author: Stefan Roese <sr@denx.de> Date: Thu Mar 8 10:13:16 2007 +0100 @@ -122,6 +292,347 @@ Date: Tue Mar 6 07:47:04 2007 +0100 Signed-off-by: Stefan Roese <sr@denx.de> +commit 781e026c8aa6f7e9eb5f0e72cc4d20971219b148 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Feb 28 00:02:04 2007 -0600 + + mpc83xx: fix implicit declaration of function 'ft_get_prop' warnings + + (cherry picked from c5bf13b02284c3204a723566a9bab700e5059659 commit) + +commit 4feab4de7bfc2cb2fed36ad76f93c3a69659bbaf +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Feb 27 23:51:42 2007 -0600 + + mpc83xx: Fix config of Arbiter, System Priority, and Clock Mode + + The config value for: + * CFG_ACR_PIPE_DEP + * CFG_ACR_RPTCNT + * CFG_SPCR_TSEC1EP + * CFG_SPCR_TSEC2EP + * CFG_SCCR_TSEC1CM + * CFG_SCCR_TSEC2CM + + Were not being used when setting the appropriate register + + Added: + * CFG_SCCR_USBMPHCM + * CFG_SCCR_USBDRCM + * CFG_SCCR_PCICM + * CFG_SCCR_ENCCM + + To allow full config of the SCCR. + + Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 + that were just bogus. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit d51b3cf371cd441030460ef19d36b2924c361b1a +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Feb 22 20:06:57 2007 -0600 + + mpc83xx: update [local-]mac-address properties on UEC based devices + + 8360 and 832x weren't updating their [local-]mac-address + properties. This patch fixes that. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + +commit 61f4f912acbe60776c5e00df1ec94094ce672957 +Author: Timur Tabi <timur@freescale.com> +Date: Tue Feb 13 10:41:42 2007 -0600 + + mpc83xx: write MAC address to mac-address and local-mac-address + + Some device trees have a mac-address property, some have local-mac-address, + and some have both. To support all of these device trees, this patch + updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. + This function already updates local-mac-address. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit 22d71a71f57fd5d38b27ac3848e50d790360a598 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Feb 27 18:41:08 2007 -0600 + + mpc83xx: add command line editing by default + +commit 3fc0bd159103b536e1c54c6f4457a09b3aba66ca +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Feb 14 19:50:53 2007 -0600 + + mpc83xx: Disable G1TXCLK, G2TXCLK h/w buffers + + Disable G1TXCLK, G2TXCLK h/w buffers. This patch + fixes a networking timeout issue with MPC8360EA (Rev.2) PBs. + + Verified on Rev. 1.1, Rev. 1.2, and Rev. 2.0 boards. + + Signed-off-by: Kim Phillips <kim.phillips@freescale.com> + Signed-off-by: Emilian Medve <Emilian.Medve@freescale.com> + +commit d61853cf2472e0b8bcbd131461a93d1c49ff0c1f +Author: Xie Xiaobo <r63061@freescale.com> +Date: Wed Feb 14 18:27:17 2007 +0800 + + mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xx + + The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. + it pass DDR/DDR2 compliance tests. + + Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> + +commit b110f40bd180c6b560276589beedf753e97c46ce +Author: Xie Xiaobo <r63061@freescale.com> +Date: Wed Feb 14 18:27:06 2007 +0800 + + mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDS + + MPC8360E rev2.0 have new spridr,and PVR value, + The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. + + Signed-off-by: Xie Xiaobo <X.Xie@freescale.com> + +commit 8d172c0f0d85998a256a95b7459a5403a30380ed +Author: Xie Xiaobo <r63061@freescale.com> +Date: Wed Feb 14 18:26:44 2007 +0800 + + mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDS + + MPC8349E rev3.1 have new spridr,and PVR value, + The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. + + Signed-off-by: Xie Xiaobo<X.Xie@freescale.com> + +commit f6f5f709e5c8e4564c4dfeecfdf2279244f9c83b +Author: Joakim Tjernlund <joakim.tjernlund@transmode.se> +Date: Wed Jan 31 11:04:19 2007 +0100 + + mpc83xx: Fix empty i2c reads/writes in fsl_i2c.c + + Fix empty i2c reads/writes, i2c_write(0x50, 0x00, 0, NULL, 0) + which is used to se if an slave will ACK after receiving its address. + + Correct i2c probing to use this method as the old method could upset + a slave as it wrote a data byte to it. + + Add a small delay in i2c_init() to let the controller + shutdown any ongoing I2C activity. + + Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> + +commit 7a78f148d6a7298e4fface680dc7eacd877b1aba +Author: Timur Tabi <timur@freescale.com> +Date: Wed Jan 31 15:54:29 2007 -0600 + + mpc83xx: Add support for the MPC8349E-mITX-GP + + Add support for the MPC8349E-mITX-GP, a stripped-down version of the + MPC8349E-mITX. Bonus features include support for low-boot (BMS bit in + HRCW is 0) for the ITX and a README for the ITX and the ITX-GP. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit fab16807adad350f618024350c6950165c247c72 +Author: Timur Tabi <timur@freescale.com> +Date: Wed Jan 31 15:54:20 2007 -0600 + + mpc83xx: Delete sdram_init() for MPC8349E-mITX + + There is no SDRAM on any of the 8349 ITX variants, so function sdram_init() + never does anything. This patch deletes it. + + Signed-off-by: Timur Tabi <timur@freescale.com> + +commit a87c856eb411b9365937d0d4b9c21e46adbe1c14 +Author: Dave Liu <daveliu@freescale.com> +Date: Fri Jan 19 10:43:26 2007 +0800 + + mpc83xx: Fix the LAW1/3 bug + + The patch solves the alignment problem of the local bus access windows to + render accessible the memory bank and PHY registers of UPC 1 (starting at + 0xf801 0000). What we actually did was to adjust the sizes of the bus + access windows so that the base address alignment requirement would be met. + + Signed-off-by: Chereji Marian <marian.chereji@freescale.com> + Signed-off-by: Gridish Shlomi <gridish@freescale.com> + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 97c4b397dce236a7318b304667bf89e59d08b17c +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jan 30 16:15:31 2007 -0600 + + mpc83xx: don't hang if watchdog configured on 8360, 832x + + don't hang if watchdog configured on 8360, 832x + + The watchdog programming model is the same across all 83xx devices; + make the code reflect that. + +commit b70047478570e371ce7223be342ce98afea0f7d6 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jan 30 16:15:21 2007 -0600 + + mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dt + + protect memcpy to bad address if a local-mac-address is missing from dt + +commit 6752ed088c75c26a89b70c46b7326a4cd6015f29 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Tue Jan 30 16:15:04 2007 -0600 + + mpc83xx: make 8360 default environment fdt be 8360 (not 8349) + + make 8360 default environment fdt be 8360 (not 8349) + +commit a28899c910024a0226331df07207b1038c300c93 +Author: Emilian Medve <Emilian.Medve@freescale.com> +Date: Tue Jan 30 16:14:50 2007 -0600 + + mpc83xx: Fix alternating tx error / tx buffer not ready bug in QE UEC + + The problem is not gcc4 but the code itself. The BD_STATUS() macro can't + be used for busy-waiting since it strips the 'volatile' property from + the bd variable. gcc3 was working by pure luck. + + This is a follow on patch to "Fix the UEC driver bug of QE" + +commit 3e78a31cfe3d3022f46f67eb88e1281d5cc2eb89 +Author: Kumar Gala <galak@kernel.crashing.org> +Date: Tue Jan 30 14:08:30 2007 -0600 + + mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X instead + + The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all + MPC834X class processors. Change the protections from CONFIG_MPC8349 to + CONFIG_MPC834X so they are more generic. + + Signed-off-by: Kumar Gala <galak@kernel.crashing.org> + +commit ae246dc6c1937c291014eadd90b6d48c438c7cb0 +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Thu Jan 25 13:40:55 2007 -0600 + + mpc83xx: add MPC832XEMDS and sbc8349 to MAKEALL + +commit 4decd84e8f04279c5cfff7f8e907465ef8d8a3fb +Author: Kim Phillips <kim.phillips@freescale.com> +Date: Wed Jan 24 17:18:37 2007 -0600 + + mpc83xx: sort Makefile targets + + reordered targets alphabetically + +commit 91e25769771c1164ed63ffca0add49f934ae3343 +Author: Paul Gortmaker <paul.gortmaker@windriver.com> +Date: Tue Jan 16 11:38:14 2007 -0500 + + mpc83xx: U-Boot support for Wind River SBC8349 + + I've redone the SBC8349 support to match git-current, which + incorporates all the MPC834x updates from Freescale since the 1.1.6 + release, including the DDR changes. + + I've kept all the SBC8349 files as parallel as possible to the + MPC8349EMDS ones for ease of maintenance and to allow for easy + inspection of what was changed to support this board. Hence the SBC8349 + U-Boot has FDT support and everything else that the MPC8349EMDS has. + + Fortunately the Freescale updates added support for boards using CS0, + but I had to change spd_sdram.c to allow for board specific settings for + the sdram_clk_cntl (it is/was hard coded to zero, and that remains the + default if the board doesn't specify a value.) + + Hopefully this should be mergeable as-is and require no whitespace + cleanups or similar, but if something doesn't measure up then let me + know and I'll fix it. + + Thanks, + Paul. + +commit 05031db456ab227f3e3752f37b9b812b65bb83ad +Author: Sam Song <samsongshu@yahoo.com.cn> +Date: Thu Dec 14 19:03:21 2006 +0800 + + mpc83xx: Remove a redundant semicolon in mpc8349itx.c + + A redundant semicolon existed in mpc8349itx.c + should be removed. + + Signed-off-by: Sam Song <samsongshu@yahoo.com.cn> + +commit f35f358241c549be3f75cfe2eaa642914275b7ba +Author: Jerry Van Baren <gerald.vanbaren@comcast.net> +Date: Wed Dec 6 21:23:55 2006 -0500 + + mpc83xx: Put the version (and magic) after the HRCW. + + Put the version (and magic) after the HRCW. This puts it in a fixed + location in flash, not at the start of flash but as close as we can get. + + Signed-off-by: Jerry Van Baren <vanbaren@cideas.com> + +commit 48aecd969171a6e99a55fae04933857787f9a5bd +Author: Dave Liu <r63238@freescale.com> +Date: Thu Dec 7 21:14:51 2006 +0800 + + mpc83xx: Add the MPC832XEMDS board readme + + Add the MPC832XEMDS board readme + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit 24c3aca3f1358b113d3215adb5433b156e99f72b +Author: Dave Liu <r63238@freescale.com> +Date: Thu Dec 7 21:13:15 2006 +0800 + + mpc83xx: Add support for the MPC832XEMDS board + + This patch supports DUART, ETH3/4 and PCI etc. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit e080313c32322e15ab5a18eb896a252858c57284 +Author: Dave Liu <r63238@freescale.com> +Date: Thu Dec 7 21:11:58 2006 +0800 + + mpc83xx: streamline the 83xx immr head file + + For better format and style, I streamlined the 83xx head files, + including immap_83xx.h and mpc83xx.h. In the old head files, 1) + duplicated macro definition appear in the both files; 2) the structure + of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The + macro definition put inside the each structure. So, I cleaned up the + structure of QE immr from immap_83xx.h, deleted the duplicated stuff and + moved the macro definition to mpc83xx.h, Just like MPC8260. + + CHANGELOG + + *streamline the 83xx immr head file + + Signed-off-by: Dave Liu <daveliu@freescale.com> + +commit ddd02492f43db5408f5ab9f823b0ba5796e28ef0 +Author: Dave Liu <r63238@freescale.com> +Date: Wed Dec 6 11:38:17 2006 +0800 + + mpc83xx: Fix the UEC driver bug of QE + + The patch prevents the GCC tool chain from striping useful code for + optimization. It will make UEC ethernet driver workable, Otherwise the + UEC will fail in tx when you are using gcc4.x. but the driver can work + when using gcc3.4.3. + + CHANGELOG + + *Prevent the GCC from striping code for optimization, Otherwise the UEC + will tx failed when you are using gcc4.x. + + Signed-off-by: Dave Liu <daveliu@freescale.com> + commit ba58e4c9a9a917ce795dd16d4ec8d515f9f7aa35 Author: Stefan Roese <sr@denx.de> Date: Thu Mar 1 21:11:36 2007 +0100 @@ -1204,6 +1715,14 @@ Date: Tue Nov 28 11:04:45 2006 +0100 Signed-off-by: Stefan Roese <sr@denx.de> +commit 58e3b14c18ed3288ceef8d086946dbf3df64ccf2 +Author: Stefan Roese <sr@denx.de> +Date: Tue Nov 28 11:04:45 2006 +0100 + + [PATCH] nand: Fix patch merge problem + + Signed-off-by: Stefan Roese <sr@denx.de> + commit 4f4b602ec7524a032bdf3c6d28c7f525a4a67eaa Author: Wolfgang Denk <wd@pollux.denx.de> Date: Mon Nov 27 22:53:53 2006 +0100 diff --git a/MAINTAINERS b/MAINTAINERS index 183fb10..68233cf 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -284,6 +284,7 @@ Stefan Roese <sr@denx.de> TQM85xx MPC8540/8541/8555/8560 + acadia PPC405EZ alpr PPC440GX bamboo PPC440EP bunbinga PPC405EP @@ -75,22 +75,22 @@ LIST_8xx=" \ ######################################################################### LIST_4xx=" \ - ADCIOP alpr AP1000 AR405 \ - ASH405 bamboo bubinga CANBT \ - CMS700 CPCI2DP CPCI405 CPCI4052 \ - CPCI405AB CPCI405DT CPCI440 CPCIISER4 \ - CRAYL1 csb272 csb472 DASA_SIM \ - DP405 DU405 ebony ERIC \ - EXBITGEN G2000 HH405 HUB405 \ - JSE KAREF katmai luan \ - METROBOX MIP405 MIP405T ML2 \ - ml300 ocotea OCRTC ORSG \ - p3p440 PCI405 pcs440ep PIP405 \ - PLU405 PMC405 PPChameleonEVB sbc405 \ - sc3 sequoia sequoia_nand taishan \ - VOH405 VOM405 W7OLMC W7OLMG \ - walnut WUH405 XPEDITE1K yellowstone \ - yosemite yucca \ + acadia ADCIOP alpr AP1000 \ + AR405 ASH405 bamboo bubinga \ + CANBT CMS700 CPCI2DP CPCI405 \ + CPCI4052 CPCI405AB CPCI405DT CPCI440 \ + CPCIISER4 CRAYL1 csb272 csb472 \ + DASA_SIM DP405 DU405 ebony \ + ERIC EXBITGEN G2000 HH405 \ + HUB405 JSE KAREF katmai \ + luan METROBOX MIP405 MIP405T \ + ML2 ml300 ocotea OCRTC \ + ORSG p3p440 PCI405 pcs440ep \ + PIP405 PLU405 PMC405 PPChameleonEVB \ + sbc405 sc3 sequoia sequoia_nand \ + taishan VOH405 VOM405 W7OLMC \ + W7OLMG walnut WUH405 XPEDITE1K \ + yellowstone yosemite yucca \ " ######################################################################### @@ -1006,6 +1006,9 @@ wtk_config: unconfig ######################################################################### xtract_4xx = $(subst _25,,$(subst _33,,$(subst _BA,,$(subst _ME,,$(subst _HI,,$(subst _config,,$1)))))) +acadia_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx acadia amcc + ADCIOP_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx adciop esd diff --git a/board/amcc/acadia/Makefile b/board/amcc/acadia/Makefile new file mode 100644 index 0000000..183f694 --- /dev/null +++ b/board/amcc/acadia/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2007 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +OBJS = $(BOARD).o cpr.o memory.o +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +sinclude .depend + +######################################################################### diff --git a/board/amcc/acadia/acadia.c b/board/amcc/acadia/acadia.c new file mode 100644 index 0000000..c8aaad2 --- /dev/null +++ b/board/amcc/acadia/acadia.c @@ -0,0 +1,152 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +extern void board_pll_init_f(void); + +/* Some specific Acadia Defines */ +#define CPLD_BASE 0x80000000 + +void liveoak_gpio_init(void) +{ + /* + * GPIO0 setup (select GPIO or alternate function) + */ + out32(GPIO0_OSRL, CFG_GPIO0_OSRL); + out32(GPIO0_OSRH, CFG_GPIO0_OSRH); /* output select */ + out32(GPIO0_ISR1L, CFG_GPIO0_ISR1L); + out32(GPIO0_ISR1H, CFG_GPIO0_ISR1H); /* input select */ + out32(GPIO0_TSRL, CFG_GPIO0_TSRL); + out32(GPIO0_TSRH, CFG_GPIO0_TSRH); /* three-state select */ + out32(GPIO0_TCR, CFG_GPIO0_TCR); /* enable output driver for outputs */ + + /* + * Ultra (405EZ) was nice enough to add another GPIO controller + */ + out32(GPIO1_OSRH, CFG_GPIO1_OSRH); /* output select */ + out32(GPIO1_OSRL, CFG_GPIO1_OSRL); + out32(GPIO1_ISR1H, CFG_GPIO1_ISR1H); /* input select */ + out32(GPIO1_ISR1L, CFG_GPIO1_ISR1L); + out32(GPIO1_TSRH, CFG_GPIO1_TSRH); /* three-state select */ + out32(GPIO1_TSRL, CFG_GPIO1_TSRL); + out32(GPIO1_TCR, CFG_GPIO1_TCR); /* enable output driver for outputs */ +} + +#if 0 /* test-only: not called at all??? */ +void ext_bus_cntlr_init(void) +{ +#if (defined(EBC_PB4AP) && defined(EBC_PB4CR) && !(CFG_INIT_DCACHE_CS == 4)) + mtebc(pb4ap, EBC_PB4AP); + mtebc(pb4cr, EBC_PB4CR); +#endif +} +#endif + +int board_early_init_f(void) +{ + unsigned int reg; + +#if 0 /* test-only */ + /* + * If CRAM memory and SPI/NAND boot, and if the CRAM memory is + * already initialized by the pre-loader then we can't reinitialize + * CPR registers, GPIO registers and EBC registers as this will + * have the effect of un-initializing CRAM. + */ + spr_reg = (volatile unsigned long) mfspr(SPRG7); + if (spr_reg != LOAK_CRAM) { /* != CRAM */ + board_pll_init_f(); + liveoak_gpio_init(); + ext_bus_cntlr_init(); + + mtebc(pb1ap, CFG_EBC_PB1AP); + mtebc(pb1cr, CFG_EBC_PB1CR); + + mtebc(pb2ap, CFG_EBC_PB2AP); + mtebc(pb2cr, CFG_EBC_PB2CR); + } +#else + board_pll_init_f(); + liveoak_gpio_init(); +/* ext_bus_cntlr_init(); */ +#endif + +#if 0 /* test-only (orig) */ + /* + * If we boot from NAND Flash, we are running in + * RAM, so disable the EBC_CS0 so that it goes back + * to the NOR Flash. It will be enabled later + * for the NAND Flash on EBC_CS1 + */ + mfsdr(sdrultra0, reg); + mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); +#endif +#if 0 /* test-only */ + /* configure for NAND */ + mfsdr(sdrultra0, reg); + reg &= ~SDR_ULTRA0_CSN_MASK; + reg |= SDR_ULTRA0_CSNSEL0 >> CFG_NAND_CS; + mtsdr(sdrultra0, reg & ~SDR_ULTRA0_CSNSEL0); +#endif + + /* USB Host core needs this bit set */ + mfsdr(sdrultra1, reg); + mtsdr(sdrultra1, reg | SDR_ULTRA1_LEDNENABLE); + + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + mtdcr(uicer, 0x00000000); /* disable all ints */ + mtdcr(uiccr, 0x00000010); + mtdcr(uicpr, 0xFE7FFFF0); /* set int polarities */ + mtdcr(uictr, 0x00000010); /* set int trigger levels */ + mtdcr(uicsr, 0xFFFFFFFF); /* clear all ints */ + + return 0; +} + +int misc_init_f(void) +{ + /* Set EPLD to take PHY out of reset */ + out8(CPLD_BASE + 0x05, 0x00); + udelay(100000); + + return 0; +} + +/* + * Check Board Identity: + */ +int checkboard(void) +{ + char *s = getenv("serial#"); + + printf("Board: Acadia - AMCC PPC405EZ Evaluation Board"); + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} diff --git a/post/cpu/Makefile b/board/amcc/acadia/config.mk index 645e838..ce21374 100644 --- a/post/cpu/Makefile +++ b/board/amcc/acadia/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002-2006 +# (C) Copyright 2000 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # See file CREDITS for list of people who contributed to this @@ -21,13 +21,21 @@ # MA 02111-1307 USA # -SUBDIRS = +sinclude $(TOPDIR)/board/amcc/liveoak/config.tmp -LIB = libcpu.a +ifndef TEXT_BASE +TEXT_BASE = 0xFFFC0000 +endif -AOBJS = asm.o -COBJS = cmp.o cmpi.o two.o twox.o three.o threex.o -COBJS += threei.o andi.o srawi.o rlwnm.o rlwinm.o rlwimi.o -COBJS += store.o load.o cr.o b.o multi.o string.o complex.o +ifeq ($(CONFIG_NAND_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-nand.lds +endif -include $(TOPDIR)/post/rules.mk +ifeq ($(CONFIG_SPI_U_BOOT),y) +LDSCRIPT = $(TOPDIR)/board/$(BOARDDIR)/u-boot-spi.lds +PAD_TO = 0x00840000 +endif + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/board/amcc/acadia/cpr.c b/board/amcc/acadia/cpr.c new file mode 100644 index 0000000..23b9e12 --- /dev/null +++ b/board/amcc/acadia/cpr.c @@ -0,0 +1,195 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <ppc405.h> + +/* test-only: move into cpu directory!!! */ + +#if defined(PLLMR0_200_133_66) +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 200.0 | 4 (0x02)| + * | PLB | 133.3 | 6 (0x06)| + * | OPB | 66.6 | 12 (0x0C)| + * | EBC | 66.6 | 12 (0x0C)| + * | SPI | 66.6 | 12 (0x0C)| + * | UART0 | 10.0 | 40 (0x28)| + * | UART1 | 10.0 | 40 (0x28)| + * | DAC | 2.0 | 200 (0xC8)| + * | ADC | 2.0 | 200 (0xC8)| + * | PWM | 100.0 | 4 (0x04)| + * | EMAC | 25.0 | 16 (0x10)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x0000033c); + mtcpr(cprplld, 0x0c010200); + mtcpr(cprprimad, 0x04060c0c); + mtcpr(cprperd0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_266_160_80) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 266.64 | 3 | + * | PLB | 159.98 | 5 (0x05)| + * | OPB | 79.99 | 10 (0x0A)| + * | EBC | 79.99 | 10 (0x0A)| + * | SPI | 79.99 | 10 (0x0A)| + * | UART0 | 28.57 | 7 (0x07)| + * | UART1 | 28.57 | 7 (0x07)| + * | DAC | 28.57 | 7 (0xA7)| + * | ADC | 4 | 50 (0x32)| + * | PWM | 28.57 | 7 (0x07)| + * | EMAC | 4 | 50 (0x32)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x20000238); + mtcpr(cprplld, 0x03010400); + mtcpr(cprprimad, 0x03050a0a); + mtcpr(cprperc0, 0x00000000); + mtcpr(cprperd0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0x07323200); + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_333_166_83) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------------------- + * | CLK | FREQ (MHz) | DIV RATIO | + * ---------------------------------- + * | CPU | 333.33 | 2 | + * | PLB | 166.66 | 4 (0x04)| + * | OPB | 83.33 | 8 (0x08)| + * | EBC | 83.33 | 8 (0x08)| + * | SPI | 83.33 | 8 (0x08)| + * | UART0 | 16.66 | 5 (0x05)| + * | UART1 | 16.66 | 5 (0x05)| + * | DAC | ???? | 166 (0xA6)| + * | ADC | ???? | 166 (0xA6)| + * | PWM | 41.66 | 3 (0x03)| + * | EMAC | ???? | 3 (0x03)| + * ----------------------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x0000033C); + mtcpr(cprplld, 0x0a010000); + mtcpr(cprprimad, 0x02040808); + mtcpr(cprperd0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xA6A60300); + mtcpr(cprclkupd, 0x40000000); +} + +#elif defined(PLLMR0_100_100_12) + +void board_pll_init_f(void) +{ + /* + * set PLL clocks based on input sysclk is 33M + * + * ---------------------- + * | CLK | FREQ (MHz) | + * ---------------------- + * | CPU | 100.00 | + * | PLB | 100.00 | + * | OPB | 12.00 | + * | EBC | 49.00 | + * ---------------------- + */ + + /* Initialize PLL */ + mtcpr(cprpllc, 0x000003BC); + mtcpr(cprplld, 0x06060600); + mtcpr(cprprimad, 0x02020004); + mtcpr(cprperd0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(cprperd1, 0xC8C81600); + mtcpr(cprclkupd, 0x40000000); +} +#endif /* CPU_<speed>_405EZ */ + +#if defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) +/* + * Get timebase clock frequency + */ +unsigned long get_tbclk (void) +{ + unsigned long cpr_plld; + unsigned long cpr_primad; + unsigned long primad_cpudv; + unsigned long pllFbkDiv; + unsigned long freqProcessor; + + /* + * Read PLL Mode registers + */ + mfcpr(cprplld, cpr_plld); + + /* + * Read CPR_PRIMAD register + */ + mfcpr(cprprimad, cpr_primad); + + /* + * Determine CPU clock frequency + */ + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); + if (primad_cpudv == 0) + primad_cpudv = 16; + + /* + * Determine FBK_DIV. + */ + pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (pllFbkDiv == 0) + pllFbkDiv = 256; + + freqProcessor = (CONFIG_SYS_CLK_FREQ * pllFbkDiv) / primad_cpudv; + + return (freqProcessor); +} +#endif /* defined(CONFIG_NAND_SPL) || defined(CONFIG_SPI_SPL) */ diff --git a/board/amcc/acadia/flash.c b/board/amcc/acadia/flash.c new file mode 100644 index 0000000..0626aba --- /dev/null +++ b/board/amcc/acadia/flash.c @@ -0,0 +1,1108 @@ +/* + * (C) Copyright 2004-2005 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * (C) Copyright 2002 Jun Gu <jung@artesyncp.com> + * Add support for Am29F016D and dynamic switch setting. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * Modified 4/5/2001 + * Wait for completion of each sector erase command issued + * 4/5/2001 + * Chris Hallinan - DS4.COM, Inc. - clh@net1plus.com + */ + +#include <common.h> +#include <ppc4xx.h> +#include <asm/processor.h> + +#ifdef DEBUG +#define DEBUGF(x...) printf(x) +#else +#define DEBUGF(x...) +#endif /* DEBUG */ + +flash_info_t flash_info[CFG_MAX_FLASH_BANKS]; /* info for FLASH chips */ + +/* + * Mark big flash bank (16 bit instead of 8 bit access) in address with bit 0 + */ +static unsigned long flash_addr_table[][CFG_MAX_FLASH_BANKS] = { + {0xffc00001}, /* 0:boot from big flash */ +}; + +/* + * include common flash code (for amcc boards) + */ +/*----------------------------------------------------------------------- + * Functions + */ +static int write_word(flash_info_t * info, ulong dest, ulong data); +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word_1(flash_info_t * info, ulong dest, ulong data); +static int write_word_2(flash_info_t * info, ulong dest, ulong data); +static int flash_erase_1(flash_info_t * info, int s_first, int s_last); +static int flash_erase_2(flash_info_t * info, int s_first, int s_last); +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info); +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info); +#endif + +void flash_print_info(flash_info_t * info) +{ + int i; + int k; + int size; + int erased; + volatile unsigned long *flash; + + if (info->flash_id == FLASH_UNKNOWN) { + printf("missing or unknown FLASH type\n"); + return; + } + + switch (info->flash_id & FLASH_VENDMASK) { + case FLASH_MAN_AMD: + printf("AMD "); + break; + case FLASH_MAN_STM: + printf("STM "); + break; + case FLASH_MAN_FUJ: + printf("FUJITSU "); + break; + case FLASH_MAN_SST: + printf("SST "); + break; + case FLASH_MAN_MX: + printf("MIXC "); + break; + default: + printf("Unknown Vendor "); + break; + } + + switch (info->flash_id & FLASH_TYPEMASK) { + case FLASH_AM040: + printf("AM29F040 (512 Kbit, uniform sector size)\n"); + break; + case FLASH_AM400B: + printf("AM29LV400B (4 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM400T: + printf("AM29LV400T (4 Mbit, top boot sector)\n"); + break; + case FLASH_AM800B: + printf("AM29LV800B (8 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM800T: + printf("AM29LV800T (8 Mbit, top boot sector)\n"); + break; + case FLASH_AMD016: + printf("AM29F016D (16 Mbit, uniform sector size)\n"); + break; + case FLASH_AM160B: + printf("AM29LV160B (16 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM160T: + printf("AM29LV160T (16 Mbit, top boot sector)\n"); + break; + case FLASH_AM320B: + printf("AM29LV320B (32 Mbit, bottom boot sect)\n"); + break; + case FLASH_AM320T: + printf("AM29LV320T (32 Mbit, top boot sector)\n"); + break; + case FLASH_AM033C: + printf("AM29LV033C (32 Mbit, top boot sector)\n"); + break; + case FLASH_SST800A: + printf("SST39LF/VF800 (8 Mbit, uniform sector size)\n"); + break; + case FLASH_SST160A: + printf("SST39LF/VF160 (16 Mbit, uniform sector size)\n"); + break; + case FLASH_STMW320DT: + printf ("M29W320DT (32 M, top sector)\n"); + break; + case FLASH_MXLV320T: + printf ("MXLV320T (32 Mbit, top sector)\n"); + break; + default: + printf("Unknown Chip Type\n"); + break; + } + + printf(" Size: %ld KB in %d Sectors\n", + info->size >> 10, info->sector_count); + + printf(" Sector Start Addresses:"); + for (i = 0; i < info->sector_count; ++i) { + /* + * Check if whole sector is erased + */ + if (i != (info->sector_count - 1)) + size = info->start[i + 1] - info->start[i]; + else + size = info->start[0] + info->size - info->start[i]; + erased = 1; + flash = (volatile unsigned long *)info->start[i]; + size = size >> 2; /* divide by 4 for longword access */ + for (k = 0; k < size; k++) { + if (*flash++ != 0xffffffff) { + erased = 0; + break; + } + } + + if ((i % 5) == 0) + printf("\n "); + printf(" %08lX%s%s", + info->start[i], + erased ? " E" : " ", info->protect[i] ? "RO " : " "); + } + printf("\n"); + return; +} + +/* + * The following code cannot be run from FLASH! + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +{ + /* bit 0 used for big flash marking */ + if ((ulong)addr & 0x1) { + return flash_get_size_2((vu_long *)((ulong)addr & 0xfffffffe), info); + } else { + return flash_get_size_1(addr, info); + } +} + +static ulong flash_get_size_1(vu_long * addr, flash_info_t * info) +#else +static ulong flash_get_size(vu_long * addr, flash_info_t * info) +#endif +{ + short i; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } + + value = addr2[1]; /* device ID */ + DEBUGF("\nFLASH DEVICEID: %x\n", value); + + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) STM_ID_M29W040B: + info->flash_id += FLASH_AM040; + info->sector_count = 8; + info->size = 0x0080000; /* => 512 ko */ + break; + + case (CFG_FLASH_WORD_SIZE) AMD_ID_F016D: + info->flash_id += FLASH_AMD016; + info->sector_count = 32; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV033C: + info->flash_id += FLASH_AMDLV033C; + info->sector_count = 64; + info->size = 0x00400000; + break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400T: + info->flash_id += FLASH_AM400T; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV400B: + info->flash_id += FLASH_AM400B; + info->sector_count = 11; + info->size = 0x00080000; + break; /* => 0.5 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800T: + info->flash_id += FLASH_AM800T; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV800B: + info->flash_id += FLASH_AM800B; + info->sector_count = 19; + info->size = 0x00100000; + break; /* => 1 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160T: + info->flash_id += FLASH_AM160T; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + case (CFG_FLASH_WORD_SIZE) AMD_ID_LV160B: + info->flash_id += FLASH_AM160B; + info->sector_count = 35; + info->size = 0x00200000; + break; /* => 2 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else { + if (info->flash_id & FLASH_BTYPE) { + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address, (A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +static int wait_for_DQ7_1(flash_info_t * info, int sect) +{ + ulong start, now, last; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + } + return 0; +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV +int flash_erase(flash_info_t * info, int s_first, int s_last) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { + return flash_erase_2(info, s_first, s_last); + } else { + return flash_erase_1(info, s_first, s_last); + } +} + +static int flash_erase_1(flash_info_t * info, int s_first, int s_last) +#else +int flash_erase(flash_info_t * info, int s_first, int s_last) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ + } + l_sect = sect; + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_1(info, sect); + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + return 0; +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt) +{ + ulong cp, wp, data; + int i, l, rc; + + wp = (addr & ~3); /* get lower word aligned address */ + + /* + * handle unaligned start bytes + */ + if ((l = addr - wp) != 0) { + data = 0; + for (i = 0, cp = wp; i < l; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + for (; i < 4 && cnt > 0; ++i) { + data = (data << 8) | *src++; + --cnt; + ++cp; + } + for (; cnt == 0 && i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + } + + /* + * handle word aligned part + */ + while (cnt >= 4) { + data = 0; + for (i = 0; i < 4; ++i) { + data = (data << 8) | *src++; + } + if ((rc = write_word(info, wp, data)) != 0) { + return (rc); + } + wp += 4; + cnt -= 4; + } + + if (cnt == 0) { + return (0); + } + + /* + * handle unaligned tail bytes + */ + data = 0; + for (i = 0, cp = wp; i < 4 && cnt > 0; ++i, ++cp) { + data = (data << 8) | *src++; + --cnt; + } + for (; i < 4; ++i, ++cp) { + data = (data << 8) | (*(uchar *) cp); + } + + return (write_word(info, wp, data)); +} + +/*----------------------------------------------------------------------- + * Copy memory to flash, returns: + * 0 - OK + * 1 - write timeout + * 2 - Flash not erased + */ +#ifdef CFG_FLASH_2ND_16BIT_DEV +static int write_word(flash_info_t * info, ulong dest, ulong data) +{ + if (((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320B) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T)) { + return write_word_2(info, dest, data); + } else { + return write_word_1(info, dest, data); + } +} + +static int write_word_1(flash_info_t * info, ulong dest, ulong data) +#else +static int write_word(flash_info_t * info, ulong dest, ulong data) +#endif +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} + +#ifdef CFG_FLASH_2ND_16BIT_DEV + +#undef CFG_FLASH_WORD_SIZE +#define CFG_FLASH_WORD_SIZE unsigned short + +/* + * The following code cannot be run from FLASH! + */ +static ulong flash_get_size_2(vu_long * addr, flash_info_t * info) +{ + short i; + int n; + CFG_FLASH_WORD_SIZE value; + ulong base = (ulong) addr; + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) addr; + + DEBUGF("FLASH ADDR: %08x\n", (unsigned)addr); + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + /* Write auto select command: read Manufacturer ID */ + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00900090; + udelay(1000); + + value = addr2[0]; + DEBUGF("FLASH MANUFACT: %x\n", value); + +#if 0 /* TODO: remove ifdef when Flash responds correctly */ + switch (value) { + case (CFG_FLASH_WORD_SIZE) AMD_MANUFACT: + info->flash_id = FLASH_MAN_AMD; + break; + case (CFG_FLASH_WORD_SIZE) FUJ_MANUFACT: + info->flash_id = FLASH_MAN_FUJ; + break; + case (CFG_FLASH_WORD_SIZE) SST_MANUFACT: + info->flash_id = FLASH_MAN_SST; + break; + case (CFG_FLASH_WORD_SIZE) STM_MANUFACT: + info->flash_id = FLASH_MAN_STM; + break; + case (CFG_FLASH_WORD_SIZE) MX_MANUFACT: + info->flash_id = FLASH_MAN_MX; + break; + default: + info->flash_id = FLASH_UNKNOWN; + info->sector_count = 0; + info->size = 0; + return (0); /* no or unknown flash */ + } +#endif /* TODO: remove ifdef when Flash responds correctly */ + + /* + * TODO: Start + * uncomment block above when Flash responds correctly. + * also remove the lines below: + */ + info->flash_id = FLASH_MAN_AMD; + DEBUGF("FLASH MANUFACT: FLASH_MAN_AMD\n"); + /* TODO: End */ + + value = addr2[1]; /* device ID */ + + DEBUGF("\nFLASH DEVICEID: %x\n", value); + +#if 0 /* TODO: remove ifdef when Flash responds correctly */ + switch (value) { + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320T: + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)AMD_ID_LV320B: + info->flash_id += FLASH_AM320B; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)STM_ID_29W320DT: + info->flash_id += FLASH_STMW320DT; + info->sector_count = 67; + info->size = 0x00400000; break; /* => 4 MB */ + + case (CFG_FLASH_WORD_SIZE)MX_ID_LV320T: + info->flash_id += FLASH_MXLV320T; + info->sector_count = 71; + info->size = 0x00400000; break; /* => 4 MB */ + + default: + info->flash_id = FLASH_UNKNOWN; + return (0); /* => no or unknown flash */ + } +#endif /* TODO: remove ifdef when Flash responds correctly */ + + /* + * TODO: Start + * uncomment block above when Flash responds correctly. + * also remove the lines below: + */ + DEBUGF("\nFLASH DEVICEID: FLASH_AM320T\n"); + info->flash_id += FLASH_AM320T; + info->sector_count = 71; + info->size = 0x00400000; /* => 4 MB */ + /* TODO: End */ + + /* set up sector start address table */ + if (((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM040) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AMD016)) { + for (i = 0; i < info->sector_count; i++) + info->start[i] = base + (i * 0x00010000); + } else if ((info->flash_id & FLASH_TYPEMASK) == FLASH_STMW320DT) { + /* set sector offsets for top boot block type */ + base += info->size; + i = info->sector_count; + /* 1 x 16k boot sector */ + base -= 16 << 10; + --i; + info->start[i] = base; + /* 2 x 8k boot sectors */ + for (n=0; n<2; ++n) { + base -= 8 << 10; + --i; + info->start[i] = base; + } + /* 1 x 32k boot sector */ + base -= 32 << 10; + --i; + info->start[i] = base; + + while (i > 0) { /* 64k regular sectors */ + base -= 64 << 10; + --i; + info->start[i] = base; + } + } else if ( ((info->flash_id & FLASH_TYPEMASK) == FLASH_MXLV320T) || + ((info->flash_id & FLASH_TYPEMASK) == FLASH_AM320T) ) { + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00002000; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + info->start[i--] = base + info->size - 0x0000a000; + info->start[i--] = base + info->size - 0x0000c000; + info->start[i--] = base + info->size - 0x0000e000; + info->start[i--] = base + info->size - 0x00010000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + else { + if (info->flash_id & FLASH_BTYPE){ + /* set sector offsets for bottom boot block type */ + info->start[0] = base + 0x00000000; + info->start[1] = base + 0x00004000; + info->start[2] = base + 0x00006000; + info->start[3] = base + 0x00008000; + for (i = 4; i < info->sector_count; i++) { + info->start[i] = + base + (i * 0x00010000) - 0x00030000; + } + } else { + /* set sector offsets for top boot block type */ + i = info->sector_count - 1; + info->start[i--] = base + info->size - 0x00004000; + info->start[i--] = base + info->size - 0x00006000; + info->start[i--] = base + info->size - 0x00008000; + for (; i >= 0; i--) { + info->start[i] = base + i * 0x00010000; + } + } + } + + /* check for protected sectors */ + for (i = 0; i < info->sector_count; i++) { + /* read sector protection at sector address,(A7 .. A0) = 0x02 */ + /* D0 = 1 if protected */ + addr2 = (volatile CFG_FLASH_WORD_SIZE *)(info->start[i]); + + /* For AMD29033C flash we need to resend the command of * + * reading flash protection for upper 8 Mb of flash */ + if (i == 32) { + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0xAAAAAAAA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x55555555; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x90909090; + } + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) + info->protect[i] = 0; + else + info->protect[i] = addr2[2] & 1; + } + + /* issue bank reset to return to read mode */ + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; + + return (info->size); +} + +/* + * TODO: FIX: this wait loop sometimes fails: DQ7 indicates the erase command + * never was accepted (i.e. didn't start) - why???? + */ +static int wait_for_DQ7_2(flash_info_t * info, int sect) +{ + ulong start, now, last, counter = 0; + volatile CFG_FLASH_WORD_SIZE *addr = + (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + start = get_timer(0); + DEBUGF("DQ7_2: start = 0x%08lx\n", start); + last = start; + while ((addr[0] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (CFG_FLASH_WORD_SIZE) 0x00800080) { + DEBUGF("DQ7_2: start = 0x%08lx, now = 0x%08lx\n", start, now); + if ((now = get_timer(start)) > CFG_FLASH_ERASE_TOUT) { + printf("Timeout\n"); + return -1; + } + /* show that we're waiting */ + if ((now - last) > 1000) { /* every second */ + putc('.'); + last = now; + } + udelay(1000000); /* 1 sec */ + putc('.'); + counter++; + if (counter > 5) { + return -1; + } + DEBUGF("DQ7_2: now = 0x%08lx, last = 0x%08lx\n", now, last); + } + return 0; +} + +static void wr_flash_cmd(ulong sector, ushort addr, CFG_FLASH_WORD_SIZE value) +{ + int fw_size; + + fw_size = sizeof(value); + switch (fw_size) + { + case 1: + out8((ulong)(sector + addr), value); + break; + case 2: + out16((ulong)(sector + (addr << 1)), value); + break; + default: + printf("flash_erase: error incorrect chip programing size.\n"); + } + return; +} + +static int flash_erase_2(flash_info_t * info, int s_first, int s_last) +{ + volatile CFG_FLASH_WORD_SIZE *addr = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *addr2; + int flag, prot, sect, l_sect, count = 0; + int i; + + if ((s_first < 0) || (s_first > s_last)) { + if (info->flash_id == FLASH_UNKNOWN) { + printf("- missing\n"); + } else { + printf("- no sectors to erase\n"); + } + return 1; + } + + if (info->flash_id == FLASH_UNKNOWN) { + printf("Can't erase unknown flash type - aborted\n"); + return 1; + } + + prot = 0; + for (sect = s_first; sect <= s_last; ++sect) { + if (info->protect[sect]) { + prot++; + } + } + + if (prot) { + printf("- Warning: %d protected sectors will not be erased!\n", + prot); + } else { + printf("\n"); + } + + l_sect = -1; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + /* Start erase on unprotected sectors */ + for (sect = s_first, count = 0; sect <= s_last; sect++) { + if (info->protect[sect] == 0) { /* not protected */ + addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[sect]); + + if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_SST) { + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00500050; /* block erase */ + for (i = 0; i < 50; i++) + udelay(1000); /* wait 1 ms */ + } else { + /* + * TODO: fix code + */ + wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); + wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); + wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); + wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00800080); + wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR0, (CFG_FLASH_WORD_SIZE) 0x00AA00AA); + wr_flash_cmd((ulong)addr, CFG_FLASH_ADDR1, (CFG_FLASH_WORD_SIZE) 0x00550055); + wr_flash_cmd((ulong)addr2, 0, (CFG_FLASH_WORD_SIZE) 0x00300030); + udelay(2000000); /* 2 sec */ + wr_flash_cmd((ulong)addr, 0, (CFG_FLASH_WORD_SIZE) 0x00F000F0); + +#if 0 + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00800080; + addr[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[0] = (CFG_FLASH_WORD_SIZE) 0x00300030; /* sector erase */ +#endif + } + l_sect = sect; + printf(".."); + printf(".."); + /* + * Wait for each sector to complete, it's more + * reliable. According to AMD Spec, you must + * issue all erase commands within a specified + * timeout. This has been seen to fail, especially + * if printf()s are included (for debug)!! + */ + wait_for_DQ7_2(info, sect); + count++; + } + } + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* wait at least 80us - let's wait 1 ms */ + udelay(1000); + + /* reset to read mode */ + addr = (CFG_FLASH_WORD_SIZE *) info->start[0]; + addr[0] = (CFG_FLASH_WORD_SIZE) 0x00F000F0; /* reset bank */ + + printf(" done\n"); + + if (count > 0) { + return 0; + } else { + return 1; + } +} + +static int write_word_2(flash_info_t * info, ulong dest, ulong data) +{ + volatile CFG_FLASH_WORD_SIZE *addr2 = (CFG_FLASH_WORD_SIZE *) (info->start[0]); + volatile CFG_FLASH_WORD_SIZE *dest2 = (CFG_FLASH_WORD_SIZE *) dest; + volatile CFG_FLASH_WORD_SIZE *data2 = (CFG_FLASH_WORD_SIZE *) & data; + ulong start; + int i; + + /* Check if Flash is (sufficiently) erased */ + if ((*((vu_long *)dest) & data) != data) { + return (2); + } + + for (i = 0; i < 4 / sizeof(CFG_FLASH_WORD_SIZE); i++) { + int flag; + + /* Disable interrupts which might cause a timeout here */ + flag = disable_interrupts(); + + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00AA00AA; + addr2[CFG_FLASH_ADDR1] = (CFG_FLASH_WORD_SIZE) 0x00550055; + addr2[CFG_FLASH_ADDR0] = (CFG_FLASH_WORD_SIZE) 0x00A000A0; + + dest2[i] = data2[i]; + + /* re-enable interrupts if necessary */ + if (flag) + enable_interrupts(); + + /* data polling for D7 */ + start = get_timer(0); + while ((dest2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080) != + (data2[i] & (CFG_FLASH_WORD_SIZE) 0x00800080)) { + + if (get_timer(start) > CFG_FLASH_WRITE_TOUT) { + return (1); + } + } + } + + return (0); +} +#endif /* CFG_FLASH_2ND_16BIT_DEV */ + +/*----------------------------------------------------------------------- + * Functions + */ +static ulong flash_get_size(vu_long * addr, flash_info_t * info); +static int write_word(flash_info_t * info, ulong dest, ulong data); + +/*----------------------------------------------------------------------- + */ + +unsigned long flash_init(void) +{ + unsigned long total_b = 0; + unsigned long size_b[CFG_MAX_FLASH_BANKS]; + unsigned short index = 0; + int i; + + index = 0; + + DEBUGF("\n"); + DEBUGF("FLASH: Index: %d\n", index); + + /* Init: no FLASHes known */ + for (i = 0; i < CFG_MAX_FLASH_BANKS; ++i) { + flash_info[i].flash_id = FLASH_UNKNOWN; + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + + /* check whether the address is 0 */ + if (flash_addr_table[index][i] == 0) { + continue; + } + + /* call flash_get_size() to initialize sector address */ + size_b[i] = flash_get_size((vu_long *) flash_addr_table[index][i], + &flash_info[i]); + flash_info[i].size = size_b[i]; + if (flash_info[i].flash_id == FLASH_UNKNOWN) { + printf("## Unknown FLASH on Bank %d - Size = 0x%08lx = %ld MB\n", + i, size_b[i], size_b[i] << 20); + flash_info[i].sector_count = -1; + flash_info[i].size = 0; + } + + /* Monitor protection ON by default */ + (void)flash_protect(FLAG_PROTECT_SET, CFG_MONITOR_BASE, + CFG_MONITOR_BASE + CFG_MONITOR_LEN - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#if defined(CFG_ENV_IS_IN_FLASH) && defined(CFG_ENV_ADDR_REDUND) + (void)flash_protect(FLAG_PROTECT_SET, CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SECT_SIZE - 1, + &flash_info[i]); +#endif +#endif + + total_b += flash_info[i].size; + } + + return total_b; +} diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c new file mode 100644 index 0000000..a1b0155 --- /dev/null +++ b/board/amcc/acadia/memory.c @@ -0,0 +1,552 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> + +#define CRAM_BANK0_BASE 0x0 +#define CRAM_DIDR 0x00100000 +#define MICRON_MT45W8MW16BGX_CRAM_ID 0x1b431b43 +#define MICRON_MT45W8MW16BGX_CRAM_ID2 0x13431343 +#define MICRON_DIDR_VENDOR_ID 0x00030003 /* 00011b */ +#define CRAM_DIDR_VENDOR_ID_MASK 0x001f001f /* DIDR[4:0] */ +#define CRAM_DEVID_NOT_SUPPORTED 0x00000000 + +#define PSRAM_PASS 0x50415353 /* "PASS" */ +#define PSRAM_FAIL 0x4641494C /* "FAIL" */ + +static u32 is_cram_inited(void); +static u32 is_cram(void); +static long int cram_init(u32); +static void cram_bcr_write(u32); +void udelay (unsigned long); + +void sdram_init(void) +{ + volatile unsigned long spr_reg; + + /* + * If CRAM not initialized or CRAM looks initialized because this + * is after a warm reboot then set SPRG7 to indicate CRAM needs + * initialization. Note that CRAM is initialized by the SPI and + * NAND preloader. + */ + spr_reg = (volatile unsigned long) mfspr(SPRG6); + if ((is_cram_inited() != 1) || (spr_reg != LOAK_SPL)) { + mtspr(SPRG7, LOAK_NONE); /* "NONE" */ + } +#if 1 + /* + * When running the NAND SPL, the normal EBC configuration is not + * done, so We need to enable EPLD access on EBC_CS_2 and the memory + * on EBC_CS_3 + */ + + /* Enable CPLD - Needed for PSRAM Access */ + + + /* Init SDRAM by setting EBC Bank 3 for PSRAM */ + mtebc(pb1ap, CFG_EBC_PB1AP); + mtebc(pb1cr, CFG_EBC_PB1CR); + + mtebc(pb2ap, CFG_EBC_PB2AP); + mtebc(pb2cr, CFG_EBC_PB2CR); + + /* pre-boot loader code: we are in OCM */ + mtspr(SPRG6, LOAK_SPL); /* "SPL " */ + mtspr(SPRG7, LOAK_OCM); /* "OCM " */ +#endif + return; +} + +static void cram_bcr_write(u32 wr_val) +{ + u32 tmp_reg; + u32 val; + volatile u32 gpio_reg; + + /* # Program CRAM write */ + + /* + * set CRAM_CRE = 0x1 + * set wr_val = wr_val << 2 + */ + gpio_reg = in32(GPIO1_OR); + out32(GPIO1_OR, gpio_reg | 0x00000400); + wr_val = wr_val << 2; + /* wr_val = 0x1c048; */ + + /* + * # stop PLL clock before programming CRAM + * set EPLD0_MUX_CTL.OESPR3 = 1 + * delay 2 + */ + + /* + * # CS1 + * read 0x00200000 + * #shift 2 bit left before write + * set val = wr_val + 0x00200000 + * write dmem val 0 + * read 0x00200000 val + * print val/8x + */ + tmp_reg = in32(0x00200000); + val = wr_val + 0x00200000; + /* val = 0x0021c048; */ + out32(val, 0x0000); + udelay(100000); + val = in32(0x00200000); + + debug("CRAM VAL: %x for CS1 ", val); + + /* + * # CS2 + * read 0x02200000 + * #shift 2 bit left before write + * set val = wr_val + 0x02200000 + * write dmem val 0 + * read 0x02200000 val + * print val/8x + */ + tmp_reg = in32(0x02200000); + val = wr_val + 0x02200000; + /* val = 0x0221c048; */ + out32(val, 0x0000); + udelay(100000); + val = in32(0x02200000); + + debug("CRAM VAL: %x for CS2 ", val); + + /* + * # Start PLL clock before programming CRAM + * set EPLD0_MUX_CTL.OESPR3 = 0 + */ + + /* + * set CRAMCR = 0x1 + */ + gpio_reg = in32(GPIO1_OR); + out32(GPIO1_OR, gpio_reg | 0x00000400); + + /* + * # read CRAM config BCR ( bit19:18 = 10b ) + * #read 0x00200000 + * # 1001_1001_0001_1111 ( 991f ) => + * #10_0110_0100_0111_1100 => 2647c => 0022647c + * #0011_0010_0011_1110 (323e) + * # + */ + + /* + * set EPLD0_MUX_CTL.CRAMCR = 0x0 + */ + gpio_reg = in32(GPIO1_OR); + out32(GPIO1_OR, gpio_reg & 0xFFFFFBFF); + return; +} + +static u32 is_cram_inited() +{ + volatile unsigned long spr_reg; + + /* + * If CRAM is initialized already, then don't reinitialize it again. + * In the case of NAND boot and SPI boot, CRAM will already be + * initialized by the pre-loader + */ + spr_reg = (volatile unsigned long) mfspr(SPRG7); + if (spr_reg == LOAK_CRAM) { + return 1; + } else { + return 0; + } +} + +/****** + * return 0 if not CRAM + * return 1 if CRAM and it's already inited by preloader + * else return cram_id (CRAM Device Identification Register) + ******/ +static u32 is_cram(void) +{ + u32 gpio_TCR, gpio_OSRL, gpio_OR, gpio_ISR1L; + volatile u32 gpio_reg; + volatile u32 cram_id = 0; + + if (is_cram_inited() == 1) { + /* this is CRAM and it is already inited (by preloader) */ + cram_id = 1; + } else { + /* + * # CRAM CLOCK + * set GPIO0_TCR.G8 = 1 + * set GPIO0_OSRL.G8 = 0 + * set GPIO0_OR.G8 = 0 + */ + gpio_reg = in32(GPIO0_TCR); + gpio_TCR = gpio_reg; + out32(GPIO0_TCR, gpio_reg | 0x00800000); + gpio_reg = in32(GPIO0_OSRL); + gpio_OSRL = gpio_reg; + out32(GPIO0_OSRL, gpio_reg & 0xffffbfff); + gpio_reg = in32(GPIO0_OR); + gpio_OR = gpio_reg; + out32(GPIO0_OR, gpio_reg & 0xff7fffff); + + /* + * # CRAM Addreaa Valid + * set GPIO0_TCR.G10 = 1 + * set GPIO0_OSRL.G10 = 0 + * set GPIO0_OR.G10 = 0 + */ + gpio_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, gpio_reg | 0x00200000); + gpio_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, gpio_reg & 0xfffffbff); + gpio_reg = in32(GPIO0_OR); + out32(GPIO0_OR, gpio_reg & 0xffdfffff); + + /* + * # config input (EBC_WAIT) + * set GPIO0_ISR1L.G9 = 1 + * set GPIO0_TCR.G9 = 0 + */ + gpio_reg = in32(GPIO0_ISR1L); + gpio_ISR1L = gpio_reg; + out32(GPIO0_ISR1L, gpio_reg | 0x00001000); + gpio_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, gpio_reg & 0xffbfffff); + + /* + * Enable CRE to read Registers + * set GPIO0_TCR.21 = 1 + * set GPIO1_OR.21 = 1 + */ + gpio_reg = in32(GPIO1_TCR); + out32(GPIO1_TCR, gpio_reg | 0x00000400); + + gpio_reg = in32(GPIO1_OR); + out32(GPIO1_OR, gpio_reg | 0x00000400); + + /* Read Version ID */ + cram_id = (volatile u32) in32(CRAM_BANK0_BASE+CRAM_DIDR); + udelay(100000); + + asm volatile(" sync"); + asm volatile(" eieio"); + + debug("Cram ID: %X ", cram_id); + + switch (cram_id) { + case MICRON_MT45W8MW16BGX_CRAM_ID: + case MICRON_MT45W8MW16BGX_CRAM_ID2: + /* supported CRAM vendor/part */ + break; + case CRAM_DEVID_NOT_SUPPORTED: + default: + /* check for DIDR Vendor ID of Micron */ + if ((cram_id & CRAM_DIDR_VENDOR_ID_MASK) == + MICRON_DIDR_VENDOR_ID) + { + /* supported CRAM vendor */ + break; + } + /* this is not CRAM or not supported CRAM vendor/part */ + cram_id = 0; + /* + * reset the GPIO registers to the values that were + * there before this routine + */ + out32(GPIO0_TCR, gpio_TCR); + out32(GPIO0_OSRL, gpio_OSRL); + out32(GPIO0_OR, gpio_OR); + out32(GPIO0_ISR1L, gpio_ISR1L); + break; + } + } + + return cram_id; +} + +static long int cram_init(u32 already_inited) +{ + volatile u32 tmp_reg; + u32 cram_wr_val; + + if (already_inited == 0) return 0; + + /* + * If CRAM is initialized already, then don't reinitialize it again. + * In the case of NAND boot and SPI boot, CRAM will already be + * initialized by the pre-loader + */ + if (already_inited != 1) { + /* + * #o CRAM Card + * # - CRAMCRE @reg16 = 1; for CRAM to use + * # - CRAMCRE @reg16 = 0; for CRAM to program + * + * # enable CRAM SEL, move from setEPLD.cmd + * set EPLD0_MUX_CTL.OECRAM = 0 + * set EPLD0_MUX_CTL.CRAMCR = 1 + * set EPLD0_ETHRSTBOOT.SLCRAM = 0 + * #end + */ + + /* + * #1. EBC need to program READY, CLK, ADV for ASync mode + * # config output + */ + + /* + * # CRAM CLOCK + * set GPIO0_TCR.G8 = 1 + * set GPIO0_OSRL.G8 = 0 + * set GPIO0_OR.G8 = 0 + */ + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg | 0x00800000); + tmp_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, tmp_reg & 0xffffbfff); + tmp_reg = in32(GPIO0_OR); + out32(GPIO0_OR, tmp_reg & 0xff7fffff); + + /* + * # CRAM Addreaa Valid + * set GPIO0_TCR.G10 = 1 + * set GPIO0_OSRL.G10 = 0 + * set GPIO0_OR.G10 = 0 + */ + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg | 0x00200000); + tmp_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, tmp_reg & 0xfffffbff); + tmp_reg = in32(GPIO0_OR); + out32(GPIO0_OR, tmp_reg & 0xffdfffff); + + /* + * # config input (EBC_WAIT) + * set GPIO0_ISR1L.G9 = 1 + * set GPIO0_TCR.G9 = 0 + */ + tmp_reg = in32(GPIO0_ISR1L); + out32(GPIO0_ISR1L, tmp_reg | 0x00001000); + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg & 0xffbfffff); + + /* + * # config CS4 from GPIO + * set GPIO0_TCR.G0 = 1 + * set GPIO0_OSRL.G0 = 1 + */ + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg | 0x80000000); + tmp_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, tmp_reg | 0x40000000); + + /* + * #2. EBC in Async mode + * # set EBC0_PB1AP = 0x078f0ec0 + * set EBC0_PB1AP = 0x078f1ec0 + * set EBC0_PB2AP = 0x078f1ec0 + */ + mtebc(pb1ap, 0x078F1EC0); + mtebc(pb2ap, 0x078F1EC0); + + /* + * #set EBC0_PB1CR = 0x000bc000 + * #enable CS2 for CRAM + * set EBC0_PB2CR = 0x020bc000 + */ + mtebc(pb1cr, 0x000BC000); + mtebc(pb2cr, 0x020BC000); + + /* + * #3. set CRAM in Sync mode + * #exec cm_bcr_write.cmd { 0x701f } + * #3. set CRAM in Sync mode (full drv strength) + * exec cm_bcr_write.cmd { 0x701F } + */ + cram_wr_val = 0x7012; /* CRAM burst setting */ + cram_bcr_write(cram_wr_val); + + /* + * #4. EBC in Sync mode + * #set EBC0_PB1AP = 0x9f800fc0 + * #set EBC0_PB1AP = 0x900001c0 + * set EBC0_PB2AP = 0x9C0201c0 + * set EBC0_PB2AP = 0x9C0201c0 + */ + mtebc(pb1ap, 0x9C0201C0); + mtebc(pb2ap, 0x9C0201C0); + + /* + * #5. EBC need to program READY, CLK, ADV for Sync mode + * # config output + * set GPIO0_TCR.G8 = 1 + * set GPIO0_OSRL.G8 = 1 + * set GPIO0_TCR.G10 = 1 + * set GPIO0_OSRL.G10 = 1 + */ + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg | 0x00800000); + tmp_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, tmp_reg | 0x00004000); + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg | 0x00200000); + tmp_reg = in32(GPIO0_OSRL); + out32(GPIO0_OSRL, tmp_reg | 0x00000400); + + /* + * # config input + * set GPIO0_ISR1L.G9 = 1 + * set GPIO0_TCR.G9 = 0 + */ + tmp_reg = in32(GPIO0_ISR1L); + out32(GPIO0_ISR1L, tmp_reg | 0x00001000); + tmp_reg = in32(GPIO0_TCR); + out32(GPIO0_TCR, tmp_reg & 0xffbfffff); + + /* + * # config EBC to use RDY + * set SDR0_ULTRA0.EBCREN = 1 + */ + mfsdr(sdrultra0, tmp_reg); + mtsdr(sdrultra0, tmp_reg | 0x04000000); + + /* + * set EPLD0_MUX_CTL.OESPR3 = 0 + */ + mtspr(SPRG7, LOAK_CRAM); /* "CRAM" */ + } /* if (already_inited != 1) */ + + return (64 * 1024 * 1024); +} + +/****** + * return 0 if not PSRAM + * return 1 if is PSRAM + ******/ +static int is_psram(u32 addr) +{ + u32 test_pattern = 0xdeadbeef; + volatile u32 readback; + + if (addr == CFG_SDRAM_BASE) { + /* This is to temp enable OE for PSRAM */ + out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); + udelay(10000); + } + + out32(addr, test_pattern); + asm volatile(" sync"); + asm volatile(" eieio"); + + readback = (volatile u32) in32(addr); + asm volatile(" sync"); + asm volatile(" eieio"); + if (readback == test_pattern) { + return 1; + } else { + return 0; + } +} + +static long int psram_init(void) +{ + u32 readback; + long psramsize = 0; + int i; + + /* This is to temp enable OE for PSRAM */ + out16(EPLD_BASE+EPLD_MUXOE, 0x7f0f); + udelay(10000); + + /* + * PSRAM bank 1: read then write to address 0x00000000 + */ + for (i = 0; i < 100; i++) { + if (is_psram(CFG_SDRAM_BASE + (i*256)) == 1) { + readback = PSRAM_PASS; + } else { + readback = PSRAM_FAIL; + break; + } + } + if (readback == PSRAM_PASS) { + debug("psram_init(bank0): pass\n"); + psramsize = (16 * 1024 * 1024); + } else { + debug("psram_init(bank0): fail\n"); + return 0; + } + +#if 0 + /* + * PSRAM bank 1: read then write to address 0x01000000 + */ + for (i = 0; i < 100; i++) { + if (is_psram((1 << 24) + (i*256)) == 1) { + readback = PSRAM_PASS; + } else { + readback = PSRAM_FAIL; + break; + } + } + if (readback == PSRAM_PASS) { + debug("psram_init(bank1): pass\n"); + psramsize = psramsize + (16 * 1024 * 1024); + } +#endif + + mtspr(SPRG7, LOAK_PSRAM); /* "PSRA" - PSRAM */ + + return psramsize; +} + +long int initdram(int board_type) +{ + long int sram_size; + u32 cram_inited; + + /* Determine Attached Memory Expansion Card*/ + cram_inited = is_cram(); + if (cram_inited != 0) { /* CRAM */ + debug("CRAM Expansion Card attached\n"); + sram_size = cram_init(cram_inited); + } else if (is_psram(CFG_SDRAM_BASE+4) == 1) { /* PSRAM */ + debug("PSRAM Expansion Card attached\n"); + sram_size = psram_init(); + } else { /* no SRAM */ + debug("No Memory Card Attached!!\n"); + sram_size = 0; + } + + return sram_size; +} + +int testdram(void) +{ + return (0); +} diff --git a/board/amcc/acadia/u-boot.lds b/board/amcc/acadia/u-boot.lds new file mode 100644 index 0000000..be03092 --- /dev/null +++ b/board/amcc/acadia/u-boot.lds @@ -0,0 +1,150 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_ARCH(powerpc) +SEARCH_DIR(/lib); SEARCH_DIR(/usr/lib); SEARCH_DIR(/usr/local/lib); SEARCH_DIR(/usr/local/powerpc-any-elf/lib); +/* Do we need any of these for elf? + __DYNAMIC = 0; */ +SECTIONS +{ + .resetvec 0xFFFFFFFC : + { + *(.resetvec) + } = 0xffff + + /* Read-only sections, merged into text segment: */ + . = + SIZEOF_HEADERS; + .interp : { *(.interp) } + .hash : { *(.hash) } + .dynsym : { *(.dynsym) } + .dynstr : { *(.dynstr) } + .rel.text : { *(.rel.text) } + .rela.text : { *(.rela.text) } + .rel.data : { *(.rel.data) } + .rela.data : { *(.rela.data) } + .rel.rodata : { *(.rel.rodata) } + .rela.rodata : { *(.rela.rodata) } + .rel.got : { *(.rel.got) } + .rela.got : { *(.rela.got) } + .rel.ctors : { *(.rel.ctors) } + .rela.ctors : { *(.rela.ctors) } + .rel.dtors : { *(.rel.dtors) } + .rela.dtors : { *(.rela.dtors) } + .rel.bss : { *(.rel.bss) } + .rela.bss : { *(.rela.bss) } + .rel.plt : { *(.rel.plt) } + .rela.plt : { *(.rela.plt) } + .init : { *(.init) } + .plt : { *(.plt) } + .text : + { + /* WARNING - the following is hand-optimized to fit within */ + /* the sector layout of our flash chips! XXX FIXME XXX */ + + cpu/ppc4xx/start.o (.text) + cpu/ppc4xx/kgdb.o (.text) + cpu/ppc4xx/traps.o (.text) + cpu/ppc4xx/interrupts.o (.text) + cpu/ppc4xx/serial.o (.text) + cpu/ppc4xx/cpu_init.o (.text) + cpu/ppc4xx/speed.o (.text) + common/dlmalloc.o (.text) + lib_generic/crc32.o (.text) + lib_ppc/extable.o (.text) + lib_generic/zlib.o (.text) + +/* . = env_offset;*/ +/* common/environment.o(.text)*/ + + *(.text) + *(.fixup) + *(.got1) + } + _etext = .; + PROVIDE (etext = .); + .rodata : + { + *(.rodata) + *(.rodata1) + *(.rodata.str1.4) + *(.eh_frame) + } + .fini : { *(.fini) } =0 + .ctors : { *(.ctors) } + .dtors : { *(.dtors) } + + /* Read-write section, merged into data segment: */ + . = (. + 0x00FF) & 0xFFFFFF00; + _erotext = .; + PROVIDE (erotext = .); + .reloc : + { + *(.got) + _GOT2_TABLE_ = .; + *(.got2) + _FIXUP_TABLE_ = .; + *(.fixup) + } + __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2; + __fixup_entries = (. - _FIXUP_TABLE_)>>2; + + .data : + { + *(.data) + *(.data1) + *(.sdata) + *(.sdata2) + *(.dynamic) + CONSTRUCTORS + } + _edata = .; + PROVIDE (edata = .); + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = .; + __start___ex_table = .; + __ex_table : { *(__ex_table) } + __stop___ex_table = .; + + . = ALIGN(256); + __init_begin = .; + .text.init : { *(.text.init) } + .data.init : { *(.data.init) } + . = ALIGN(256); + __init_end = .; + + __bss_start = .; + .bss : + { + *(.sbss) *(.scommon) + *(.dynbss) + *(.bss) + *(COMMON) + } + _end = . ; + PROVIDE (end = .); +} diff --git a/board/tqm8272/tqm8272.c b/board/tqm8272/tqm8272.c index 8257c77..70d1bb8 100644 --- a/board/tqm8272/tqm8272.c +++ b/board/tqm8272/tqm8272.c @@ -768,7 +768,7 @@ int analyse_hwib (void) p +=1; p +=1; /* connector */ if (*p != '0') { - hw->eeprom = 0x100 << (*p - 'A'); + hw->eeprom = 0x1000 << (*p - 'A'); } p++; diff --git a/cpu/mpc8260/cpu_init.c b/cpu/mpc8260/cpu_init.c index 7dcc949..380d7af 100644 --- a/cpu/mpc8260/cpu_init.c +++ b/cpu/mpc8260/cpu_init.c @@ -129,9 +129,9 @@ void cpu_init_f (volatile immap_t * immr) /* BCR - Bus Configuration Register (4-25) */ #if defined(CFG_BCR_60x) && (CFG_BCR_SINGLE) if (immr->im_siu_conf.sc_bcr & BCR_EBM) { - immr->im_siu_conf.sc_bcr = CFG_BCR_60x; + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_60x, 0x80000010); } else { - immr->im_siu_conf.sc_bcr = CFG_BCR_SINGLE; + immr->im_siu_conf.sc_bcr = SET_VAL_MASK(immr->im_siu_conf.sc_bcr, CFG_BCR_SINGLE, 0x80000010); } #else immr->im_siu_conf.sc_bcr = CFG_BCR; @@ -141,9 +141,9 @@ void cpu_init_f (volatile immap_t * immr) #if defined(CFG_SIUMCR_LOW) && (CFG_SIUMCR_HIGH) cpu_clk = board_get_cpu_clk_f (); if (cpu_clk >= 100000000) { - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_HIGH; + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_HIGH, 0x9f3cc000); } else { - immr->im_siu_conf.sc_siumcr = CFG_SIUMCR_LOW; + immr->im_siu_conf.sc_siumcr = SET_VAL_MASK(immr->im_siu_conf.sc_siumcr, CFG_SIUMCR_LOW, 0x9f3cc000); } #else immr->im_siu_conf.sc_siumcr = CFG_SIUMCR; diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index 1edd6fb..75c6ab2 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -275,22 +275,7 @@ void pci_mpc8250_init (struct pci_controller *hose) | SIUMCR_BCTLC00 | SIUMCR_MMR11; #elif defined(CONFIG_TQM8272) -#if 0 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_LBPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_LBPC11) | - SIUMCR_LBPC01 | - SIUMCR_CS10PC01 | - SIUMCR_APPC10; -#else -#if 0 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr | - SIUMCR_APPC10); -#else - immap->im_siu_conf.sc_siumcr = 0x88000000; -#endif -#endif +/* nothing to do for this Board here */ #else /* * Setting required to enable IRQ1-IRQ7 (SIUMCR [DPPC]), @@ -304,7 +289,6 @@ void pci_mpc8250_init (struct pci_controller *hose) SIUMCR_CS10PC01 | SIUMCR_APPC10; #endif -printf("%s siumcr: %x\n", __FUNCTION__, immap->im_siu_conf.sc_siumcr); /* Make PCI lowest priority */ /* Each 4 bits is a device bus request and the MS 4bits diff --git a/cpu/mpc8xx/serial.c b/cpu/mpc8xx/serial.c index 9d0fc6b..ffc898c 100644 --- a/cpu/mpc8xx/serial.c +++ b/cpu/mpc8xx/serial.c @@ -236,8 +236,7 @@ static int smc_init (void) im->im_ioport.iop_pdpar |= 0x800; im->im_ioport.iop_pddir &= ~0x800; - cp->cp_simode = 0x0000; - cp->cp_simode |= 0x7000; + cp->cp_simode = ((cp->cp_simode & ~0xf000) | 0x7000); #else /* Set up the baud rate generator */ smc_setbrg (); diff --git a/cpu/ppc4xx/4xx_enet.c b/cpu/ppc4xx/4xx_enet.c index 4f55583..cf56581 100644 --- a/cpu/ppc4xx/4xx_enet.c +++ b/cpu/ppc4xx/4xx_enet.c @@ -1333,6 +1333,9 @@ int enetInt (struct eth_device *dev) } } mtdcr (uicsr, MAL_UIC_DEF|EMAC_UIC_DEF|EMAC_UIC_DEF1); /* Clear */ +#if defined(CONFIG_405EZ) + mtsdr (sdricintstat, SDR_ICRX_STAT | SDR_ICTX0_STAT | SDR_ICTX1_STAT); +#endif /* defined(CONFIG_405EZ) */ } while (serviced); diff --git a/cpu/ppc4xx/cpu.c b/cpu/ppc4xx/cpu.c index b02f6f4..2d8740c 100644 --- a/cpu/ppc4xx/cpu.c +++ b/cpu/ppc4xx/cpu.c @@ -47,6 +47,9 @@ void board_reset(void); #if defined(CONFIG_440) #define FREQ_EBC (sys_info.freqEPB) +#elif defined(CONFIG_405EZ) +#define FREQ_EBC ((CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / \ + sys_info.pllExtBusDiv) #else #define FREQ_EBC (sys_info.freqPLB / sys_info.pllExtBusDiv) #endif @@ -209,7 +212,8 @@ int checkcpu (void) puts("AMCC PowerPC 4"); -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) puts("05"); #endif #if defined(CONFIG_440) @@ -257,6 +261,10 @@ int checkcpu (void) puts("EP Rev. B"); break; + case PVR_405EZ_RA: + puts("EZ Rev. A"); + break; + #if defined(CONFIG_440) case PVR_440GP_RB: puts("GP Rev. B"); @@ -386,9 +394,9 @@ int checkcpu (void) } printf (" at %s MHz (PLB=%lu, OPB=%lu, EBC=%lu MHz)\n", strmhz(buf, clock), - sys_info.freqPLB / 1000000, - sys_info.freqPLB / sys_info.pllOpbDiv / 1000000, - FREQ_EBC / 1000000); + sys_info.freqPLB / 1000000, + get_OPB_freq() / 1000000, + FREQ_EBC / 1000000); if (addstr[0] != 0) printf(" %s\n", addstr); @@ -418,7 +426,7 @@ int checkcpu (void) putc('\n'); #endif -#if defined(CONFIG_405EP) +#if defined(CONFIG_405EP) || defined(CONFIG_405EZ) printf (" 16 kB I-Cache 16 kB D-Cache"); #elif defined(CONFIG_440) printf (" 32 kB I-Cache 32 kB D-Cache"); diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index 82ae443..9d1cd13 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -256,7 +256,8 @@ cpu_init_f (void) */ #if (defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) #if (defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405)) + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405)) /* * Move the next instructions into icache, since these modify the flash * we are running from! diff --git a/cpu/ppc4xx/serial.c b/cpu/ppc4xx/serial.c index fab0d95..e62dd9d 100644 --- a/cpu/ppc4xx/serial.c +++ b/cpu/ppc4xx/serial.c @@ -264,7 +264,8 @@ int serial_tstc () #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ defined(CONFIG_440) #if defined(CONFIG_440) @@ -309,7 +310,7 @@ int serial_tstc () #define MFREG(a, d) mfsdr(a, d) #define MTREG(a, d) mtsdr(a, d) #endif /* #if defined(CONFIG_440GP) */ -#elif defined(CONFIG_405EP) +#elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) #define UART0_BASE 0xef600300 #define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f @@ -392,47 +393,95 @@ volatile static serial_buffer_t buf_info; #if defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLOCK) static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv ) + unsigned short *pbdiv) { - sys_info_t sysinfo; + sys_info_t sysinfo; unsigned long div; /* total divisor udiv * bdiv */ unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ unsigned long i; - unsigned long est; /* current estimate */ + unsigned long est; /* current estimate */ - get_sys_info( &sysinfo ); + get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB/(16*baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv<<1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ + udiv = 32; /* Assume lowest possible serial clk */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + diff = 32; /* highest possible */ /* i is the test udiv value -- start with the largest * possible (32) to minimize serial clock and constrain * search to umin. */ - for( i = 32; i > umin; i-- ){ - ibdiv = div/i; + for (i = 32; i > umin; i--) { + ibdiv = div / i; est = i * ibdiv; idiff = (est > div) ? (est-div) : (div-est); - if( idiff == 0 ){ + if (idiff == 0) { udiv = i; break; /* can't do better */ - } - else if( idiff < diff ){ + } else if (idiff < diff) { udiv = i; /* best so far */ diff = idiff; /* update lowest diff*/ } } *pudiv = udiv; - *pbdiv = div/udiv; + *pbdiv = div / udiv; +} + +#elif defined(CONFIG_405EZ) + +static void serial_divs (int baudrate, unsigned long *pudiv, + unsigned short *pbdiv) +{ + sys_info_t sysinfo; + unsigned long div; /* total divisor udiv * bdiv */ + unsigned long umin; /* minimum udiv */ + unsigned short diff; /* smallest diff */ + unsigned long udiv; /* best udiv */ + unsigned short idiff; /* current diff */ + unsigned short ibdiv; /* current bdiv */ + unsigned long i; + unsigned long est; /* current estimate */ + unsigned long plloutb; + u32 reg; + + get_sys_info(&sysinfo); + plloutb = ((CONFIG_SYS_CLK_FREQ * sysinfo.pllFwdDiv * sysinfo.pllFbkDiv) + / sysinfo.pllFwdDivB); + udiv = 256; /* Assume lowest possible serial clk */ + div = plloutb / (16 * baudrate); /* total divisor */ + umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ + diff = 256; /* highest possible */ + + /* i is the test udiv value -- start with the largest + * possible (256) to minimize serial clock and constrain + * search to umin. + */ + for (i = 256; i > umin; i--) { + ibdiv = div / i; + est = i * ibdiv; + idiff = (est > div) ? (est-div) : (div-est); + if (idiff == 0) { + udiv = i; + break; /* can't do better */ + } else if (idiff < diff) { + udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ + } + } + + *pudiv = udiv; + mfcpr(cprperd0, reg); + reg &= ~0x0000ffff; + reg |= ((udiv - 0) << 8) | (udiv - 0); + mtcpr(cprperd0, reg); + *pbdiv = div / udiv; } #endif /* defined(CONFIG_440) && !defined(CFG_EXT_SERIAL_CLK) */ @@ -518,6 +567,10 @@ int serial_init (void) unsigned short bdiv; volatile char val; +#if defined(CONFIG_405EZ) + serial_divs(gd->baudrate, &udiv, &bdiv); + clk = tmp = reg = 0; +#else #ifdef CONFIG_405EP reg = mfdcr(cpc0_ucr) & ~(UCR0_MASK | UCR1_MASK); clk = gd->cpu_clk; @@ -548,9 +601,9 @@ int serial_init (void) reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (cntrl0, reg); #endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; bdiv = (clk + tmp / 2) / tmp; +#endif /* CONFIG_405EZ */ out8(UART_BASE + UART_LCR, 0x80); /* set DLAB bit */ out8(UART_BASE + UART_DLL, bdiv); /* set baudrate divisor */ diff --git a/cpu/ppc4xx/speed.c b/cpu/ppc4xx/speed.c index 06220c3..028b11a 100644 --- a/cpu/ppc4xx/speed.c +++ b/cpu/ppc4xx/speed.c @@ -767,11 +767,119 @@ ulong get_PCI_freq (void) return val; } +#elif defined(CONFIG_405EZ) +void get_sys_info (PPC405_SYS_INFO * sysInfo) +{ + unsigned long cpr_plld; + unsigned long cpr_primad; + unsigned long sysClkPeriodPs = ONE_BILLION / (CONFIG_SYS_CLK_FREQ/1000); + unsigned long primad_cpudv; + unsigned long m; + + /* + * Read PLL Mode registers + */ + mfcpr(cprplld, cpr_plld); + + /* + * Determine forward divider A + */ + sysInfo->pllFwdDiv = ((cpr_plld & PLLD_FWDVA_MASK) >> 16); + + /* + * Determine forward divider B (should be equal to A) + */ + sysInfo->pllFwdDivB = ((cpr_plld & PLLD_FWDVB_MASK) >> 8); + if (sysInfo->pllFwdDivB == 0) { + sysInfo->pllFwdDivB = 8; + } + + /* + * Determine FBK_DIV. + */ + sysInfo->pllFbkDiv = ((cpr_plld & PLLD_FBDV_MASK) >> 24); + if (sysInfo->pllFbkDiv == 0) { + sysInfo->pllFbkDiv = 256; + } + + /* + * Read CPR_PRIMAD register + */ + mfcpr(cprprimad, cpr_primad); + /* + * Determine PLB_DIV. + */ + sysInfo->pllPlbDiv = ((cpr_primad & PRIMAD_PLBDV_MASK) >> 16); + if (sysInfo->pllPlbDiv == 0) { + sysInfo->pllPlbDiv = 16; + } + + /* + * Determine EXTBUS_DIV. + */ + sysInfo->pllExtBusDiv = (cpr_primad & PRIMAD_EBCDV_MASK); + if (sysInfo->pllExtBusDiv == 0) { + sysInfo->pllExtBusDiv = 16; + } + + /* + * Determine OPB_DIV. + */ + sysInfo->pllOpbDiv = ((cpr_primad & PRIMAD_OPBDV_MASK) >> 8); + if (sysInfo->pllOpbDiv == 0) { + sysInfo->pllOpbDiv = 16; + } + + /* + * Determine the M factor + */ + m = sysInfo->pllFbkDiv * sysInfo->pllFwdDivB; + + /* + * Determine VCO clock frequency + */ + sysInfo->freqVCOHz = (1000000000000LL * (unsigned long long)m) / + (unsigned long long)sysClkPeriodPs; + + /* + * Determine CPU clock frequency + */ + primad_cpudv = ((cpr_primad & PRIMAD_CPUDV_MASK) >> 24); + if (primad_cpudv == 0) { + primad_cpudv = 16; + } + + sysInfo->freqProcessor = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / primad_cpudv; + + /* + * Determine PLB clock frequency + */ + sysInfo->freqPLB = (CONFIG_SYS_CLK_FREQ * sysInfo->pllFbkDiv) / sysInfo->pllPlbDiv; +} + +/******************************************** + * get_OPB_freq + * return OPB bus freq in Hz + *********************************************/ +ulong get_OPB_freq (void) +{ + ulong val = 0; + + PPC405_SYS_INFO sys_info; + + get_sys_info (&sys_info); + val = (CONFIG_SYS_CLK_FREQ * sys_info.pllFbkDiv) / sys_info.pllOpbDiv; + + return val; +} + #endif int get_clocks (void) { -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); @@ -796,7 +904,9 @@ ulong get_bus_freq (ulong dummy) { ulong val; -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_440) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440) || defined(CONFIG_405) sys_info_t sys_info; get_sys_info (&sys_info); diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index 54be37c..d918b3e 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -699,7 +699,9 @@ _start: #endif /* CONFIG_IOP480 */ /*****************************************************************************/ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405) || defined(CONFIG_405EP) +#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ + defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ + defined(CONFIG_405) /*----------------------------------------------------------------------- */ /* Clear and set up some registers. */ /*----------------------------------------------------------------------- */ @@ -727,13 +729,13 @@ _start: /*----------------------------------------------------------------------- */ /* Enable two 128MB cachable regions. */ /*----------------------------------------------------------------------- */ - addis r4,r0,0x8000 - addi r4,r4,0x0001 + lis r4,0x8000 + ori r4,r4,0x0001 mticcr r4 /* instruction cache */ isync - addis r4,r0,0x0000 - addi r4,r4,0x0000 + lis r4,0x0000 + ori r4,r4,0x0000 mtdccr r4 /* data cache */ #if !(defined(CFG_EBC_PB0AP) && defined(CFG_EBC_PB0CR)) @@ -755,6 +757,70 @@ _start: #endif /* CONFIG_405EP */ #if defined(CFG_OCM_DATA_ADDR) && defined(CFG_OCM_DATA_SIZE) +/* test-only... (clean up later when NAND booting is supported) */ +#if defined(CONFIG_405EZ) + /******************************************************************** + * Setup OCM - On Chip Memory - PPC405EZ uses OCM Controller V2 + *******************************************************************/ + /* + * We can map the OCM on the PLB3, so map it at + * CFG_OCM_DATA_ADDR + 0x8000 + */ + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x8270 /* 32K Offset, 16K for Bank 1, R/W/Enable */ + mtdcr ocmplb3cr1,r3 /* Set PLB Access */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmplb3cr2,r3 /* Set PLB Access */ + isync + + lis r3,CFG_OCM_DATA_ADDR@h /* OCM location */ + ori r3,r3,CFG_OCM_DATA_ADDR@l + ori r3,r3,0x0270 /* 16K for Bank 1, R/W/Enable */ + mtdcr ocmdscr1, r3 /* Set Data Side */ + mtdcr ocmiscr1, r3 /* Set Instruction Side */ + ori r3,r3,0x4000 /* Add 0x4000 for bank 2 */ + mtdcr ocmdscr2, r3 /* Set Data Side */ + mtdcr ocmiscr2, r3 /* Set Instruction Side */ + addis r3,0,0x0800 /* OCM Data Parity Disable - 1 Wait State */ + mtdcr ocmdsisdpc,r4 + + isync + +#if defined(CONFIG_NAND_SPL) + /* + * 405EZ can boot from NAND Flash. + * If we are booting the SPL (Pre-loader), copy code from + * the mapped 4K NAND Flash to the OCM + */ + li r4,(CFG_NAND_BOOT_SPL_SIZE >> 2) - 1 + mtctr r4 + lis r2,CFG_NAND_BOOT_SPL_SRC@h + ori r2,r2,CFG_NAND_BOOT_SPL_SRC@l + lis r3,CFG_NAND_BOOT_SPL_DST@h + ori r3,r3,CFG_NAND_BOOT_SPL_DST@l +spl_loop: + lwzu r4,4(r2) + stwu r4,4(r3) + bdnz spl_loop + + /* + * Jump to code in OCM Ram + */ + bl 00f +00: mflr r10 + lis r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@h + ori r3,r3,(CFG_NAND_BOOT_SPL_SRC - CFG_NAND_BOOT_SPL_DST)@l + sub r10,r10,r3 + addi r10,r10,28 + mtlr r10 + blr +start_ram: + sync + isync +#endif +#else +/* ...test-only */ /******************************************************************** * Setup OCM - On Chip Memory *******************************************************************/ @@ -774,6 +840,7 @@ _start: addis r4, 0, 0xC000 /* OCM data area enabled */ mtdcr ocmdscntl, r4 isync +#endif /* CONFIG_405EZ */ #endif /*----------------------------------------------------------------------- */ diff --git a/cpu/ppc4xx/usb_ohci.c b/cpu/ppc4xx/usb_ohci.c index ab852c5..c71a6a9 100644 --- a/cpu/ppc4xx/usb_ohci.c +++ b/cpu/ppc4xx/usb_ohci.c @@ -76,7 +76,7 @@ #define m16_swap(x) swap_16(x) #define m32_swap(x) swap_32(x) -#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) +#if defined(CONFIG_405EZ) || defined(CONFIG_440EP) || defined(CONFIG_440EPX) #define ohci_cpu_to_le16(x) (x) #define ohci_cpu_to_le32(x) (x) #else @@ -1601,7 +1601,7 @@ int usb_lowlevel_init(void) gohci.irq = -1; #if defined(CONFIG_440EP) gohci.regs = (struct ohci_regs *)(CFG_PERIPHERAL_BASE | 0x1000); -#elif defined(CONFIG_440EPX) +#elif defined(CONFIG_440EPX) || defined(CFG_USB_HOST) gohci.regs = (struct ohci_regs *)(CFG_USB_HOST); #endif @@ -1625,8 +1625,10 @@ int usb_lowlevel_init(void) ohci_inited = 1; urb_finished = 1; +#if defined(CONFIG_440EP) || defined(CONFIG_440EPX) /* init the device driver */ usb_dev_init(); +#endif return 0; } diff --git a/cpu/ppc4xx/vecnum.h b/cpu/ppc4xx/vecnum.h index 685d48b..bddf9e5 100644 --- a/cpu/ppc4xx/vecnum.h +++ b/cpu/ppc4xx/vecnum.h @@ -231,6 +231,47 @@ #else /* !defined(CONFIG_440) */ +#if defined(CONFIG_405EZ) +#define VECNUM_D0 0 /* DMA channel 0 */ +#define VECNUM_D1 1 /* DMA channel 1 */ +#define VECNUM_D2 2 /* DMA channel 2 */ +#define VECNUM_D3 3 /* DMA channel 3 */ +#define VECNUM_1588 4 /* IEEE 1588 network synchronization */ +#define VECNUM_U0 5 /* UART0 */ +#define VECNUM_U1 6 /* UART1 */ +#define VECNUM_CAN0 7 /* CAN 0 */ +#define VECNUM_CAN1 8 /* CAN 1 */ +#define VECNUM_SPI 9 /* SPI */ +#define VECNUM_IIC0 10 /* I2C */ +#define VECNUM_CHT0 11 /* Chameleon timer high pri interrupt */ +#define VECNUM_CHT1 12 /* Chameleon timer high pri interrupt */ +#define VECNUM_USBH1 13 /* USB Host 1 */ +#define VECNUM_USBH2 14 /* USB Host 2 */ +#define VECNUM_USBDEV 15 /* USB Device */ +#define VECNUM_ETH0 16 /* 10/100 Ethernet interrupt status */ +#define VECNUM_EWU0 17 /* Ethernet wakeup sequence detected */ + +#define VECNUM_MADMAL 18 /* Logical OR of following MadMAL int */ +#define VECNUM_MS 18 /* MAL_SERR_INT */ +#define VECNUM_TXDE 18 /* MAL_TXDE_INT */ +#define VECNUM_RXDE 18 /* MAL_RXDE_INT */ + +#define VECNUM_MTE 19 /* MAL TXEOB */ +#define VECNUM_MTE1 20 /* MAL TXEOB1 */ +#define VECNUM_MRE 21 /* MAL RXEOB */ +#define VECNUM_NAND 22 /* NAND Flash controller */ +#define VECNUM_ADC 23 /* ADC */ +#define VECNUM_DAC 24 /* DAC */ +#define VECNUM_OPB2PLB 25 /* OPB to PLB bridge interrupt */ +#define VECNUM_RESERVED0 26 /* Reserved */ +#define VECNUM_EIR0 27 /* External interrupt 0 */ +#define VECNUM_EIR1 28 /* External interrupt 1 */ +#define VECNUM_EIR2 29 /* External interrupt 2 */ +#define VECNUM_EIR3 30 /* External interrupt 3 */ +#define VECNUM_EIR4 31 /* External interrupt 4 */ + +#else /* !CONFIG_405EZ */ + #define VECNUM_U0 0 /* UART0 */ #define VECNUM_U1 1 /* UART1 */ #define VECNUM_D0 5 /* DMA channel 0 */ @@ -251,6 +292,7 @@ #define VECNUM_EIR4 29 /* External interrupt 4 */ #define VECNUM_EIR5 30 /* External interrupt 5 */ #define VECNUM_EIR6 31 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ #endif /* defined(CONFIG_440) */ diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index ad9fd49..0585962 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -298,6 +298,10 @@ #define SPRN_SPRG1 0x111 /* Special Purpose Register General 1 */ #define SPRN_SPRG2 0x112 /* Special Purpose Register General 2 */ #define SPRN_SPRG3 0x113 /* Special Purpose Register General 3 */ +#define SPRN_SPRG4 0x114 /* Special Purpose Register General 4 */ +#define SPRN_SPRG5 0x115 /* Special Purpose Register General 5 */ +#define SPRN_SPRG6 0x116 /* Special Purpose Register General 6 */ +#define SPRN_SPRG7 0x117 /* Special Purpose Register General 7 */ #define SPRN_SRR0 0x01A /* Save/Restore Register 0 */ #define SPRN_SRR1 0x01B /* Save/Restore Register 1 */ #define SPRN_SRR2 0x3DE /* Save/Restore Register 2 */ @@ -529,6 +533,10 @@ #define SPRG1 SPRN_SPRG1 #define SPRG2 SPRN_SPRG2 #define SPRG3 SPRN_SPRG3 +#define SPRG4 SPRN_SPRG4 +#define SPRG5 SPRN_SPRG5 +#define SPRG6 SPRN_SPRG6 +#define SPRG7 SPRN_SPRG7 #define SRR0 SPRN_SRR0 /* Save and Restore Register 0 */ #define SRR1 SPRN_SRR1 /* Save and Restore Register 1 */ #define SVR SPRN_SVR /* System Version Register */ @@ -731,6 +739,7 @@ #define PVR_405CR_RC 0x40110145 /* same as pc405gp rev e */ #define PVR_405EP_RA 0x51210950 #define PVR_405GPR_RB 0x50910951 +#define PVR_405EZ_RA 0x41511460 #define PVR_440GP_RB 0x40120440 #define PVR_440GP_RC 0x40120481 #define PVR_440EP_RA 0x42221850 diff --git a/include/asm-ppc/u-boot.h b/include/asm-ppc/u-boot.h index 30b44e3..464f6b5 100644 --- a/include/asm-ppc/u-boot.h +++ b/include/asm-ppc/u-boot.h @@ -83,6 +83,7 @@ typedef struct bd_info { defined(CONFIG_405GP) || \ defined(CONFIG_405CR) || \ defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || \ defined(CONFIG_440) unsigned char bi_s_version[4]; /* Version of this structure */ unsigned char bi_r_version[32]; /* Version of the ROM (AMCC) */ @@ -107,7 +108,8 @@ typedef struct bd_info { unsigned char bi_enet3addr[6]; #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || defined (CONFIG_440GX) || \ +#if defined(CONFIG_405GP) || defined(CONFIG_405EP) || \ + defined(CONFIG_405EZ) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) unsigned int bi_opbfreq; /* OPB clock in Hz */ diff --git a/include/configs/acadia.h b/include/configs/acadia.h new file mode 100644 index 0000000..9e02ca3 --- /dev/null +++ b/include/configs/acadia.h @@ -0,0 +1,424 @@ +/* + * (C) Copyright 2007 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * acadia.h - configuration for AMCC Acadia (405EZ) + ***********************************************************************/ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_ACADIA 1 /* Board is Acadia */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_405EZ 1 /* Specifc 405EZ support*/ +#undef CFG_DRAM_TEST /* Disable-takes long time */ +#define CONFIG_SYS_CLK_FREQ 66666666 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ +#define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ + +#define CONFIG_NO_SERIAL_EEPROM +/*#undef CONFIG_NO_SERIAL_EEPROM*/ + +#ifdef CONFIG_NO_SERIAL_EEPROM + +/*---------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 66MHz input clock to the 405EZ. + *---------------------------------------------------------------------------*/ +/* #define PLLMR0_100_100_12 */ +#define PLLMR0_200_133_66 +/* #define PLLMR0_266_160_80 */ +/* #define PLLMR0_333_166_83 */ +#endif + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFE000000 +#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024)/* Reserve 128 kB for malloc() */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ + +/* + * Define here the location of the environment variables (FLASH). + * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only + * supported for backward compatibility. + */ +#if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) + #define CFG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */ +#else + #define CFG_ENV_IS_IN_NAND 1 /* use NAND for environment vars */ +#endif + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "hostname=acadia\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_nfs=run nfsargs addip addtty;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip addtty;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ + "bootm\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ + "bootfile=acadia/uImage\0" \ + "kernel_addr=fff10000\0" \ + "ramdisk_addr=fff20000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 200000 acadia/u-boot.bin\0" \ + "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ + "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "setenv filesize;saveenv\0" \ + "upd=run load;run update\0" \ + "kozio=bootm ffc60000\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#if 0 +#define CONFIG_BOOTDELAY -1 /* autoboot disabled */ +#else +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#endif + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR 0 /* PHY address */ +#define CONFIG_NET_MULTI 1 +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NETCONSOLE /* include NetConsole support */ + +#define CONFIG_USB_OHCI +#define CONFIG_USB_STORAGE + +#if 0 /* test-only */ +#define TEST_ONLY_NAND +#endif + +#ifdef TEST_ONLY_NAND +#define CMD_NAND CFG_CMD_NAND +#else +#define CMD_NAND 0 +#endif + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#define CONFIG_SUPPORT_VFAT + +#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ + CFG_CMD_ASKENV | \ + CFG_CMD_DHCP | \ + CFG_CMD_DTT | \ + CFG_CMD_DIAG | \ + CFG_CMD_EEPROM | \ + CFG_CMD_ELF | \ + CFG_CMD_FAT | \ + CFG_CMD_I2C | \ + CFG_CMD_IRQ | \ + CFG_CMD_MII | \ + CMD_NAND | \ + CFG_CMD_NET | \ + CFG_CMD_NFS | \ + CFG_CMD_PCI | \ + CFG_CMD_PING | \ + CFG_CMD_REGINFO | \ + CFG_CMD_SDRAM | \ + CFG_CMD_USB) + +/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ +#include <cmd_confdefs.h> + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */ +#define CFG_BASE_BAUD 691200 +#define CONFIG_BAUDRATE 115200 + +/* The following table includes the supported baudrates */ +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR (0xa8>>1) +#define CFG_I2C_EEPROM_ADDR_LEN 1 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 3 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 + +/* I2C SYSMON (LM75, AD7414 is almost compatible) */ +#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ +#define CONFIG_DTT_AD7414 1 /* use AD7414 */ +#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */ +#define CFG_DTT_MAX_TEMP 70 +#define CFG_DTT_LOW_TEMP -30 +#define CFG_DTT_HYSTERESIS 3 + +#if 0 /* test-only... */ +/*----------------------------------------------------------------------- + * SPI stuff - Define to include SPI control + *----------------------------------------------------------------------- + */ +#define CONFIG_SPI +#endif + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ + +#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} +#define CFG_MAX_FLASH_BANKS 1 /* number of banks */ +#define CFG_MAX_FLASH_SECT 1024 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef TEST_ONLY_NAND +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CFG_NAND_BASE (CFG_NAND + CFG_NAND_CS) +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#endif + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_DCACHE_SIZE 16384 /* For AMCC 405EZ CPU */ +#define CFG_CACHELINE_SIZE 32 /* ... */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value*/ +#endif + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in data cache) + */ +/* use on chip memory ( OCM ) for temperary stack until sdram is tested */ +#define CFG_TEMP_STACK_OCM 1 + +/* On Chip Memory location */ +#define CFG_OCM_DATA_ADDR 0xF8000000 +#define CFG_OCM_DATA_SIZE 0x4000 /* 16K of onchip SRAM */ +#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SRAM */ +#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */ + +#define CFG_GBL_DATA_SIZE 128 /* size for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + */ +#define CFG_NAND 0xd0000000 +#define CFG_NAND_CS 0 /* NAND chip connected to CSx */ + +/* Memory Bank 0 (Flash) initialization */ +#define CFG_EBC_PB0AP 0x03337200 +#define CFG_EBC_PB0CR 0xfe0bc000 /* BAS=0xFE0,BS=32MB,BU=R/W,BW=32bit */ + +/* Memory Bank 1 (CRAM) initialization */ +#define CFG_EBC_PB1AP 0x030400c0 +#define CFG_EBC_PB1CR 0x000bc000 + +/* Memory Bank 2 (CRAM) initialization */ +#define CFG_EBC_PB2AP 0x030400c0 +#define CFG_EBC_PB2CR 0x020bc000 + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND | 0x1c000) + +/* Memory Bank 4 (CPLD) initialization */ +#define CFG_EBC_PB4AP 0x04006000 +#define CFG_EBC_PB4CR 0x80018000 /* BAS=0x000,BS=16MB,BU=R/W,BW=32bit */ + +#define CFG_EBC_CFG 0xf8400000 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_0 setup (PPC405EZ specific) + * + * GPIO0[0-3] - External Bus Controller CS_4 - CS_7 Outputs + * GPIO0[4] - External Bus Controller Hold Input + * GPIO0[5] - External Bus Controller Priority Input + * GPIO0[6] - External Bus Controller HLDA Output + * GPIO0[7] - External Bus Controller Bus Request Output + * GPIO0[8] - CRAM Clk Output + * GPIO0[9] - External Bus Controller Ready Input + * GPIO0[10] - CRAM Adv Output + * GPIO0[11-24] - NAND Flash Control Data -> Bypasses GPIO when enabled + * GPIO0[25] - External DMA Request Input + * GPIO0[26] - External DMA EOT I/O + * GPIO0[25] - External DMA Ack_n Output + * GPIO0[17-23] - External Interrupts IRQ0 - IRQ6 inputs + * GPIO0[28-30] - Trace Outputs / PWM Inputs + * GPIO0[31] - PWM_8 I/O + */ +#define CFG_GPIO0_TCR 0xC0000000 +#define CFG_GPIO0_OSRL 0x50000000 +#define CFG_GPIO0_OSRH 0x00000055 +#define CFG_GPIO0_ISR1L 0x00000000 +#define CFG_GPIO0_ISR1H 0x00000055 +#define CFG_GPIO0_TSRL 0x00000000 +#define CFG_GPIO0_TSRH 0x00000055 + +/*----------------------------------------------------------------------- + * Definitions for GPIO_1 setup (PPC405EZ specific) + * + * GPIO1[0-6] - PWM_9 to PWM_15 I/O + * GPIO1[7] - PWM_DIV_CLK (Out) / IRQ4 Input + * GPIO1[8] - TS5 Output / DAC_IP_TRIG Input + * GPIO1[9] - TS6 Output / ADC_IP_TRIG Input + * GPIO1[10-12] - UART0 Control Inputs + * GPIO1[13] - UART0_DTR_N Output/IEEE_1588_TS Output/TMRCLK Input + * GPIO1[14] - UART0_RTS_N Output/SPI_SS_2_N Output + * GPIO1[15] - SPI_SS_3_N Output/UART0_RI_N Input + * GPIO1[16] - SPI_SS_1_N Output + * GPIO1[17-20] - Trace Output/External Interrupts IRQ0 - IRQ3 inputs + */ +#define CFG_GPIO1_OSRH 0x55455555 +#define CFG_GPIO1_OSRL 0x40000110 +#define CFG_GPIO1_ISR1H 0x00000000 +#define CFG_GPIO1_ISR1L 0x15555445 +#define CFG_GPIO1_TSRH 0x00000000 +#define CFG_GPIO1_TSRL 0x00000000 +#define CFG_GPIO1_TCR 0xFFFF8014 + +/*----------------------------------------------------------------------- + * EPLD Regs. + */ +#define EPLD_BASE 0x80000000 +#define EPLD_ETHRSTBOOT 0x10 +#define EPLD_CTRL 0x14 +#define EPLD_MUXOE 0x16 + +/* + * State definations + */ +#define LOAK_INIT 0x494e4954 /* ASCII "INIT" */ +#define LOAK_NONE 0x4e4f4e45 /* ASCII "NONE" */ +#define LOAK_CRAM 0x4352414d /* ASCII "CRAM" */ +#define LOAK_PSRAM 0x50535241 /* ASCII "PSRA" - PSRAM */ +#define LOAK_OCM 0x4f434d20 /* ASCII "OCM " */ +#define LOAK_ZERO 0x5a45524f /* ASCII "ZERO" */ +#define LOAK_SPL 0x53504c20 /* ASCII "SPL" */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) + #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ + #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#endif /* __CONFIG_H */ diff --git a/include/ppc405.h b/include/ppc405.h index a49912c..08f10d2 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -117,6 +117,48 @@ /*-----------------------------------------------------------------------------+ | Universal interrupt controller interrupts +-----------------------------------------------------------------------------*/ +#if defined(CONFIG_405EZ) +#define UIC_DMA0 0x80000000 /* DMA chan. 0 */ +#define UIC_DMA1 0x40000000 /* DMA chan. 1 */ +#define UIC_DMA2 0x20000000 /* DMA chan. 2 */ +#define UIC_DMA3 0x10000000 /* DMA chan. 3 */ +#define UIC_1588 0x08000000 /* IEEE 1588 network synchronization */ +#define UIC_UART0 0x04000000 /* UART 0 */ +#define UIC_UART1 0x02000000 /* UART 1 */ +#define UIC_CAN0 0x01000000 /* CAN 0 */ +#define UIC_CAN1 0x00800000 /* CAN 1 */ +#define UIC_SPI 0x00400000 /* SPI */ +#define UIC_IIC 0x00200000 /* IIC */ +#define UIC_CHT0 0x00100000 /* Chameleon timer high pri interrupt */ +#define UIC_CHT1 0x00080000 /* Chameleon timer high pri interrupt */ +#define UIC_USBH1 0x00040000 /* USB Host 1 */ +#define UIC_USBH2 0x00020000 /* USB Host 2 */ +#define UIC_USBDEV 0x00010000 /* USB Device */ +#define UIC_ENET 0x00008000 /* Ethernet interrupt status */ +#define UIC_ENET1 0x00008000 /* dummy define */ +#define UIC_EMAC_WAKE 0x00004000 /* EMAC wake up */ + +#define UIC_MADMAL 0x00002000 /* Logical OR of following MadMAL int */ +#define UIC_MAL_SERR 0x00002000 /* MAL SERR */ +#define UIC_MAL_TXDE 0x00002000 /* MAL TXDE */ +#define UIC_MAL_RXDE 0x00002000 /* MAL RXDE */ + +#define UIC_MAL_TXEOB 0x00001000 /* MAL TXEOB */ +#define UIC_MAL_TXEOB1 0x00000800 /* MAL TXEOB1 */ +#define UIC_MAL_RXEOB 0x00000400 /* MAL RXEOB */ +#define UIC_NAND 0x00000200 /* NAND Flash controller */ +#define UIC_ADC 0x00000100 /* ADC */ +#define UIC_DAC 0x00000080 /* DAC */ +#define UIC_OPB2PLB 0x00000040 /* OPB to PLB bridge interrupt */ +#define UIC_RESERVED0 0x00000020 /* Reserved */ +#define UIC_EXT0 0x00000010 /* External interrupt 0 */ +#define UIC_EXT1 0x00000008 /* External interrupt 1 */ +#define UIC_EXT2 0x00000004 /* External interrupt 2 */ +#define UIC_EXT3 0x00000002 /* External interrupt 3 */ +#define UIC_EXT4 0x00000001 /* External interrupt 4 */ + +#else /* !defined(CONFIG_405EZ) */ + #define UIC_UART0 0x80000000 /* UART 0 */ #define UIC_UART1 0x40000000 /* UART 1 */ #define UIC_IIC 0x20000000 /* IIC */ @@ -144,6 +186,7 @@ #define UIC_EXT4 0x00000004 /* External interrupt 4 */ #define UIC_EXT5 0x00000002 /* External interrupt 5 */ #define UIC_EXT6 0x00000001 /* External interrupt 6 */ +#endif /* defined(CONFIG_405EZ) */ /****************************************************************************** * SDRAM Controller @@ -496,6 +539,325 @@ */ #define VCO_MIN 500 #define VCO_MAX 1000 +#elif defined(CONFIG_405EZ) +/****************************************************************************** + * SDR Registers + ******************************************************************************/ +#define SDR_DCR_BASE 0x0E +#define sdrcfga (SDR_DCR_BASE+0x0) /* ADDR */ +#define sdrcfgd (SDR_DCR_BASE+0x1) /* Data */ + +#define mtsdr(reg, data) mtdcr(sdrcfga,reg);mtdcr(sdrcfgd,data) +#define mfsdr(reg, data) mtdcr(sdrcfga,reg);data = mfdcr(sdrcfgd) + +#define sdrnand0 0x4000 +#define sdrultra0 0x4040 +#define sdrultra1 0x4050 +#define sdricintstat 0x4510 + +#define SDR_NAND0_NDEN 0x80000000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +/****************************************************************************** + * Control + ******************************************************************************/ +#define CNTRL_DCR_BASE 0x0C +#define cprcfga (CNTRL_DCR_BASE+0x0) /* CPR addr reg */ +#define cprcfgd (CNTRL_DCR_BASE+0x1) /* CPR data reg */ + +/* CPR Registers */ +#define cprclkupd 0x020 /* CPR_CLKUPD */ +#define cprpllc 0x040 /* CPR_PLLC */ +#define cprplld 0x060 /* CPR_PLLD */ +#define cprprimad 0x080 /* CPR_PRIMAD */ +#define cprperd0 0x0e0 /* CPR_PERD0 */ +#define cprperd1 0x0e1 /* CPR_PERD1 */ +#define cprperc0 0x180 /* CPR_PERC0 */ +#define cprmisc0 0x181 /* CPR_MISC0 */ +#define cprmisc1 0x182 /* CPR_MISC1 */ + +/* + * Macro for accessing the indirect CPR register + */ +#define mtcpr(reg, data) mtdcr(cprcfga,reg);mtdcr(cprcfgd,data) +#define mfcpr(reg, data) mtdcr(cprcfga,reg);data = mfdcr(cprcfgd) + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#if 0 /* Deprecated */ +#define CNTRL_DCR_BASE 0x0f0 +#define cpc0_pllmr0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ +#define cpc0_boot (CNTRL_DCR_BASE+0x1) /* Clock status register */ +#define cpc0_epctl (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ +#define cpc0_pllmr1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ +#define cpc0_ucr (CNTRL_DCR_BASE+0x5) /* UART control register */ +#define cpc0_pci (CNTRL_DCR_BASE+0x9) /* PCI control register */ + +#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ +#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ +#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ +#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register*/ +#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ +#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ +#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ +#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ +#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ +#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ +#define PLLMR1_FBMUL_DIV_16 0x00000000 +#define PLLMR1_FBMUL_DIV_1 0x00100000 +#define PLLMR1_FBMUL_DIV_2 0x00200000 +#define PLLMR1_FBMUL_DIV_3 0x00300000 +#define PLLMR1_FBMUL_DIV_4 0x00400000 +#define PLLMR1_FBMUL_DIV_5 0x00500000 +#define PLLMR1_FBMUL_DIV_6 0x00600000 +#define PLLMR1_FBMUL_DIV_7 0x00700000 +#define PLLMR1_FBMUL_DIV_8 0x00800000 +#define PLLMR1_FBMUL_DIV_9 0x00900000 +#define PLLMR1_FBMUL_DIV_10 0x00A00000 +#define PLLMR1_FBMUL_DIV_11 0x00B00000 +#define PLLMR1_FBMUL_DIV_12 0x00C00000 +#define PLLMR1_FBMUL_DIV_13 0x00D00000 +#define PLLMR1_FBMUL_DIV_14 0x00E00000 +#define PLLMR1_FBMUL_DIV_15 0x00F00000 + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVA_DIV_8 0x00000000 +#define PLLMR1_FWDVA_DIV_7 0x00010000 +#define PLLMR1_FWDVA_DIV_6 0x00020000 +#define PLLMR1_FWDVA_DIV_5 0x00030000 +#define PLLMR1_FWDVA_DIV_4 0x00040000 +#define PLLMR1_FWDVA_DIV_3 0x00050000 +#define PLLMR1_FWDVA_DIV_2 0x00060000 +#define PLLMR1_FWDVA_DIV_1 0x00070000 +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_EPRCSR register */ +#define CPC0_EPRCSR_E0NFE 0x80000000 +#define CPC0_EPRCSR_E1NFE 0x40000000 +#define CPC0_EPRCSR_E1RPP 0x00000080 +#define CPC0_EPRCSR_E0RPP 0x00000040 +#define CPC0_EPRCSR_E1ERP 0x00000020 +#define CPC0_EPRCSR_E0ERP 0x00000010 +#define CPC0_EPRCSR_E1PCI 0x00000002 +#define CPC0_EPRCSR_E0PCI 0x00000001 + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 + /* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 + /* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 + /* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 + /* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ + /* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 + /* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 + /* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 + /* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 + /* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 + /* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + *------------------------------------------------------------------------------- + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + *------------------------------------------------------------------------------- + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +/* + * PLL Voltage Controlled Oscillator (VCO) definitions + * Maximum and minimum values (in MHz) for correct PLL operation. + */ +#define VCO_MIN 500 +#define VCO_MAX 1000 +#endif /* #if 0 */ #else /* #ifdef CONFIG_405EP */ /****************************************************************************** * Control @@ -578,6 +940,121 @@ /****************************************************************************** * Memory Access Layer ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define MAL_DCR_BASE 0x380 +#define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ +#define malesr (MAL_DCR_BASE+0x01) /* Err Status reg (Read/Clear)*/ +#define malier (MAL_DCR_BASE+0x02) /* Interrupt enable reg */ +#define maldbr (MAL_DCR_BASE+0x03) /* Mal Debug reg (Read only) */ +#define maltxcasr (MAL_DCR_BASE+0x04) /* TX Channel active reg (set)*/ +#define maltxcarr (MAL_DCR_BASE+0x05) /* TX Channel active reg (Reset) */ +#define maltxeobisr (MAL_DCR_BASE+0x06) /* TX End of buffer int status reg */ +#define maltxdeir (MAL_DCR_BASE+0x07) /* TX Descr. Error Int reg */ +/* 0x08-0x0F Reserved */ +#define malrxcasr (MAL_DCR_BASE+0x10) /* RX Channel active reg (set)*/ +#define malrxcarr (MAL_DCR_BASE+0x11) /* RX Channel active reg (Reset) */ +#define malrxeobisr (MAL_DCR_BASE+0x12) /* RX End of buffer int status reg */ +#define malrxdeir (MAL_DCR_BASE+0x13) /* RX Descr. Error Int reg */ +/* 0x14-0x1F Reserved */ +#define maltxctp0r (MAL_DCR_BASE+0x20) /* TX 0 Channel table ptr reg */ +#define maltxctp1r (MAL_DCR_BASE+0x21) /* TX 1 Channel table ptr reg */ +#define maltxctp2r (MAL_DCR_BASE+0x22) /* TX 2 Channel table ptr reg */ +#define maltxctp3r (MAL_DCR_BASE+0x23) /* TX 3 Channel table ptr reg */ +#define maltxctp4r (MAL_DCR_BASE+0x24) /* TX 4 Channel table ptr reg */ +#define maltxctp5r (MAL_DCR_BASE+0x25) /* TX 5 Channel table ptr reg */ +#define maltxctp6r (MAL_DCR_BASE+0x26) /* TX 6 Channel table ptr reg */ +#define maltxctp7r (MAL_DCR_BASE+0x27) /* TX 7 Channel table ptr reg */ +#define maltxctp8r (MAL_DCR_BASE+0x28) /* TX 8 Channel table ptr reg */ +#define maltxctp9r (MAL_DCR_BASE+0x29) /* TX 9 Channel table ptr reg */ +#define maltxctp10r (MAL_DCR_BASE+0x2A) /* TX 10 Channel table ptr reg */ +#define maltxctp11r (MAL_DCR_BASE+0x2B) /* TX 11 Channel table ptr reg */ +#define maltxctp12r (MAL_DCR_BASE+0x2C) /* TX 12 Channel table ptr reg */ +#define maltxctp13r (MAL_DCR_BASE+0x2D) /* TX 13 Channel table ptr reg */ +#define maltxctp14r (MAL_DCR_BASE+0x2E) /* TX 14 Channel table ptr reg */ +#define maltxctp15r (MAL_DCR_BASE+0x2F) /* TX 15 Channel table ptr reg */ +#define maltxctp16r (MAL_DCR_BASE+0x30) /* TX 16 Channel table ptr reg */ +#define maltxctp17r (MAL_DCR_BASE+0x31) /* TX 17 Channel table ptr reg */ +#define maltxctp18r (MAL_DCR_BASE+0x32) /* TX 18 Channel table ptr reg */ +#define maltxctp19r (MAL_DCR_BASE+0x33) /* TX 19 Channel table ptr reg */ +#define maltxctp20r (MAL_DCR_BASE+0x34) /* TX 20 Channel table ptr reg */ +#define maltxctp21r (MAL_DCR_BASE+0x35) /* TX 21 Channel table ptr reg */ +#define maltxctp22r (MAL_DCR_BASE+0x36) /* TX 22 Channel table ptr reg */ +#define maltxctp23r (MAL_DCR_BASE+0x37) /* TX 23 Channel table ptr reg */ +#define maltxctp24r (MAL_DCR_BASE+0x38) /* TX 24 Channel table ptr reg */ +#define maltxctp25r (MAL_DCR_BASE+0x39) /* TX 25 Channel table ptr reg */ +#define maltxctp26r (MAL_DCR_BASE+0x3A) /* TX 26 Channel table ptr reg */ +#define maltxctp27r (MAL_DCR_BASE+0x3B) /* TX 27 Channel table ptr reg */ +#define maltxctp28r (MAL_DCR_BASE+0x3C) /* TX 28 Channel table ptr reg */ +#define maltxctp29r (MAL_DCR_BASE+0x3D) /* TX 29 Channel table ptr reg */ +#define maltxctp30r (MAL_DCR_BASE+0x3E) /* TX 30 Channel table ptr reg */ +#define maltxctp31r (MAL_DCR_BASE+0x3F) /* TX 31 Channel table ptr reg */ +#define malrxctp0r (MAL_DCR_BASE+0x40) /* RX 0 Channel table ptr reg */ +#define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table ptr reg */ +#define malrxctp2r (MAL_DCR_BASE+0x42) /* RX 2 Channel table ptr reg */ +#define malrxctp3r (MAL_DCR_BASE+0x43) /* RX 3 Channel table ptr reg */ +#define malrxctp4r (MAL_DCR_BASE+0x44) /* RX 4 Channel table ptr reg */ +#define malrxctp5r (MAL_DCR_BASE+0x45) /* RX 5 Channel table ptr reg */ +#define malrxctp6r (MAL_DCR_BASE+0x46) /* RX 6 Channel table ptr reg */ +#define malrxctp7r (MAL_DCR_BASE+0x47) /* RX 7 Channel table ptr reg */ +#define malrxctp8r (MAL_DCR_BASE+0x48) /* RX 8 Channel table ptr reg */ +#define malrxctp9r (MAL_DCR_BASE+0x49) /* RX 9 Channel table ptr reg */ +#define malrxctp10r (MAL_DCR_BASE+0x4A) /* RX 10 Channel table ptr reg */ +#define malrxctp11r (MAL_DCR_BASE+0x4B) /* RX 11 Channel table ptr reg */ +#define malrxctp12r (MAL_DCR_BASE+0x4C) /* RX 12 Channel table ptr reg */ +#define malrxctp13r (MAL_DCR_BASE+0x4D) /* RX 13 Channel table ptr reg */ +#define malrxctp14r (MAL_DCR_BASE+0x4E) /* RX 14 Channel table ptr reg */ +#define malrxctp15r (MAL_DCR_BASE+0x4F) /* RX 15 Channel table ptr reg */ +#define malrxctp16r (MAL_DCR_BASE+0x50) /* RX 16 Channel table ptr reg */ +#define malrxctp17r (MAL_DCR_BASE+0x51) /* RX 17 Channel table ptr reg */ +#define malrxctp18r (MAL_DCR_BASE+0x52) /* RX 18 Channel table ptr reg */ +#define malrxctp19r (MAL_DCR_BASE+0x53) /* RX 19 Channel table ptr reg */ +#define malrxctp20r (MAL_DCR_BASE+0x54) /* RX 20 Channel table ptr reg */ +#define malrxctp21r (MAL_DCR_BASE+0x55) /* RX 21 Channel table ptr reg */ +#define malrxctp22r (MAL_DCR_BASE+0x56) /* RX 22 Channel table ptr reg */ +#define malrxctp23r (MAL_DCR_BASE+0x57) /* RX 23 Channel table ptr reg */ +#define malrxctp24r (MAL_DCR_BASE+0x58) /* RX 24 Channel table ptr reg */ +#define malrxctp25r (MAL_DCR_BASE+0x59) /* RX 25 Channel table ptr reg */ +#define malrxctp26r (MAL_DCR_BASE+0x5A) /* RX 26 Channel table ptr reg */ +#define malrxctp27r (MAL_DCR_BASE+0x5B) /* RX 27 Channel table ptr reg */ +#define malrxctp28r (MAL_DCR_BASE+0x5C) /* RX 28 Channel table ptr reg */ +#define malrxctp29r (MAL_DCR_BASE+0x5D) /* RX 29 Channel table ptr reg */ +#define malrxctp30r (MAL_DCR_BASE+0x5E) /* RX 30 Channel table ptr reg */ +#define malrxctp31r (MAL_DCR_BASE+0x5F) /* RX 31 Channel table ptr reg */ +#define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ +#define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#define malrcbs2 (MAL_DCR_BASE+0x62) /* RX 2 Channel buffer size reg */ +#define malrcbs3 (MAL_DCR_BASE+0x63) /* RX 3 Channel buffer size reg */ +#define malrcbs4 (MAL_DCR_BASE+0x64) /* RX 4 Channel buffer size reg */ +#define malrcbs5 (MAL_DCR_BASE+0x65) /* RX 5 Channel buffer size reg */ +#define malrcbs6 (MAL_DCR_BASE+0x66) /* RX 6 Channel buffer size reg */ +#define malrcbs7 (MAL_DCR_BASE+0x67) /* RX 7 Channel buffer size reg */ +#define malrcbs8 (MAL_DCR_BASE+0x68) /* RX 8 Channel buffer size reg */ +#define malrcbs9 (MAL_DCR_BASE+0x69) /* RX 9 Channel buffer size reg */ +#define malrcbs10 (MAL_DCR_BASE+0x6A) /* RX 10 Channel buffer size reg */ +#define malrcbs11 (MAL_DCR_BASE+0x6B) /* RX 11 Channel buffer size reg */ +#define malrcbs12 (MAL_DCR_BASE+0x6C) /* RX 12 Channel buffer size reg */ +#define malrcbs13 (MAL_DCR_BASE+0x6D) /* RX 13 Channel buffer size reg */ +#define malrcbs14 (MAL_DCR_BASE+0x6E) /* RX 14 Channel buffer size reg */ +#define malrcbs15 (MAL_DCR_BASE+0x6F) /* RX 15 Channel buffer size reg */ +#define malrcbs16 (MAL_DCR_BASE+0x70) /* RX 16 Channel buffer size reg */ +#define malrcbs17 (MAL_DCR_BASE+0x71) /* RX 17 Channel buffer size reg */ +#define malrcbs18 (MAL_DCR_BASE+0x72) /* RX 18 Channel buffer size reg */ +#define malrcbs19 (MAL_DCR_BASE+0x73) /* RX 19 Channel buffer size reg */ +#define malrcbs20 (MAL_DCR_BASE+0x74) /* RX 20 Channel buffer size reg */ +#define malrcbs21 (MAL_DCR_BASE+0x75) /* RX 21 Channel buffer size reg */ +#define malrcbs22 (MAL_DCR_BASE+0x76) /* RX 22 Channel buffer size reg */ +#define malrcbs23 (MAL_DCR_BASE+0x77) /* RX 23 Channel buffer size reg */ +#define malrcbs24 (MAL_DCR_BASE+0x78) /* RX 24 Channel buffer size reg */ +#define malrcbs25 (MAL_DCR_BASE+0x79) /* RX 25 Channel buffer size reg */ +#define malrcbs26 (MAL_DCR_BASE+0x7A) /* RX 26 Channel buffer size reg */ +#define malrcbs27 (MAL_DCR_BASE+0x7B) /* RX 27 Channel buffer size reg */ +#define malrcbs28 (MAL_DCR_BASE+0x7C) /* RX 28 Channel buffer size reg */ +#define malrcbs29 (MAL_DCR_BASE+0x7D) /* RX 29 Channel buffer size reg */ +#define malrcbs30 (MAL_DCR_BASE+0x7E) /* RX 30 Channel buffer size reg */ +#define malrcbs31 (MAL_DCR_BASE+0x7F) /* RX 31 Channel buffer size reg */ + +#else /* !defined(CONFIG_405EZ) */ + #define MAL_DCR_BASE 0x180 #define malmcr (MAL_DCR_BASE+0x00) /* MAL Config reg */ #define malesr (MAL_DCR_BASE+0x01) /* Error Status reg (Read/Clear) */ @@ -598,6 +1075,7 @@ #define malrxctp1r (MAL_DCR_BASE+0x41) /* RX 1 Channel table pointer reg */ #define malrcbs0 (MAL_DCR_BASE+0x60) /* RX 0 Channel buffer size reg */ #define malrcbs1 (MAL_DCR_BASE+0x61) /* RX 1 Channel buffer size reg */ +#endif /* defined(CONFIG_405EZ) */ /*----------------------------------------------------------------------------- | IIC Register Offsets @@ -635,15 +1113,76 @@ /****************************************************************************** * On Chip Memory ******************************************************************************/ +#if defined(CONFIG_405EZ) +#define OCM_DCR_BASE 0x020 +#define ocmplb3cr1 (OCM_DCR_BASE+0x00) /* OCM PLB3 Bank 1 Config Reg */ +#define ocmplb3cr2 (OCM_DCR_BASE+0x01) /* OCM PLB3 Bank 2 Config Reg */ +#define ocmplb3bear (OCM_DCR_BASE+0x02) /* OCM PLB3 Bus Error Add Reg */ +#define ocmplb3besr0 (OCM_DCR_BASE+0x03) /* OCM PLB3 Bus Error Stat Reg 0 */ +#define ocmplb3besr1 (OCM_DCR_BASE+0x04) /* OCM PLB3 Bus Error Stat Reg 1 */ +#define ocmcid (OCM_DCR_BASE+0x05) /* OCM Core ID */ +#define ocmrevid (OCM_DCR_BASE+0x06) /* OCM Revision ID */ +#define ocmplb3dpc (OCM_DCR_BASE+0x07) /* OCM PLB3 Data Parity Check */ +#define ocmdscr1 (OCM_DCR_BASE+0x08) /* OCM D-side Bank 1 Config Reg */ +#define ocmdscr2 (OCM_DCR_BASE+0x09) /* OCM D-side Bank 2 Config Reg */ +#define ocmiscr1 (OCM_DCR_BASE+0x0A) /* OCM I-side Bank 1 Config Reg */ +#define ocmiscr2 (OCM_DCR_BASE+0x0B) /* OCM I-side Bank 2 Config Reg */ +#define ocmdsisdpc (OCM_DCR_BASE+0x0C) /* OCM D-side/I-side Data Par Chk*/ +#define ocmdsisbear (OCM_DCR_BASE+0x0D) /* OCM D-side/I-side Bus Err Addr*/ +#define ocmdsisbesr (OCM_DCR_BASE+0x0E) /* OCM D-side/I-side Bus Err Stat*/ +#else #define OCM_DCR_BASE 0x018 #define ocmisarc (OCM_DCR_BASE+0x00) /* OCM I-side address compare reg */ #define ocmiscntl (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ #define ocmdsarc (OCM_DCR_BASE+0x02) /* OCM D-side address compare reg */ #define ocmdscntl (OCM_DCR_BASE+0x03) /* OCM D-side control reg */ +#endif /* CONFIG_405EZ */ /****************************************************************************** * GPIO macro register defines ******************************************************************************/ +#if defined(CONFIG_405EZ) +/* Only the 405EZ has 2 GPIOs */ +#define GPIO_BASE 0xEF600700 +#define GPIO0_OR (GPIO_BASE+0x0) +#define GPIO0_TCR (GPIO_BASE+0x4) +#define GPIO0_OSRL (GPIO_BASE+0x8) +#define GPIO0_OSRH (GPIO_BASE+0xC) +#define GPIO0_TSRL (GPIO_BASE+0x10) +#define GPIO0_TSRH (GPIO_BASE+0x14) +#define GPIO0_ODR (GPIO_BASE+0x18) +#define GPIO0_IR (GPIO_BASE+0x1C) +#define GPIO0_RR1 (GPIO_BASE+0x20) +#define GPIO0_RR2 (GPIO_BASE+0x24) +#define GPIO0_RR3 (GPIO_BASE+0x28) +#define GPIO0_ISR1L (GPIO_BASE+0x30) +#define GPIO0_ISR1H (GPIO_BASE+0x34) +#define GPIO0_ISR2L (GPIO_BASE+0x38) +#define GPIO0_ISR2H (GPIO_BASE+0x3C) +#define GPIO0_ISR3L (GPIO_BASE+0x40) +#define GPIO0_ISR3H (GPIO_BASE+0x44) + +#define GPIO1_BASE 0xEF600800 +#define GPIO1_OR (GPIO1_BASE+0x0) +#define GPIO1_TCR (GPIO1_BASE+0x4) +#define GPIO1_OSRL (GPIO1_BASE+0x8) +#define GPIO1_OSRH (GPIO1_BASE+0xC) +#define GPIO1_TSRL (GPIO1_BASE+0x10) +#define GPIO1_TSRH (GPIO1_BASE+0x14) +#define GPIO1_ODR (GPIO1_BASE+0x18) +#define GPIO1_IR (GPIO1_BASE+0x1C) +#define GPIO1_RR1 (GPIO1_BASE+0x20) +#define GPIO1_RR2 (GPIO1_BASE+0x24) +#define GPIO1_RR3 (GPIO1_BASE+0x28) +#define GPIO1_ISR1L (GPIO1_BASE+0x30) +#define GPIO1_ISR1H (GPIO1_BASE+0x34) +#define GPIO1_ISR2L (GPIO1_BASE+0x38) +#define GPIO1_ISR2H (GPIO1_BASE+0x3C) +#define GPIO1_ISR3L (GPIO1_BASE+0x40) +#define GPIO1_ISR3H (GPIO1_BASE+0x44) + +#else /* !405EZ */ + #define GPIO_BASE 0xEF600700 #define GPIO0_OR (GPIO_BASE+0x0) #define GPIO0_TCR (GPIO_BASE+0x4) @@ -660,6 +1199,7 @@ #define GPIO0_ISR2H (GPIO_BASE+0x38) #define GPIO0_ISR2L (GPIO_BASE+0x3C) +#endif /* CONFIG_405EZ */ /* * Macro for accessing the indirect EBC register diff --git a/include/ppc4xx_enet.h b/include/ppc4xx_enet.h index 43c5ca4..3d8ca09 100644 --- a/include/ppc4xx_enet.h +++ b/include/ppc4xx_enet.h @@ -130,13 +130,13 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440GX) -#define EMAC_NUM_DEV 4 +#define EMAC_NUM_DEV 4 #elif (defined(CONFIG_440) || defined(CONFIG_405EP)) && \ defined(CONFIG_NET_MULTI) && \ !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) -#define EMAC_NUM_DEV 2 +#define EMAC_NUM_DEV 2 #else -#define EMAC_NUM_DEV 1 +#define EMAC_NUM_DEV 1 #endif #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ @@ -153,16 +153,16 @@ typedef struct emac_4xx_hw_st { /*ZMII Bridge Register addresses */ #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0D00) #else -#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) +#define ZMII_BASE (CFG_PERIPHERAL_BASE + 0x0780) #endif -#define ZMII_FER (ZMII_BASE) -#define ZMII_SSR (ZMII_BASE + 4) -#define ZMII_SMIISR (ZMII_BASE + 8) +#define ZMII_FER (ZMII_BASE) +#define ZMII_SSR (ZMII_BASE + 4) +#define ZMII_SMIISR (ZMII_BASE + 8) -#define ZMII_RMII 0x22000000 -#define ZMII_MDI0 0x80000000 +#define ZMII_RMII 0x22000000 +#define ZMII_MDI0 0x80000000 /* ZMII FER Register Bit Definitions */ #define ZMII_FER_DIS (0x0) @@ -299,49 +299,41 @@ typedef struct emac_4xx_hw_st { #if defined(CONFIG_440) #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0E00) #else -#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) +#define EMAC_BASE (CFG_PERIPHERAL_BASE + 0x0800) #endif #else -#define EMAC_BASE 0xEF600800 +#if defined(CONFIG_405EZ) +#define EMAC_BASE 0xEF600900 +#else +#define EMAC_BASE 0xEF600800 +#endif #endif -#define EMAC_M0 (EMAC_BASE) -#define EMAC_M1 (EMAC_BASE + 4) -#define EMAC_TXM0 (EMAC_BASE + 8) -#define EMAC_TXM1 (EMAC_BASE + 12) -#define EMAC_RXM (EMAC_BASE + 16) -#define EMAC_ISR (EMAC_BASE + 20) -#define EMAC_IER (EMAC_BASE + 24) -#define EMAC_IAH (EMAC_BASE + 28) -#define EMAC_IAL (EMAC_BASE + 32) -#define EMAC_VLAN_TPID_REG (EMAC_BASE + 36) -#define EMAC_VLAN_TCI_REG (EMAC_BASE + 40) +#define EMAC_M0 (EMAC_BASE) +#define EMAC_M1 (EMAC_BASE + 4) +#define EMAC_TXM0 (EMAC_BASE + 8) +#define EMAC_TXM1 (EMAC_BASE + 12) +#define EMAC_RXM (EMAC_BASE + 16) +#define EMAC_ISR (EMAC_BASE + 20) +#define EMAC_IER (EMAC_BASE + 24) +#define EMAC_IAH (EMAC_BASE + 28) +#define EMAC_IAL (EMAC_BASE + 32) #define EMAC_PAUSE_TIME_REG (EMAC_BASE + 44) -#define EMAC_IND_HASH_1 (EMAC_BASE + 48) -#define EMAC_IND_HASH_2 (EMAC_BASE + 52) -#define EMAC_IND_HASH_3 (EMAC_BASE + 56) -#define EMAC_IND_HASH_4 (EMAC_BASE + 60) -#define EMAC_GRP_HASH_1 (EMAC_BASE + 64) -#define EMAC_GRP_HASH_2 (EMAC_BASE + 68) -#define EMAC_GRP_HASH_3 (EMAC_BASE + 72) -#define EMAC_GRP_HASH_4 (EMAC_BASE + 76) -#define EMAC_LST_SRC_LOW (EMAC_BASE + 80) -#define EMAC_LST_SRC_HI (EMAC_BASE + 84) #define EMAC_I_FRAME_GAP_REG (EMAC_BASE + 88) -#define EMAC_STACR (EMAC_BASE + 92) -#define EMAC_TRTR (EMAC_BASE + 96) -#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) +#define EMAC_STACR (EMAC_BASE + 92) +#define EMAC_TRTR (EMAC_BASE + 96) +#define EMAC_RX_HI_LO_WMARK (EMAC_BASE + 100) /* bit definitions */ /* MODE REG 0 */ -#define EMAC_M0_RXI (0x80000000) -#define EMAC_M0_TXI (0x40000000) -#define EMAC_M0_SRST (0x20000000) -#define EMAC_M0_TXE (0x10000000) -#define EMAC_M0_RXE (0x08000000) -#define EMAC_M0_WKE (0x04000000) +#define EMAC_M0_RXI (0x80000000) +#define EMAC_M0_TXI (0x40000000) +#define EMAC_M0_SRST (0x20000000) +#define EMAC_M0_TXE (0x10000000) +#define EMAC_M0_RXE (0x08000000) +#define EMAC_M0_WKE (0x04000000) /* on 440GX EMAC_MR1 has a different layout! */ #if defined(CONFIG_440GX) || \ @@ -351,23 +343,23 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_FDE (0x80000000) #define EMAC_M1_ILE (0x40000000) #define EMAC_M1_VLE (0x20000000) -#define EMAC_M1_EIFC (0x10000000) -#define EMAC_M1_APP (0x08000000) -#define EMAC_M1_RSVD (0x06000000) -#define EMAC_M1_IST (0x01000000) -#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS (0x00400000) -#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K (0x00100000) -#define EMAC_M1_RFS_1K (0x00080000) -#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_8K (0x00040000) -#define EMAC_M1_TX_FIFO_4K (0x00030000) +#define EMAC_M1_EIFC (0x10000000) +#define EMAC_M1_APP (0x08000000) +#define EMAC_M1_RSVD (0x06000000) +#define EMAC_M1_IST (0x01000000) +#define EMAC_M1_MF_1000MBPS (0x00800000) /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS (0x00400000) +#define EMAC_M1_RFS_16K (0x00280000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_8K (0x00200000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_4K (0x00180000) /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K (0x00100000) +#define EMAC_M1_RFS_1K (0x00080000) +#define EMAC_M1_TX_FIFO_16K (0x00050000) /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_8K (0x00040000) +#define EMAC_M1_TX_FIFO_4K (0x00030000) #define EMAC_M1_TX_FIFO_2K (0x00020000) -#define EMAC_M1_TX_FIFO_1K (0x00010000) -#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ +#define EMAC_M1_TX_FIFO_1K (0x00010000) +#define EMAC_M1_TR_MULTI (0x00008000) /* 0'x for single packet */ #define EMAC_M1_MWSW (0x00007000) #define EMAC_M1_JUMBO_ENABLE (0x00000800) #define EMAC_M1_IPPA (0x000007c0) @@ -378,34 +370,34 @@ typedef struct emac_4xx_hw_st { #define EMAC_M1_RSVD1 (0x00000007) #else /* defined(CONFIG_440GX) */ /* EMAC_MR1 is the same on 405GP, 405GPr, 405EP, 440GP, 440EP */ -#define EMAC_M1_FDE 0x80000000 -#define EMAC_M1_ILE 0x40000000 -#define EMAC_M1_VLE 0x20000000 -#define EMAC_M1_EIFC 0x10000000 -#define EMAC_M1_APP 0x08000000 -#define EMAC_M1_AEMI 0x02000000 -#define EMAC_M1_IST 0x01000000 -#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ -#define EMAC_M1_MF_100MBPS 0x00400000 -#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ -#define EMAC_M1_RFS_2K 0x00200000 -#define EMAC_M1_RFS_1K 0x00100000 -#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ -#define EMAC_M1_TX_FIFO_1K 0x00040000 -#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ -#define EMAC_M1_TR0_MULTI 0x00008000 -#define EMAC_M1_TR1_DEPEND 0x00004000 -#define EMAC_M1_TR1_MULTI 0x00002000 +#define EMAC_M1_FDE 0x80000000 +#define EMAC_M1_ILE 0x40000000 +#define EMAC_M1_VLE 0x20000000 +#define EMAC_M1_EIFC 0x10000000 +#define EMAC_M1_APP 0x08000000 +#define EMAC_M1_AEMI 0x02000000 +#define EMAC_M1_IST 0x01000000 +#define EMAC_M1_MF_1000MBPS 0x00800000 /* 0's for 10MBPS */ +#define EMAC_M1_MF_100MBPS 0x00400000 +#define EMAC_M1_RFS_4K 0x00300000 /* ~4k for 512 byte */ +#define EMAC_M1_RFS_2K 0x00200000 +#define EMAC_M1_RFS_1K 0x00100000 +#define EMAC_M1_TX_FIFO_2K 0x00080000 /* 0's for 512 byte */ +#define EMAC_M1_TX_FIFO_1K 0x00040000 +#define EMAC_M1_TR0_DEPEND 0x00010000 /* 0'x for single packet */ +#define EMAC_M1_TR0_MULTI 0x00008000 +#define EMAC_M1_TR1_DEPEND 0x00004000 +#define EMAC_M1_TR1_MULTI 0x00002000 #if defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define EMAC_M1_JUMBO_ENABLE 0x00001000 +#define EMAC_M1_JUMBO_ENABLE 0x00001000 #endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ #endif /* defined(CONFIG_440GX) */ /* Transmit Mode Register 0 */ -#define EMAC_TXM0_GNP0 (0x80000000) -#define EMAC_TXM0_GNP1 (0x40000000) -#define EMAC_TXM0_GNPD (0x20000000) -#define EMAC_TXM0_FC (0x10000000) +#define EMAC_TXM0_GNP0 (0x80000000) +#define EMAC_TXM0_GNP1 (0x40000000) +#define EMAC_TXM0_GNPD (0x20000000) +#define EMAC_TXM0_FC (0x10000000) /* Receive Mode Register */ #define EMAC_RMR_SP (0x80000000) @@ -427,39 +419,38 @@ typedef struct emac_4xx_hw_st { #define EMAC_ISR_PP (0x01000000) #define EMAC_ISR_BP (0x00800000) #define EMAC_ISR_RP (0x00400000) -#define EMAC_ISR_SE (0x00200000) -#define EMAC_ISR_SYE (0x00100000) -#define EMAC_ISR_BFCS (0x00080000) -#define EMAC_ISR_PTLE (0x00040000) -#define EMAC_ISR_ORE (0x00020000) -#define EMAC_ISR_IRE (0x00010000) -#define EMAC_ISR_DBDM (0x00000200) -#define EMAC_ISR_DB0 (0x00000100) -#define EMAC_ISR_SE0 (0x00000080) -#define EMAC_ISR_TE0 (0x00000040) -#define EMAC_ISR_DB1 (0x00000020) -#define EMAC_ISR_SE1 (0x00000010) -#define EMAC_ISR_TE1 (0x00000008) -#define EMAC_ISR_MOS (0x00000002) -#define EMAC_ISR_MOF (0x00000001) - +#define EMAC_ISR_SE (0x00200000) +#define EMAC_ISR_SYE (0x00100000) +#define EMAC_ISR_BFCS (0x00080000) +#define EMAC_ISR_PTLE (0x00040000) +#define EMAC_ISR_ORE (0x00020000) +#define EMAC_ISR_IRE (0x00010000) +#define EMAC_ISR_DBDM (0x00000200) +#define EMAC_ISR_DB0 (0x00000100) +#define EMAC_ISR_SE0 (0x00000080) +#define EMAC_ISR_TE0 (0x00000040) +#define EMAC_ISR_DB1 (0x00000020) +#define EMAC_ISR_SE1 (0x00000010) +#define EMAC_ISR_TE1 (0x00000008) +#define EMAC_ISR_MOS (0x00000002) +#define EMAC_ISR_MOF (0x00000001) /* STA CONTROL REG */ -#define EMAC_STACR_OC (0x00008000) -#define EMAC_STACR_PHYE (0x00004000) +#define EMAC_STACR_OC (0x00008000) +#define EMAC_STACR_PHYE (0x00004000) #ifdef CONFIG_IBM_EMAC4_V4 /* EMAC4 V4 changed bit setting */ -#define EMAC_STACR_INDIRECT_MODE (0x00002000) -#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ -#define EMAC_STACR_READ (0x00001000) /* $BUC */ -#define EMAC_STACR_OP_MASK (0x00001800) -#define EMAC_STACR_MDIO_ADDR (0x00000000) -#define EMAC_STACR_MDIO_WRITE (0x00000800) -#define EMAC_STACR_MDIO_READ (0x00001800) -#define EMAC_STACR_MDIO_READ_INC (0x00001000) +#define EMAC_STACR_INDIRECT_MODE (0x00002000) +#define EMAC_STACR_WRITE (0x00000800) /* $BUC */ +#define EMAC_STACR_READ (0x00001000) /* $BUC */ +#define EMAC_STACR_OP_MASK (0x00001800) +#define EMAC_STACR_MDIO_ADDR (0x00000000) +#define EMAC_STACR_MDIO_WRITE (0x00000800) +#define EMAC_STACR_MDIO_READ (0x00001800) +#define EMAC_STACR_MDIO_READ_INC (0x00001000) #else -#define EMAC_STACR_WRITE (0x00002000) -#define EMAC_STACR_READ (0x00001000) +#define EMAC_STACR_WRITE (0x00002000) +#define EMAC_STACR_READ (0x00001000) #endif #define EMAC_STACR_CLK_83MHZ (0x00000800) /* 0's for 50Mhz */ @@ -467,9 +458,9 @@ typedef struct emac_4xx_hw_st { #define EMAC_STACR_CLK_100MHZ (0x00000C00) /* Transmit Request Threshold Register */ -#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ -#define EMAC_TRTR_192 (0x10000000) -#define EMAC_TRTR_128 (0x01000000) +#define EMAC_TRTR_256 (0x18000000) /* 0's for 64 Bytes */ +#define EMAC_TRTR_192 (0x10000000) +#define EMAC_TRTR_128 (0x01000000) /* the follwing defines are for the MadMAL status and control registers. */ /* For bits 0..5 look at the mal.h file */ diff --git a/post/cache.c b/post/cache.c deleted file mode 100644 index 501465c..0000000 --- a/post/cache.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* Cache test - * - * This test verifies the CPU data and instruction cache using - * several test scenarios. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include <watchdog.h> - -#if CONFIG_POST & CFG_POST_CACHE - -#define CACHE_POST_SIZE 1024 - -extern int cache_post_test1 (char *, unsigned int); -extern int cache_post_test2 (char *, unsigned int); -extern int cache_post_test3 (char *, unsigned int); -extern int cache_post_test4 (char *, unsigned int); -extern int cache_post_test5 (void); -extern int cache_post_test6 (void); - -int cache_post_test (int flags) -{ - int ints = disable_interrupts (); - int res = 0; - static char ta[CACHE_POST_SIZE + 0xf]; - char *testarea = (char *) (((unsigned long) ta + 0xf) & ~0xf); - - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test1 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test2 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test3 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test4 (testarea, CACHE_POST_SIZE); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test5 (); - WATCHDOG_RESET (); - if (res == 0) - res = cache_post_test6 (); - - WATCHDOG_RESET (); - if (ints) - enable_interrupts (); - return res; -} - -#endif /* CONFIG_POST & CFG_POST_CACHE */ -#endif /* CONFIG_POST */ diff --git a/post/cache_8xx.S b/post/cache_8xx.S deleted file mode 100644 index 2d41b55..0000000 --- a/post/cache_8xx.S +++ /dev/null @@ -1,495 +0,0 @@ -/* - * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> - -#ifdef CONFIG_POST -#if defined(CONFIG_MPC823) || \ - defined(CONFIG_MPC850) || \ - defined(CONFIG_MPC855) || \ - defined(CONFIG_MPC860) || \ - defined(CONFIG_MPC862) - -#include <post.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> - -#if CONFIG_POST & CFG_POST_CACHE - - .text - -cache_post_dinvalidate: - lis r10, IDC_INVALL@h - mtspr DC_CST, r10 - blr - -cache_post_iinvalidate: - lis r10, IDC_INVALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ddisable: - lis r10, IDC_DISABLE@h - mtspr DC_CST, r10 - blr - -cache_post_dwb: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_CFWT@h - mtspr DC_CST, r10 - blr - -cache_post_dwt: - lis r10, IDC_ENABLE@h - mtspr DC_CST, r10 - lis r10, DC_SFWT@h - mtspr DC_CST, r10 - blr - -cache_post_idisable: - lis r10, IDC_DISABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ienable: - lis r10, IDC_ENABLE@h - mtspr IC_CST, r10 - isync - blr - -cache_post_iunlock: - lis r10, IDC_UNALL@h - mtspr IC_CST, r10 - isync - blr - -cache_post_ilock: - mtspr IC_ADR, r3 - lis r10, IDC_LDLCK@h - mtspr IC_CST, r10 - isync - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the negative pattern to a cached area - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test1 -cache_post_test1: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back or write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * turn off the data cache - * write the negative pattern to the area - * turn on the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test2 -cache_post_test2: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - bl cache_post_ddisable - bl cache_post_dinvalidate - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-through mode - * invalidate the data cache - * write the zero pattern to a cached area - * flush the data cache - * write the negative pattern to the area - * turn off the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test3 -cache_post_test3: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwt - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -/* - * turn on the data cache - * switch the data cache to write-back mode - * invalidate the data cache - * write the negative pattern to a cached area - * flush the data cache - * write the zero pattern to the area - * invalidate the data cache - * read the area - * - * The negative pattern must be read at the last step - */ - .global cache_post_test4 -cache_post_test4: - mflr r0 - stw r0, 4(r1) - - stwu r3, -4(r1) - stwu r4, -4(r1) - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Write the negative pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0xff - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_dwb - bl cache_post_dinvalidate - - /* Write the zero pattern to the test area */ - lwz r0, 0(r1) - mtctr r0 - li r0, 0 - lwz r3, 4(r1) - subi r3, r3, 1 -1: - stbu r0, 1(r3) - bdnz 1b - - bl cache_post_ddisable - bl cache_post_dinvalidate - - /* Read the test area */ - lwz r0, 0(r1) - mtctr r0 - lwz r4, 4(r1) - subi r4, r4, 1 - li r3, 0 -1: - lbzu r0, 1(r4) - cmpli cr0, r0, 0xff - beq 2f - li r3, -1 - b 3f -2: - bdnz 1b -3: - - addi r1, r1, 8 - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test5_1: - li r3, 0 -cache_post_test5_2: - li r3, -1 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed -*/ - .global cache_post_test5 -cache_post_test5: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test5_reloc */ - bl cache_post_test5_reloc -cache_post_test5_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test5_data */ - lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Lock the branch instruction */ - lis r3, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_data - cache_post_test5_reloc)@l - add r3, r3, r9 - bl cache_post_ilock - - /* Replace the test instruction */ - lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h - ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h - ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test5_data: - nop - - bl cache_post_iunlock - - lwz r0, 4(r1) - mtlr r0 - blr - -cache_post_test6_1: - li r3, -1 -cache_post_test6_2: - li r3, 0 - -/* - * turn on the instruction cache - * unlock the entire instruction cache - * invalidate the instruction cache - * lock a branch instruction in the instruction cache - * replace the branch instruction with "nop" - * jump to the branch instruction - * check that the branch instruction was executed - */ - .global cache_post_test6 -cache_post_test6: - mflr r0 - stw r0, 4(r1) - - bl cache_post_ienable - bl cache_post_iunlock - bl cache_post_iinvalidate - - /* Compute r9 = cache_post_test6_reloc */ - bl cache_post_test6_reloc -cache_post_test6_reloc: - mflr r9 - - /* Copy the test instruction to cache_post_test6_data */ - lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Replace the test instruction */ - lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h - ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l - add r3, r3, r9 - lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h - ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l - add r4, r4, r9 - lwz r0, 0(r3) - stw r0, 0(r4) - - bl cache_post_iinvalidate - - /* Execute to the test instruction */ -cache_post_test6_data: - nop - - lwz r0, 4(r1) - mtlr r0 - blr - -#endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ -#endif /* CONFIG_POST & CFG_POST_CACHE */ -#endif /* CONFIG_POST */ diff --git a/post/codec.c b/post/codec.c deleted file mode 100644 index e881752..0000000 --- a/post/codec.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004 - * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CODEC test - * - * This test verifies the connection and performs a memory test - * on any connected codec(s). The meat of the work is done - * in the board specific function. - */ - -#ifdef CONFIG_POST - -#include <post.h> - -#if CONFIG_POST & CFG_POST_CODEC - -extern int board_post_codec(int flags); - -int codec_post_test (int flags) -{ - return board_post_codec(flags); -} - -#endif /* CONFIG_POST & CFG_POST_CODEC */ -#endif /* CONFIG_POST */ diff --git a/post/cpu.c b/post/cpu.c deleted file mode 100644 index 1f2ded2..0000000 --- a/post/cpu.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * - * This test checks the arithmetic logic unit (ALU) of CPU. - * It tests independently various groups of instructions using - * run-time modification of the code to reduce the memory footprint. - * For more details refer to post/cpu/ *.c files. - */ - -#ifdef CONFIG_POST - -#include <watchdog.h> -#include <post.h> - -#if CONFIG_POST & CFG_POST_CPU - -extern int cpu_post_test_cmp (void); -extern int cpu_post_test_cmpi (void); -extern int cpu_post_test_two (void); -extern int cpu_post_test_twox (void); -extern int cpu_post_test_three (void); -extern int cpu_post_test_threex (void); -extern int cpu_post_test_threei (void); -extern int cpu_post_test_andi (void); -extern int cpu_post_test_srawi (void); -extern int cpu_post_test_rlwnm (void); -extern int cpu_post_test_rlwinm (void); -extern int cpu_post_test_rlwimi (void); -extern int cpu_post_test_store (void); -extern int cpu_post_test_load (void); -extern int cpu_post_test_cr (void); -extern int cpu_post_test_b (void); -extern int cpu_post_test_multi (void); -extern int cpu_post_test_string (void); -extern int cpu_post_test_complex (void); - -ulong cpu_post_makecr (long v) -{ - ulong cr = 0; - - if (v < 0) - cr |= 0x80000000; - if (v > 0) - cr |= 0x40000000; - if (v == 0) - cr |= 0x20000000; - - return cr; -} - -int cpu_post_test (int flags) -{ - int ic = icache_status (); - int ret = 0; - - WATCHDOG_RESET(); - if (ic) - icache_disable (); - - if (ret == 0) - ret = cpu_post_test_cmp (); - if (ret == 0) - ret = cpu_post_test_cmpi (); - if (ret == 0) - ret = cpu_post_test_two (); - if (ret == 0) - ret = cpu_post_test_twox (); - WATCHDOG_RESET(); - if (ret == 0) - ret = cpu_post_test_three (); - if (ret == 0) - ret = cpu_post_test_threex (); - if (ret == 0) - ret = cpu_post_test_threei (); - if (ret == 0) - ret = cpu_post_test_andi (); - WATCHDOG_RESET(); - if (ret == 0) - ret = cpu_post_test_srawi (); - if (ret == 0) - ret = cpu_post_test_rlwnm (); - if (ret == 0) - ret = cpu_post_test_rlwinm (); - if (ret == 0) - ret = cpu_post_test_rlwimi (); - WATCHDOG_RESET(); - if (ret == 0) - ret = cpu_post_test_store (); - if (ret == 0) - ret = cpu_post_test_load (); - if (ret == 0) - ret = cpu_post_test_cr (); - if (ret == 0) - ret = cpu_post_test_b (); - WATCHDOG_RESET(); - if (ret == 0) - ret = cpu_post_test_multi (); - WATCHDOG_RESET(); - if (ret == 0) - ret = cpu_post_test_string (); - if (ret == 0) - ret = cpu_post_test_complex (); - WATCHDOG_RESET(); - - if (ic) - icache_enable (); - - WATCHDOG_RESET(); - - return ret; -} - -#endif /* CONFIG_POST & CFG_POST_CPU */ -#endif /* CONFIG_POST */ diff --git a/post/cpu/andi.c b/post/cpu/andi.c deleted file mode 100644 index 7ddf2ab..0000000 --- a/post/cpu/andi.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Logic instructions: andi., andis. - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_andi_s -{ - ulong cmd; - ulong op1; - ushort op2; - ulong res; -} cpu_post_andi_table[] = -{ - { - OP_ANDI_, - 0x80008000, - 0xffff, - 0x00008000 - }, - { - OP_ANDIS_, - 0x80008000, - 0xffff, - 0x80000000 - }, -}; -static unsigned int cpu_post_andi_size = - sizeof (cpu_post_andi_table) / sizeof (struct cpu_post_andi_s); - -int cpu_post_test_andi (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_andi_size && ret == 0; i++) - { - struct cpu_post_andi_s *test = cpu_post_andi_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11IX(test->cmd, reg1, reg0, test->op2), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - cpu_post_exec_21 (codecr, & cr, & res, test->op1); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at andi test %d !\n", i); - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/asm.S b/post/cpu/asm.S deleted file mode 100644 index a0815a4..0000000 --- a/post/cpu/asm.S +++ /dev/null @@ -1,346 +0,0 @@ -/* - * Copyright (C) 2002 Wolfgang Denk <wd@denx.de> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <config.h> - -#ifdef CONFIG_POST - -#include <post.h> -#include <ppc_asm.tmpl> -#include <ppc_defs.h> -#include <asm/cache.h> - -#if CONFIG_POST & CFG_POST_CPU - -/* void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); */ - .global cpu_post_exec_02 -cpu_post_exec_02: - mflr r0 - stwu r0, -4(r1) - - subi r1, r1, 104 - stmw r6, 0(r1) - - mtlr r3 - mr r3, r4 - mr r4, r5 - blrl - - lmw r6, 0(r1) - addi r1, r1, 104 - - lwz r0, 0(r1) - addi r1, r1, 4 - mtlr r0 - blr - -/* void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, ulong op4); */ - .global cpu_post_exec_04 -cpu_post_exec_04: - mflr r0 - stwu r0, -4(r1) - - subi r1, r1, 96 - stmw r8, 0(r1) - - mtlr r3 - mr r3, r4 - mr r4, r5 - mr r5, r6 - mtxer r7 - blrl - - lmw r8, 0(r1) - addi r1, r1, 96 - - lwz r0, 0(r1) - addi r1, r1, 4 - mtlr r0 - blr - -/* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ - .global cpu_post_exec_12 -cpu_post_exec_12: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - - mtlr r3 - mr r3, r5 - mr r4, r6 - blrl - - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 4(r1) - addi r1, r1, 8 - mtlr r0 - blr - -/* void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); */ - .global cpu_post_exec_11 -cpu_post_exec_11: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - - mtlr r3 - mr r3, r5 - blrl - - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 4(r1) - addi r1, r1, 8 - mtlr r0 - blr - -/* void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); */ - .global cpu_post_exec_21 -cpu_post_exec_21: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r5, -4(r1) - - li r0, 0 - mtxer r0 - lwz r0, 0(r4) - mtcr r0 - - mtlr r3 - mr r3, r6 - blrl - - mfcr r0 - lwz r4, 4(r1) - stw r0, 0(r4) - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 8(r1) - addi r1, r1, 12 - mtlr r0 - blr - -/* void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, - ulong op2); */ - .global cpu_post_exec_22 -cpu_post_exec_22: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r5, -4(r1) - - li r0, 0 - mtxer r0 - lwz r0, 0(r4) - mtcr r0 - - mtlr r3 - mr r3, r6 - mr r4, r7 - blrl - - mfcr r0 - lwz r4, 4(r1) - stw r0, 0(r4) - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 8(r1) - addi r1, r1, 12 - mtlr r0 - blr - -/* void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); */ - .global cpu_post_exec_12w -cpu_post_exec_12w: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - - mtlr r3 - lwz r3, 0(r4) - mr r4, r5 - mr r5, r6 - blrl - - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 4(r1) - addi r1, r1, 8 - mtlr r0 - blr - -/* void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); */ - .global cpu_post_exec_11w -cpu_post_exec_11w: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - - mtlr r3 - lwz r3, 0(r4) - mr r4, r5 - blrl - - lwz r4, 0(r1) - stw r3, 0(r4) - - lwz r0, 4(r1) - addi r1, r1, 8 - mtlr r0 - blr - -/* void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); */ - .global cpu_post_exec_22w -cpu_post_exec_22w: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r6, -4(r1) - - mtlr r3 - lwz r3, 0(r4) - mr r4, r5 - blrl - - lwz r4, 4(r1) - stw r3, 0(r4) - lwz r4, 0(r1) - stw r5, 0(r4) - - lwz r0, 8(r1) - addi r1, r1, 12 - mtlr r0 - blr - -/* void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); */ - .global cpu_post_exec_21w -cpu_post_exec_21w: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r5, -4(r1) - - mtlr r3 - lwz r3, 0(r4) - blrl - - lwz r5, 4(r1) - stw r3, 0(r5) - lwz r5, 0(r1) - stw r4, 0(r5) - - lwz r0, 8(r1) - addi r1, r1, 12 - mtlr r0 - blr - -/* void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); */ - .global cpu_post_exec_21x -cpu_post_exec_21x: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r5, -4(r1) - - mtlr r3 - mr r3, r6 - blrl - - lwz r5, 4(r1) - stw r3, 0(r5) - lwz r5, 0(r1) - stw r4, 0(r5) - - lwz r0, 8(r1) - addi r1, r1, 12 - mtlr r0 - blr - -/* void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, - ulong cr); */ - .global cpu_post_exec_31 -cpu_post_exec_31: - mflr r0 - stwu r0, -4(r1) - stwu r4, -4(r1) - stwu r5, -4(r1) - stwu r6, -4(r1) - - mtlr r3 - lwz r3, 0(r4) - lwz r4, 0(r5) - mr r6, r7 - blrl - - lwz r7, 8(r1) - stw r3, 0(r7) - lwz r7, 4(r1) - stw r4, 0(r7) - lwz r7, 0(r1) - stw r5, 0(r7) - - lwz r0, 12(r1) - addi r1, r1, 16 - mtlr r0 - blr - -/* int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); */ - .global cpu_post_complex_1_asm -cpu_post_complex_1_asm: - li r9,0 - cmpw r9,r7 - bge cpu_post_complex_1_done - mtctr r7 -cpu_post_complex_1_loop: - mullw r0,r3,r4 - subf r0,r5,r0 - divw r0,r0,r6 - add r9,r9,r0 - bdnz cpu_post_complex_1_loop -cpu_post_complex_1_done: - mr r3,r9 - blr - -/* int cpu_post_complex_2_asm (int x, int n); */ - .global cpu_post_complex_2_asm -cpu_post_complex_2_asm: - mr. r0,r4 - mtctr r0 - mr r0,r3 - li r3,1 - li r4,1 - blelr -cpu_post_complex_2_loop: - mullw r3,r3,r0 - add r3,r3,r4 - bdnz cpu_post_complex_2_loop -blr - -#endif -#endif diff --git a/post/cpu/b.c b/post/cpu/b.c deleted file mode 100644 index b4b17c8..0000000 --- a/post/cpu/b.c +++ /dev/null @@ -1,197 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Branch instructions: b, bl, bc - * - * The first 2 instructions (b, bl) are verified by jumping - * to a fixed address and checking whether control was transfered - * to that very point. For the bl instruction the value of the - * link register is checked as well (using mfspr). - * To verify the bc instruction various combinations of the BI/BO - * fields, the CTR and the condition register values are - * checked. The list of such combinations is pre-built and - * linked in U-Boot at build time. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); -extern void cpu_post_exec_31 (ulong *code, ulong *ctr, ulong *lr, ulong *jump, - ulong cr); - -static int cpu_post_test_bc (ulong cmd, ulong bo, ulong bi, - int pjump, int dec, int link, ulong pctr, ulong cr) -{ - int ret = 0; - ulong lr = 0; - ulong ctr = pctr; - ulong jump; - - unsigned long code[] = - { - ASM_MTCR(6), - ASM_MFLR(6), - ASM_MTCTR(3), - ASM_MTLR(4), - ASM_LI(5, 1), - ASM_3O(cmd, bo, bi, 8), - ASM_LI(5, 0), - ASM_MFCTR(3), - ASM_MFLR(4), - ASM_MTLR(6), - ASM_BLR, - }; - - cpu_post_exec_31 (code, &ctr, &lr, &jump, cr); - - if (ret == 0) - ret = pjump == jump ? 0 : -1; - if (ret == 0) - { - if (dec) - ret = pctr == ctr + 1 ? 0 : -1; - else - ret = pctr == ctr ? 0 : -1; - } - if (ret == 0) - { - if (link) - ret = lr == (ulong) code + 24 ? 0 : -1; - else - ret = lr == 0 ? 0 : -1; - } - - return ret; -} - -int cpu_post_test_b (void) -{ - int ret = 0; - unsigned int i; - - if (ret == 0) - { - ulong code[] = - { - ASM_MFLR(4), - ASM_MTLR(3), - ASM_B(4), - ASM_MFLR(3), - ASM_MTLR(4), - ASM_BLR, - }; - ulong res; - - cpu_post_exec_11 (code, &res, 0); - - ret = res == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at b1 test !\n"); - } - } - - if (ret == 0) - { - ulong code[] = - { - ASM_MFLR(4), - ASM_MTLR(3), - ASM_BL(4), - ASM_MFLR(3), - ASM_MTLR(4), - ASM_BLR, - }; - ulong res; - - cpu_post_exec_11 (code, &res, 0); - - ret = res == (ulong)code + 12 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at b2 test !\n"); - } - } - - if (ret == 0) - { - ulong cc, cd; - int cond; - ulong ctr; - int link; - - i = 0; - - for (cc = 0; cc < 4 && ret == 0; cc++) - { - for (cd = 0; cd < 4 && ret == 0; cd++) - { - for (link = 0; link <= 1 && ret == 0; link++) - { - for (cond = 0; cond <= 1 && ret == 0; cond++) - { - for (ctr = 1; ctr <= 2 && ret == 0; ctr++) - { - int dec = cd < 2; - int cr = cond ? 0x80000000 : 0x00000000; - int jumpc = cc >= 2 || - (cc == 0 && !cond) || - (cc == 1 && cond); - int jumpd = cd >= 2 || - (cd == 0 && ctr != 1) || - (cd == 1 && ctr == 1); - int jump = jumpc && jumpd; - - ret = cpu_post_test_bc (link ? OP_BCL : OP_BC, - (cc << 3) + (cd << 1), 0, jump, dec, link, - ctr, cr); - - if (ret != 0) - { - post_log ("Error at b3 test %d !\n", i); - } - - i++; - } - } - } - } - } - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/cmp.c b/post/cpu/cmp.c deleted file mode 100644 index 789a24c..0000000 --- a/post/cpu/cmp.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Integer compare instructions: cmpw, cmplw - * - * To verify these instructions the test runs them with - * different combinations of operands, reads the condition - * register value and compares it with the expected one. - * The test contains a pre-built table - * containing the description of each test case: the instruction, - * the values of the operands, the condition field to save - * the result in and the expected result. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); - -static struct cpu_post_cmp_s -{ - ulong cmd; - ulong op1; - ulong op2; - ulong cr; - ulong res; -} cpu_post_cmp_table[] = -{ - { - OP_CMPW, - 123, - 123, - 2, - 0x02 - }, - { - OP_CMPW, - 123, - 133, - 3, - 0x08 - }, - { - OP_CMPW, - 123, - -133, - 4, - 0x04 - }, - { - OP_CMPLW, - 123, - 123, - 2, - 0x02 - }, - { - OP_CMPLW, - 123, - -133, - 3, - 0x08 - }, - { - OP_CMPLW, - 123, - 113, - 4, - 0x04 - }, -}; -static unsigned int cpu_post_cmp_size = - sizeof (cpu_post_cmp_table) / sizeof (struct cpu_post_cmp_s); - -int cpu_post_test_cmp (void) -{ - int ret = 0; - unsigned int i; - - for (i = 0; i < cpu_post_cmp_size && ret == 0; i++) - { - struct cpu_post_cmp_s *test = cpu_post_cmp_table + i; - unsigned long code[] = - { - ASM_2C(test->cmd, test->cr, 3, 4), - ASM_MFCR(3), - ASM_BLR - }; - ulong res; - - cpu_post_exec_12 (code, & res, test->op1, test->op2); - - ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at cmp test %d !\n", i); - } - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/cmpi.c b/post/cpu/cmpi.c deleted file mode 100644 index e0c2aaf..0000000 --- a/post/cpu/cmpi.c +++ /dev/null @@ -1,133 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Integer compare instructions: cmpwi, cmplwi - * - * To verify these instructions the test runs them with - * different combinations of operands, reads the condition - * register value and compares it with the expected one. - * The test contains a pre-built table - * containing the description of each test case: the instruction, - * the values of the operands, the condition field to save - * the result in and the expected result. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); - -static struct cpu_post_cmpi_s -{ - ulong cmd; - ulong op1; - ushort op2; - ulong cr; - ulong res; -} cpu_post_cmpi_table[] = -{ - { - OP_CMPWI, - 123, - 123, - 2, - 0x02 - }, - { - OP_CMPWI, - 123, - 133, - 3, - 0x08 - }, - { - OP_CMPWI, - 123, - -133, - 4, - 0x04 - }, - { - OP_CMPLWI, - 123, - 123, - 2, - 0x02 - }, - { - OP_CMPLWI, - 123, - -133, - 3, - 0x08 - }, - { - OP_CMPLWI, - 123, - 113, - 4, - 0x04 - }, -}; -static unsigned int cpu_post_cmpi_size = - sizeof (cpu_post_cmpi_table) / sizeof (struct cpu_post_cmpi_s); - -int cpu_post_test_cmpi (void) -{ - int ret = 0; - unsigned int i; - - for (i = 0; i < cpu_post_cmpi_size && ret == 0; i++) - { - struct cpu_post_cmpi_s *test = cpu_post_cmpi_table + i; - unsigned long code[] = - { - ASM_1IC(test->cmd, test->cr, 3, test->op2), - ASM_MFCR(3), - ASM_BLR - }; - ulong res; - - cpu_post_exec_11 (code, & res, test->op1); - - ret = ((res >> (28 - 4 * test->cr)) & 0xe) == test->res ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at cmpi test %d !\n", i); - } - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/complex.c b/post/cpu/complex.c deleted file mode 100644 index 033584b..0000000 --- a/post/cpu/complex.c +++ /dev/null @@ -1,126 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Complex calculations - * - * The calculations in this test are just a combination of simpler - * calculations, but probably under different timing conditions, etc. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern int cpu_post_complex_1_asm (int a1, int a2, int a3, int a4, int n); -extern int cpu_post_complex_2_asm (int x, int n); - - /* - * n - * SUM (a1 * a2 - a3) / a4 = n * result - * i=1 - */ -static int cpu_post_test_complex_1 (void) -{ - int a1 = 666; - int a2 = 667; - int a3 = 668; - int a4 = 66; - int n = 100; - int result = 6720; /* (a1 * a2 - a3) / a4 */ - - if (cpu_post_complex_1_asm(a1, a2, a3, a4, n) != n * result) - { - return -1; - } - - return 0; -} - - /* (1 + x + x^2 + ... + x^n) * (1 - x) = 1 - x^(n+1) - */ -static int cpu_post_test_complex_2 (void) -{ - int ret = -1; - int x; - int n; - int k; - int left; - int right; - - for (x = -8; x <= 8; x ++) - { - n = 9; - - left = cpu_post_complex_2_asm(x, n); - left *= 1 - x; - - right = 1; - for (k = 0; k <= n; k ++) - { - right *= x; - } - right = 1 - right; - - if (left != right) - { - goto Done; - } - } - - ret = 0; - Done: - - return ret; -} - -int cpu_post_test_complex (void) -{ - int ret = 0; - - if (ret == 0) - { - ret = cpu_post_test_complex_1(); - } - - if (ret == 0) - { - ret = cpu_post_test_complex_2(); - } - - if (ret != 0) - { - post_log ("Error at complex test !\n"); - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/cpu_asm.h b/post/cpu/cpu_asm.h deleted file mode 100644 index 1cbaf41..0000000 --- a/post/cpu/cpu_asm.h +++ /dev/null @@ -1,224 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ -#ifndef _CPU_ASM_H -#define _CPU_ASM_H - -#define BIT_C 0x00000001 - -#define OP_BLR 0x4e800020 -#define OP_EXTSB 0x7c000774 -#define OP_EXTSH 0x7c000734 -#define OP_NEG 0x7c0000d0 -#define OP_CNTLZW 0x7c000034 -#define OP_ADD 0x7c000214 -#define OP_ADDC 0x7c000014 -#define OP_ADDME 0x7c0001d4 -#define OP_ADDZE 0x7c000194 -#define OP_ADDE 0x7c000114 -#define OP_ADDI 0x38000000 -#define OP_SUBF 0x7c000050 -#define OP_SUBFC 0x7c000010 -#define OP_SUBFE 0x7c000110 -#define OP_SUBFME 0x7c0001d0 -#define OP_SUBFZE 0x7c000190 -#define OP_MFCR 0x7c000026 -#define OP_MTCR 0x7c0ff120 -#define OP_MFXER 0x7c0102a6 -#define OP_MTXER 0x7c0103a6 -#define OP_MCRXR 0x7c000400 -#define OP_MCRF 0x4c000000 -#define OP_CRAND 0x4c000202 -#define OP_CRANDC 0x4c000102 -#define OP_CROR 0x4c000382 -#define OP_CRORC 0x4c000342 -#define OP_CRXOR 0x4c000182 -#define OP_CRNAND 0x4c0001c2 -#define OP_CRNOR 0x4c000042 -#define OP_CREQV 0x4c000242 -#define OP_CMPW 0x7c000000 -#define OP_CMPLW 0x7c000040 -#define OP_CMPWI 0x2c000000 -#define OP_CMPLWI 0x28000000 -#define OP_MULLW 0x7c0001d6 -#define OP_MULHW 0x7c000096 -#define OP_MULHWU 0x7c000016 -#define OP_DIVW 0x7c0003d6 -#define OP_DIVWU 0x7c000396 -#define OP_OR 0x7c000378 -#define OP_ORC 0x7c000338 -#define OP_XOR 0x7c000278 -#define OP_NAND 0x7c0003b8 -#define OP_NOR 0x7c0000f8 -#define OP_EQV 0x7c000238 -#define OP_SLW 0x7c000030 -#define OP_SRW 0x7c000430 -#define OP_SRAW 0x7c000630 -#define OP_ORI 0x60000000 -#define OP_ORIS 0x64000000 -#define OP_XORI 0x68000000 -#define OP_XORIS 0x6c000000 -#define OP_ANDI_ 0x70000000 -#define OP_ANDIS_ 0x74000000 -#define OP_SRAWI 0x7c000670 -#define OP_RLWINM 0x54000000 -#define OP_RLWNM 0x5c000000 -#define OP_RLWIMI 0x50000000 -#define OP_LWZ 0x80000000 -#define OP_LHZ 0xa0000000 -#define OP_LHA 0xa8000000 -#define OP_LBZ 0x88000000 -#define OP_LWZU 0x84000000 -#define OP_LHZU 0xa4000000 -#define OP_LHAU 0xac000000 -#define OP_LBZU 0x8c000000 -#define OP_LWZX 0x7c00002e -#define OP_LHZX 0x7c00022e -#define OP_LHAX 0x7c0002ae -#define OP_LBZX 0x7c0000ae -#define OP_LWZUX 0x7c00006e -#define OP_LHZUX 0x7c00026e -#define OP_LHAUX 0x7c0002ee -#define OP_LBZUX 0x7c0000ee -#define OP_STW 0x90000000 -#define OP_STH 0xb0000000 -#define OP_STB 0x98000000 -#define OP_STWU 0x94000000 -#define OP_STHU 0xb4000000 -#define OP_STBU 0x9c000000 -#define OP_STWX 0x7c00012e -#define OP_STHX 0x7c00032e -#define OP_STBX 0x7c0001ae -#define OP_STWUX 0x7c00016e -#define OP_STHUX 0x7c00036e -#define OP_STBUX 0x7c0001ee -#define OP_B 0x48000000 -#define OP_BL 0x48000001 -#define OP_BC 0x40000000 -#define OP_BCL 0x40000001 -#define OP_MTLR 0x7c0803a6 -#define OP_MFLR 0x7c0802a6 -#define OP_MTCTR 0x7c0903a6 -#define OP_MFCTR 0x7c0902a6 -#define OP_LMW 0xb8000000 -#define OP_STMW 0xbc000000 -#define OP_LSWI 0x7c0004aa -#define OP_LSWX 0x7c00042a -#define OP_STSWI 0x7c0005aa -#define OP_STSWX 0x7c00052a - -#define ASM_0(opcode) (opcode) -#define ASM_1(opcode, rd) ((opcode) + \ - ((rd) << 21)) -#define ASM_1C(opcode, cr) ((opcode) + \ - ((cr) << 23)) -#define ASM_11(opcode, rd, rs) ((opcode) + \ - ((rd) << 21) + \ - ((rs) << 16)) -#define ASM_11C(opcode, cd, cs) ((opcode) + \ - ((cd) << 23) + \ - ((cs) << 18)) -#define ASM_11X(opcode, rd, rs) ((opcode) + \ - ((rs) << 21) + \ - ((rd) << 16)) -#define ASM_11I(opcode, rd, rs, simm) ((opcode) + \ - ((rd) << 21) + \ - ((rs) << 16) + \ - ((simm) & 0xffff)) -#define ASM_11IF(opcode, rd, rs, simm) ((opcode) + \ - ((rd) << 21) + \ - ((rs) << 16) + \ - ((simm) << 11)) -#define ASM_11S(opcode, rd, rs, sh) ((opcode) + \ - ((rs) << 21) + \ - ((rd) << 16) + \ - ((sh) << 11)) -#define ASM_11IX(opcode, rd, rs, imm) ((opcode) + \ - ((rs) << 21) + \ - ((rd) << 16) + \ - ((imm) & 0xffff)) -#define ASM_12(opcode, rd, rs1, rs2) ((opcode) + \ - ((rd) << 21) + \ - ((rs1) << 16) + \ - ((rs2) << 11)) -#define ASM_12F(opcode, fd, fs1, fs2) ((opcode) + \ - ((fd) << 21) + \ - ((fs1) << 16) + \ - ((fs2) << 11)) -#define ASM_12X(opcode, rd, rs1, rs2) ((opcode) + \ - ((rs1) << 21) + \ - ((rd) << 16) + \ - ((rs2) << 11)) -#define ASM_2C(opcode, cr, rs1, rs2) ((opcode) + \ - ((cr) << 23) + \ - ((rs1) << 16) + \ - ((rs2) << 11)) -#define ASM_1IC(opcode, cr, rs, imm) ((opcode) + \ - ((cr) << 23) + \ - ((rs) << 16) + \ - ((imm) & 0xffff)) -#define ASM_122(opcode, rd, rs1, rs2, imm1, imm2) \ - ((opcode) + \ - ((rs1) << 21) + \ - ((rd) << 16) + \ - ((rs2) << 11) + \ - ((imm1) << 6) + \ - ((imm2) << 1)) -#define ASM_113(opcode, rd, rs, imm1, imm2, imm3) \ - ((opcode) + \ - ((rs) << 21) + \ - ((rd) << 16) + \ - ((imm1) << 11) + \ - ((imm2) << 6) + \ - ((imm3) << 1)) -#define ASM_1O(opcode, off) ((opcode) + (off)) -#define ASM_3O(opcode, bo, bi, off) ((opcode) + \ - ((bo) << 21) + \ - ((bi) << 16) + \ - (off)) - -#define ASM_ADDI(rd, rs, simm) ASM_11I(OP_ADDI, rd, rs, simm) -#define ASM_BLR ASM_0(OP_BLR) -#define ASM_STW(rd, rs, simm) ASM_11I(OP_STW, rd, rs, simm) -#define ASM_LWZ(rd, rs, simm) ASM_11I(OP_LWZ, rd, rs, simm) -#define ASM_MFCR(rd) ASM_1(OP_MFCR, rd) -#define ASM_MTCR(rd) ASM_1(OP_MTCR, rd) -#define ASM_MFXER(rd) ASM_1(OP_MFXER, rd) -#define ASM_MTXER(rd) ASM_1(OP_MTXER, rd) -#define ASM_MFCTR(rd) ASM_1(OP_MFCTR, rd) -#define ASM_MTCTR(rd) ASM_1(OP_MTCTR, rd) -#define ASM_MCRXR(cr) ASM_1C(OP_MCRXR, cr) -#define ASM_MCRF(cd, cs) ASM_11C(OP_MCRF, cd, cs) -#define ASM_B(off) ASM_1O(OP_B, off) -#define ASM_BL(off) ASM_1O(OP_BL, off) -#define ASM_MFLR(rd) ASM_1(OP_MFLR, rd) -#define ASM_MTLR(rd) ASM_1(OP_MTLR, rd) -#define ASM_LI(rd, imm) ASM_ADDI(rd, 0, imm) -#define ASM_LMW(rd, rs, simm) ASM_11I(OP_LMW, rd, rs, simm) -#define ASM_STMW(rd, rs, simm) ASM_11I(OP_STMW, rd, rs, simm) -#define ASM_LSWI(rd, rs, simm) ASM_11IF(OP_LSWI, rd, rs, simm) -#define ASM_LSWX(rd, rs1, rs2) ASM_12(OP_LSWX, rd, rs1, rs2) -#define ASM_STSWI(rd, rs, simm) ASM_11IF(OP_STSWI, rd, rs, simm) -#define ASM_STSWX(rd, rs1, rs2) ASM_12(OP_STSWX, rd, rs1, rs2) - - -#endif /* _CPU_ASM_H */ diff --git a/post/cpu/cr.c b/post/cpu/cr.c deleted file mode 100644 index da6ef37..0000000 --- a/post/cpu/cr.c +++ /dev/null @@ -1,356 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Condition register istructions: mtcr, mfcr, mcrxr, - * crand, crandc, cror, crorc, crxor, - * crnand, crnor, creqv, mcrf - * - * The mtcrf/mfcr instructions is tested by loading different - * values into the condition register (mtcrf), moving its value - * to a general-purpose register (mfcr) and comparing this value - * with the expected one. - * The mcrxr instruction is tested by loading a fixed value - * into the XER register (mtspr), moving XER value to the - * condition register (mcrxr), moving it to a general-purpose - * register (mfcr) and comparing the value of this register with - * the expected one. - * The rest of instructions is tested by loading a fixed - * value into the condition register (mtcrf), executing each - * instruction several times to modify all 4-bit condition - * fields, moving the value of the conditional register to a - * general-purpose register (mfcr) and comparing it with the - * expected one. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_11 (ulong *code, ulong *res, ulong op1); -extern void cpu_post_exec_21x (ulong *code, ulong *op1, ulong *op2, ulong op3); - -static ulong cpu_post_cr_table1[] = -{ - 0xaaaaaaaa, - 0x55555555, -}; -static unsigned int cpu_post_cr_size1 = - sizeof (cpu_post_cr_table1) / sizeof (ulong); - -static struct cpu_post_cr_s2 { - ulong xer; - ulong cr; -} cpu_post_cr_table2[] = -{ - { - 0xa0000000, - 1 - }, - { - 0x40000000, - 5 - }, -}; -static unsigned int cpu_post_cr_size2 = - sizeof (cpu_post_cr_table2) / sizeof (struct cpu_post_cr_s2); - -static struct cpu_post_cr_s3 { - ulong cr; - ulong cs; - ulong cd; - ulong res; -} cpu_post_cr_table3[] = -{ - { - 0x01234567, - 0, - 4, - 0x01230567 - }, - { - 0x01234567, - 7, - 0, - 0x71234567 - }, -}; -static unsigned int cpu_post_cr_size3 = - sizeof (cpu_post_cr_table3) / sizeof (struct cpu_post_cr_s3); - -static struct cpu_post_cr_s4 { - ulong cmd; - ulong cr; - ulong op1; - ulong op2; - ulong op3; - ulong res; -} cpu_post_cr_table4[] = -{ - { - OP_CRAND, - 0x0000ffff, - 0, - 16, - 0, - 0x0000ffff - }, - { - OP_CRAND, - 0x0000ffff, - 16, - 17, - 0, - 0x8000ffff - }, - { - OP_CRANDC, - 0x0000ffff, - 0, - 16, - 0, - 0x0000ffff - }, - { - OP_CRANDC, - 0x0000ffff, - 16, - 0, - 0, - 0x8000ffff - }, - { - OP_CROR, - 0x0000ffff, - 0, - 16, - 0, - 0x8000ffff - }, - { - OP_CROR, - 0x0000ffff, - 0, - 1, - 0, - 0x0000ffff - }, - { - OP_CRORC, - 0x0000ffff, - 0, - 16, - 0, - 0x0000ffff - }, - { - OP_CRORC, - 0x0000ffff, - 0, - 0, - 0, - 0x8000ffff - }, - { - OP_CRXOR, - 0x0000ffff, - 0, - 0, - 0, - 0x0000ffff - }, - { - OP_CRXOR, - 0x0000ffff, - 0, - 16, - 0, - 0x8000ffff - }, - { - OP_CRNAND, - 0x0000ffff, - 0, - 16, - 0, - 0x8000ffff - }, - { - OP_CRNAND, - 0x0000ffff, - 16, - 17, - 0, - 0x0000ffff - }, - { - OP_CRNOR, - 0x0000ffff, - 0, - 16, - 0, - 0x0000ffff - }, - { - OP_CRNOR, - 0x0000ffff, - 0, - 1, - 0, - 0x8000ffff - }, - { - OP_CREQV, - 0x0000ffff, - 0, - 0, - 0, - 0x8000ffff - }, - { - OP_CREQV, - 0x0000ffff, - 0, - 16, - 0, - 0x0000ffff - }, -}; -static unsigned int cpu_post_cr_size4 = - sizeof (cpu_post_cr_table4) / sizeof (struct cpu_post_cr_s4); - -int cpu_post_test_cr (void) -{ - int ret = 0; - unsigned int i; - unsigned long cr_sav; - - asm ( "mfcr %0" : "=r" (cr_sav) : ); - - for (i = 0; i < cpu_post_cr_size1 && ret == 0; i++) - { - ulong cr = cpu_post_cr_table1[i]; - ulong res; - - unsigned long code[] = - { - ASM_MTCR(3), - ASM_MFCR(3), - ASM_BLR, - }; - - cpu_post_exec_11 (code, &res, cr); - - ret = res == cr ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at cr1 test %d !\n", i); - } - } - - for (i = 0; i < cpu_post_cr_size2 && ret == 0; i++) - { - struct cpu_post_cr_s2 *test = cpu_post_cr_table2 + i; - ulong res; - ulong xer; - - unsigned long code[] = - { - ASM_MTXER(3), - ASM_MCRXR(test->cr), - ASM_MFCR(3), - ASM_MFXER(4), - ASM_BLR, - }; - - cpu_post_exec_21x (code, &res, &xer, test->xer); - - ret = xer == 0 && ((res << (4 * test->cr)) & 0xe0000000) == test->xer ? - 0 : -1; - - if (ret != 0) - { - post_log ("Error at cr2 test %d !\n", i); - } - } - - for (i = 0; i < cpu_post_cr_size3 && ret == 0; i++) - { - struct cpu_post_cr_s3 *test = cpu_post_cr_table3 + i; - ulong res; - - unsigned long code[] = - { - ASM_MTCR(3), - ASM_MCRF(test->cd, test->cs), - ASM_MFCR(3), - ASM_BLR, - }; - - cpu_post_exec_11 (code, &res, test->cr); - - ret = res == test->res ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at cr3 test %d !\n", i); - } - } - - for (i = 0; i < cpu_post_cr_size4 && ret == 0; i++) - { - struct cpu_post_cr_s4 *test = cpu_post_cr_table4 + i; - ulong res; - - unsigned long code[] = - { - ASM_MTCR(3), - ASM_12F(test->cmd, test->op3, test->op1, test->op2), - ASM_MFCR(3), - ASM_BLR, - }; - - cpu_post_exec_11 (code, &res, test->cr); - - ret = res == test->res ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at cr4 test %d !\n", i); - } - } - - asm ( "mtcr %0" : : "r" (cr_sav)); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/load.c b/post/cpu/load.c deleted file mode 100644 index 393c568..0000000 --- a/post/cpu/load.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Load instructions: lbz(x)(u), lhz(x)(u), lha(x)(u), lwz(x)(u) - * - * All operations are performed on a 16-byte array. The array - * is 4-byte aligned. The base register points to offset 8. - * The immediate offset (index register) ranges in [-8 ... +7]. - * The test cases are composed so that they do not - * cause alignment exceptions. - * The test contains a pre-built table describing all test cases. - * The table entry contains: - * the instruction opcode, the array contents, the value of the index - * register and the expected value of the destination register. - * After executing the instruction, the test verifies the - * value of the destination register and the value of the base - * register (it must change for "load with update" instructions). - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_22w (ulong *code, ulong *op1, ulong op2, ulong *op3); -extern void cpu_post_exec_21w (ulong *code, ulong *op1, ulong *op2); - -static struct cpu_post_load_s -{ - ulong cmd; - uint width; - int update; - int index; - ulong offset; -} cpu_post_load_table[] = -{ - { - OP_LWZ, - 4, - 0, - 0, - 4 - }, - { - OP_LHA, - 3, - 0, - 0, - 2 - }, - { - OP_LHZ, - 2, - 0, - 0, - 2 - }, - { - OP_LBZ, - 1, - 0, - 0, - 1 - }, - { - OP_LWZU, - 4, - 1, - 0, - 4 - }, - { - OP_LHAU, - 3, - 1, - 0, - 2 - }, - { - OP_LHZU, - 2, - 1, - 0, - 2 - }, - { - OP_LBZU, - 1, - 1, - 0, - 1 - }, - { - OP_LWZX, - 4, - 0, - 1, - 4 - }, - { - OP_LHAX, - 3, - 0, - 1, - 2 - }, - { - OP_LHZX, - 2, - 0, - 1, - 2 - }, - { - OP_LBZX, - 1, - 0, - 1, - 1 - }, - { - OP_LWZUX, - 4, - 1, - 1, - 4 - }, - { - OP_LHAUX, - 3, - 1, - 1, - 2 - }, - { - OP_LHZUX, - 2, - 1, - 1, - 2 - }, - { - OP_LBZUX, - 1, - 1, - 1, - 1 - }, -}; -static unsigned int cpu_post_load_size = - sizeof (cpu_post_load_table) / sizeof (struct cpu_post_load_s); - -int cpu_post_test_load (void) -{ - int ret = 0; - unsigned int i; - - for (i = 0; i < cpu_post_load_size && ret == 0; i++) - { - struct cpu_post_load_s *test = cpu_post_load_table + i; - uchar data[16] = - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; - ulong base0 = (ulong) (data + 8); - ulong base = base0; - ulong value; - - if (test->index) - { - ulong code[] = - { - ASM_12(test->cmd, 5, 3, 4), - ASM_BLR, - }; - - cpu_post_exec_22w (code, &base, test->offset, &value); - } - else - { - ulong code[] = - { - ASM_11I(test->cmd, 4, 3, test->offset), - ASM_BLR, - }; - - cpu_post_exec_21w (code, &base, &value); - } - - if (ret == 0) - { - if (test->update) - ret = base == base0 + test->offset ? 0 : -1; - else - ret = base == base0 ? 0 : -1; - } - - if (ret == 0) - { - switch (test->width) - { - case 1: - ret = *(uchar *)(base0 + test->offset) == value ? - 0 : -1; - break; - case 2: - ret = *(ushort *)(base0 + test->offset) == value ? - 0 : -1; - break; - case 3: - ret = *(short *)(base0 + test->offset) == value ? - 0 : -1; - break; - case 4: - ret = *(ulong *)(base0 + test->offset) == value ? - 0 : -1; - break; - } - } - - if (ret != 0) - { - post_log ("Error at load test %d !\n", i); - } - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/multi.c b/post/cpu/multi.c deleted file mode 100644 index 8724384..0000000 --- a/post/cpu/multi.c +++ /dev/null @@ -1,81 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Load/store multiple word instructions: lmw, stmw - * - * 26 consecutive words are loaded from a source memory buffer - * into GPRs r6 through r31. After that, 26 consecutive words are stored - * from the GPRs r6 through r31 into a target memory buffer. The contents - * of the source and target buffers are then compared. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); - -int cpu_post_test_multi (void) -{ - int ret = 0; - unsigned int i; - - if (ret == 0) - { - ulong src [26], dst [26]; - - ulong code[] = - { - ASM_LMW(5, 3, 0), - ASM_STMW(5, 4, 0), - ASM_BLR, - }; - - for (i = 0; i < sizeof(src) / sizeof(src[0]); i ++) - { - src[i] = i; - dst[i] = 0; - } - - cpu_post_exec_02(code, (ulong)src, (ulong)dst); - - ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; - } - - if (ret != 0) - { - post_log ("Error at multi test !\n"); - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/rlwimi.c b/post/cpu/rlwimi.c deleted file mode 100644 index f65f79a..0000000 --- a/post/cpu/rlwimi.c +++ /dev/null @@ -1,162 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Shift instructions: rlwimi - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, - ulong op2); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_rlwimi_s -{ - ulong cmd; - ulong op0; - ulong op1; - uchar op2; - uchar mb; - uchar me; - ulong res; -} cpu_post_rlwimi_table[] = -{ - { - OP_RLWIMI, - 0xff00ffff, - 0x0000aa00, - 8, - 8, - 15, - 0xffaaffff - }, -}; -static unsigned int cpu_post_rlwimi_size = - sizeof (cpu_post_rlwimi_table) / sizeof (struct cpu_post_rlwimi_s); - -int cpu_post_test_rlwimi (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_rlwimi_size && ret == 0; i++) - { - struct cpu_post_rlwimi_s *test = cpu_post_rlwimi_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -20), - ASM_STW(3, stk, 8), - ASM_STW(4, stk, 12), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg1, stk, 8), - ASM_LWZ(reg0, stk, 12), - ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 20), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -20), - ASM_STW(3, stk, 8), - ASM_STW(4, stk, 12), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg1, stk, 8), - ASM_LWZ(reg0, stk, 12), - ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me) | - BIT_C, - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 20), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_22 (code, & cr, & res, test->op0, test->op1); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwimi test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_22 (codecr, & cr, & res, test->op0, test->op1); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwimi test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/rlwinm.c b/post/cpu/rlwinm.c deleted file mode 100644 index e240c41..0000000 --- a/post/cpu/rlwinm.c +++ /dev/null @@ -1,155 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Shift instructions: rlwinm - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_rlwinm_s -{ - ulong cmd; - ulong op1; - uchar op2; - uchar mb; - uchar me; - ulong res; -} cpu_post_rlwinm_table[] = -{ - { - OP_RLWINM, - 0xffff0000, - 24, - 16, - 23, - 0x0000ff00 - }, -}; -static unsigned int cpu_post_rlwinm_size = - sizeof (cpu_post_rlwinm_table) / sizeof (struct cpu_post_rlwinm_s); - -int cpu_post_test_rlwinm (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_rlwinm_size && ret == 0; i++) - { - struct cpu_post_rlwinm_s *test = cpu_post_rlwinm_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, test->me), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_113(test->cmd, reg1, reg0, test->op2, test->mb, - test->me) | BIT_C, - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_21 (code, & cr, & res, test->op1); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwinm test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_21 (codecr, & cr, & res, test->op1); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwinm test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/rlwnm.c b/post/cpu/rlwnm.c deleted file mode 100644 index 523cf4d..0000000 --- a/post/cpu/rlwnm.c +++ /dev/null @@ -1,165 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Shift instructions: rlwnm - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, - ulong op2); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_rlwnm_s -{ - ulong cmd; - ulong op1; - ulong op2; - uchar mb; - uchar me; - ulong res; -} cpu_post_rlwnm_table[] = -{ - { - OP_RLWNM, - 0xffff0000, - 24, - 16, - 23, - 0x0000ff00 - }, -}; -static unsigned int cpu_post_rlwnm_size = - sizeof (cpu_post_rlwnm_table) / sizeof (struct cpu_post_rlwnm_s); - -int cpu_post_test_rlwnm (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_rlwnm_size && ret == 0; i++) - { - struct cpu_post_rlwnm_s *test = cpu_post_rlwnm_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int reg2 = (reg + 2) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me), - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_122(test->cmd, reg2, reg1, reg0, test->mb, test->me) | - BIT_C, - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwnm test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at rlwnm test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/srawi.c b/post/cpu/srawi.c deleted file mode 100644 index 91c82c9..0000000 --- a/post/cpu/srawi.c +++ /dev/null @@ -1,156 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Shift instructions: srawi - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_srawi_s -{ - ulong cmd; - ulong op1; - uchar op2; - ulong res; -} cpu_post_srawi_table[] = -{ - { - OP_SRAWI, - 0x8000, - 3, - 0x1000 - }, - { - OP_SRAWI, - 0x80000000, - 3, - 0xf0000000 - }, -}; -static unsigned int cpu_post_srawi_size = - sizeof (cpu_post_srawi_table) / sizeof (struct cpu_post_srawi_s); - -int cpu_post_test_srawi (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_srawi_size && ret == 0; i++) - { - struct cpu_post_srawi_s *test = cpu_post_srawi_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11S(test->cmd, reg1, reg0, test->op2), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11S(test->cmd, reg1, reg0, test->op2) | BIT_C, - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_21 (code, & cr, & res, test->op1); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at srawi test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_21 (codecr, & cr, & res, test->op1); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at srawi test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/store.c b/post/cpu/store.c deleted file mode 100644 index f495bf2..0000000 --- a/post/cpu/store.c +++ /dev/null @@ -1,235 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Store instructions: stb(x)(u), sth(x)(u), stw(x)(u) - * - * All operations are performed on a 16-byte array. The array - * is 4-byte aligned. The base register points to offset 8. - * The immediate offset (index register) ranges in [-8 ... +7]. - * The test cases are composed so that they do not - * cause alignment exceptions. - * The test contains a pre-built table describing all test cases. - * The table entry contains: - * the instruction opcode, the value of the index register and - * the value of the source register. After executing the - * instruction, the test verifies the contents of the array - * and the value of the base register (it must change for "store - * with update" instructions). - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_12w (ulong *code, ulong *op1, ulong op2, ulong op3); -extern void cpu_post_exec_11w (ulong *code, ulong *op1, ulong op2); - -static struct cpu_post_store_s -{ - ulong cmd; - uint width; - int update; - int index; - ulong offset; - ulong value; -} cpu_post_store_table[] = -{ - { - OP_STW, - 4, - 0, - 0, - -4, - 0xff00ff00 - }, - { - OP_STH, - 2, - 0, - 0, - -2, - 0xff00 - }, - { - OP_STB, - 1, - 0, - 0, - -1, - 0xff - }, - { - OP_STWU, - 4, - 1, - 0, - -4, - 0xff00ff00 - }, - { - OP_STHU, - 2, - 1, - 0, - -2, - 0xff00 - }, - { - OP_STBU, - 1, - 1, - 0, - -1, - 0xff - }, - { - OP_STWX, - 4, - 0, - 1, - -4, - 0xff00ff00 - }, - { - OP_STHX, - 2, - 0, - 1, - -2, - 0xff00 - }, - { - OP_STBX, - 1, - 0, - 1, - -1, - 0xff - }, - { - OP_STWUX, - 4, - 1, - 1, - -4, - 0xff00ff00 - }, - { - OP_STHUX, - 2, - 1, - 1, - -2, - 0xff00 - }, - { - OP_STBUX, - 1, - 1, - 1, - -1, - 0xff - }, -}; -static unsigned int cpu_post_store_size = - sizeof (cpu_post_store_table) / sizeof (struct cpu_post_store_s); - -int cpu_post_test_store (void) -{ - int ret = 0; - unsigned int i; - - for (i = 0; i < cpu_post_store_size && ret == 0; i++) - { - struct cpu_post_store_s *test = cpu_post_store_table + i; - uchar data[16] = - { 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15 }; - ulong base0 = (ulong) (data + 8); - ulong base = base0; - - if (test->index) - { - ulong code[] = - { - ASM_12(test->cmd, 5, 3, 4), - ASM_BLR, - }; - - cpu_post_exec_12w (code, &base, test->offset, test->value); - } - else - { - ulong code[] = - { - ASM_11I(test->cmd, 4, 3, test->offset), - ASM_BLR, - }; - - cpu_post_exec_11w (code, &base, test->value); - } - - if (ret == 0) - { - if (test->update) - ret = base == base0 + test->offset ? 0 : -1; - else - ret = base == base0 ? 0 : -1; - } - - if (ret == 0) - { - switch (test->width) - { - case 1: - ret = *(uchar *)(base0 + test->offset) == test->value ? - 0 : -1; - break; - case 2: - ret = *(ushort *)(base0 + test->offset) == test->value ? - 0 : -1; - break; - case 4: - ret = *(ulong *)(base0 + test->offset) == test->value ? - 0 : -1; - break; - } - } - - if (ret != 0) - { - post_log ("Error at store test %d !\n", i); - } - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/string.c b/post/cpu/string.c deleted file mode 100644 index bd83bd1..0000000 --- a/post/cpu/string.c +++ /dev/null @@ -1,106 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Load/store string instructions: lswi, stswi, lswx, stswx - * - * Several consecutive bytes from a source memory buffer are loaded - * left to right into GPRs. After that, the bytes are stored - * from the GPRs into a target memory buffer. The contents - * of the source and target buffers are then compared. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_02 (ulong *code, ulong op1, ulong op2); -extern void cpu_post_exec_04 (ulong *code, ulong op1, ulong op2, ulong op3, - ulong op4); - -#include <bedbug/regs.h> -int cpu_post_test_string (void) -{ - int ret = 0; - unsigned int i; - - if (ret == 0) - { - char src [31], dst [31]; - - ulong code[] = - { - ASM_LSWI(5, 3, 31), - ASM_STSWI(5, 4, 31), - ASM_BLR, - }; - - for (i = 0; i < sizeof(src); i ++) - { - src[i] = (char) i; - dst[i] = 0; - } - - cpu_post_exec_02(code, (ulong)src, (ulong)dst); - - ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; - } - - if (ret == 0) - { - char src [95], dst [95]; - - ulong code[] = - { - ASM_LSWX(8, 3, 5), - ASM_STSWX(8, 4, 5), - ASM_BLR, - }; - - for (i = 0; i < sizeof(src); i ++) - { - src[i] = (char) i; - dst[i] = 0; - } - - cpu_post_exec_04(code, (ulong)src, (ulong)dst, 0, sizeof(src)); - - ret = memcmp(src, dst, sizeof(dst)) == 0 ? 0 : -1; - } - - if (ret != 0) - { - post_log ("Error at string test !\n"); - } - - return ret; -} - -#endif -#endif diff --git a/post/cpu/three.c b/post/cpu/three.c deleted file mode 100644 index c2d7476..0000000 --- a/post/cpu/three.c +++ /dev/null @@ -1,259 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Ternary instructions instr rD,rA,rB - * - * Arithmetic instructions: add, addc, adde, subf, subfc, subfe, - * mullw, mulhw, mulhwu, divw, divwu - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, - ulong op2); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_three_s -{ - ulong cmd; - ulong op1; - ulong op2; - ulong res; -} cpu_post_three_table[] = -{ - { - OP_ADD, - 100, - 200, - 300 - }, - { - OP_ADD, - 100, - -200, - -100 - }, - { - OP_ADDC, - 100, - 200, - 300 - }, - { - OP_ADDC, - 100, - -200, - -100 - }, - { - OP_ADDE, - 100, - 200, - 300 - }, - { - OP_ADDE, - 100, - -200, - -100 - }, - { - OP_SUBF, - 100, - 200, - 100 - }, - { - OP_SUBF, - 300, - 200, - -100 - }, - { - OP_SUBFC, - 100, - 200, - 100 - }, - { - OP_SUBFC, - 300, - 200, - -100 - }, - { - OP_SUBFE, - 100, - 200, - 200 + ~100 - }, - { - OP_SUBFE, - 300, - 200, - 200 + ~300 - }, - { - OP_MULLW, - 200, - 300, - 200 * 300 - }, - { - OP_MULHW, - 0x10000000, - 0x10000000, - 0x1000000 - }, - { - OP_MULHWU, - 0x80000000, - 0x80000000, - 0x40000000 - }, - { - OP_DIVW, - -20, - 5, - -4 - }, - { - OP_DIVWU, - 0x8000, - 0x200, - 0x40 - }, -}; -static unsigned int cpu_post_three_size = - sizeof (cpu_post_three_table) / sizeof (struct cpu_post_three_s); - -int cpu_post_test_three (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_three_size && ret == 0; i++) - { - struct cpu_post_three_s *test = cpu_post_three_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int reg2 = (reg + 2) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_12(test->cmd, reg2, reg1, reg0), - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_12(test->cmd, reg2, reg1, reg0) | BIT_C, - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at three test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at three test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/threei.c b/post/cpu/threei.c deleted file mode 100644 index 79f0178..0000000 --- a/post/cpu/threei.c +++ /dev/null @@ -1,137 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Ternary instructions instr rA,rS,UIMM - * - * Logic instructions: ori, oris, xori, xoris - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_threei_s -{ - ulong cmd; - ulong op1; - ushort op2; - ulong res; -} cpu_post_threei_table[] = -{ - { - OP_ORI, - 0x80000000, - 0xffff, - 0x8000ffff - }, - { - OP_ORIS, - 0x00008000, - 0xffff, - 0xffff8000 - }, - { - OP_XORI, - 0x8000ffff, - 0xffff, - 0x80000000 - }, - { - OP_XORIS, - 0x00008000, - 0xffff, - 0xffff8000 - }, -}; -static unsigned int cpu_post_threei_size = - sizeof (cpu_post_threei_table) / sizeof (struct cpu_post_threei_s); - -int cpu_post_test_threei (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_threei_size && ret == 0; i++) - { - struct cpu_post_threei_s *test = cpu_post_threei_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11IX(test->cmd, reg1, reg0, test->op2), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - cr = 0; - cpu_post_exec_21 (code, & cr, & res, test->op1); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at threei test %d !\n", i); - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/threex.c b/post/cpu/threex.c deleted file mode 100644 index 2c72063..0000000 --- a/post/cpu/threex.c +++ /dev/null @@ -1,229 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Ternary instructions instr rA,rS,rB - * - * Logic instructions: or, orc, xor, nand, nor, eqv - * Shift instructions: slw, srw, sraw - * - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_22 (ulong *code, ulong *cr, ulong *res, ulong op1, - ulong op2); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_threex_s -{ - ulong cmd; - ulong op1; - ulong op2; - ulong res; -} cpu_post_threex_table[] = -{ - { - OP_OR, - 0x1234, - 0x5678, - 0x1234 | 0x5678 - }, - { - OP_ORC, - 0x1234, - 0x5678, - 0x1234 | ~0x5678 - }, - { - OP_XOR, - 0x1234, - 0x5678, - 0x1234 ^ 0x5678 - }, - { - OP_NAND, - 0x1234, - 0x5678, - ~(0x1234 & 0x5678) - }, - { - OP_NOR, - 0x1234, - 0x5678, - ~(0x1234 | 0x5678) - }, - { - OP_EQV, - 0x1234, - 0x5678, - ~(0x1234 ^ 0x5678) - }, - { - OP_SLW, - 0x80, - 16, - 0x800000 - }, - { - OP_SLW, - 0x80, - 32, - 0 - }, - { - OP_SRW, - 0x800000, - 16, - 0x80 - }, - { - OP_SRW, - 0x800000, - 32, - 0 - }, - { - OP_SRAW, - 0x80000000, - 3, - 0xf0000000 - }, - { - OP_SRAW, - 0x8000, - 3, - 0x1000 - }, -}; -static unsigned int cpu_post_threex_size = - sizeof (cpu_post_threex_table) / sizeof (struct cpu_post_threex_s); - -int cpu_post_test_threex (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_threex_size && ret == 0; i++) - { - struct cpu_post_threex_s *test = cpu_post_threex_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int reg2 = (reg + 2) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_12X(test->cmd, reg2, reg1, reg0), - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -24), - ASM_STW(3, stk, 12), - ASM_STW(4, stk, 16), - ASM_STW(reg0, stk, 8), - ASM_STW(reg1, stk, 4), - ASM_STW(reg2, stk, 0), - ASM_LWZ(reg1, stk, 12), - ASM_LWZ(reg0, stk, 16), - ASM_12X(test->cmd, reg2, reg1, reg0) | BIT_C, - ASM_STW(reg2, stk, 12), - ASM_LWZ(reg2, stk, 0), - ASM_LWZ(reg1, stk, 4), - ASM_LWZ(reg0, stk, 8), - ASM_LWZ(3, stk, 12), - ASM_ADDI(1, stk, 24), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_22 (code, & cr, & res, test->op1, test->op2); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at threex test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_22 (codecr, & cr, & res, test->op1, test->op2); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at threex test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/two.c b/post/cpu/two.c deleted file mode 100644 index cfbac5e..0000000 --- a/post/cpu/two.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Binary instructions instr rD,rA - * - * Logic instructions: neg - * Arithmetic instructions: addme, addze, subfme, subfze - - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_two_s -{ - ulong cmd; - ulong op; - ulong res; -} cpu_post_two_table[] = -{ - { - OP_NEG, - 3, - -3 - }, - { - OP_NEG, - 5, - -5 - }, - { - OP_ADDME, - 6, - 5 - }, - { - OP_ADDZE, - 5, - 5 - }, - { - OP_SUBFME, - 6, - ~6 - 1 - }, - { - OP_SUBFZE, - 5, - ~5 - }, -}; -static unsigned int cpu_post_two_size = - sizeof (cpu_post_two_table) / sizeof (struct cpu_post_two_s); - -int cpu_post_test_two (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_two_size && ret == 0; i++) - { - struct cpu_post_two_s *test = cpu_post_two_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11(test->cmd, reg1, reg0), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11(test->cmd, reg1, reg0) | BIT_C, - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_21 (code, & cr, & res, test->op); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at two test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_21 (codecr, & cr, & res, test->op); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at two test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/cpu/twox.c b/post/cpu/twox.c deleted file mode 100644 index 48d9954..0000000 --- a/post/cpu/twox.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * CPU test - * Binary instructions instr rA,rS - * - * Logic instructions: cntlzw - * Arithmetic instructions: extsb, extsh - - * The test contains a pre-built table of instructions, operands and - * expected results. For each table entry, the test will cyclically use - * different sets of operand registers and result registers. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include "cpu_asm.h" - -#if CONFIG_POST & CFG_POST_CPU - -extern void cpu_post_exec_21 (ulong *code, ulong *cr, ulong *res, ulong op1); -extern ulong cpu_post_makecr (long v); - -static struct cpu_post_twox_s -{ - ulong cmd; - ulong op; - ulong res; -} cpu_post_twox_table[] = -{ - { - OP_EXTSB, - 3, - 3 - }, - { - OP_EXTSB, - 0xff, - -1 - }, - { - OP_EXTSH, - 3, - 3 - }, - { - OP_EXTSH, - 0xff, - 0xff - }, - { - OP_EXTSH, - 0xffff, - -1 - }, - { - OP_CNTLZW, - 0x000fffff, - 12 - }, -}; -static unsigned int cpu_post_twox_size = - sizeof (cpu_post_twox_table) / sizeof (struct cpu_post_twox_s); - -int cpu_post_test_twox (void) -{ - int ret = 0; - unsigned int i, reg; - int flag = disable_interrupts(); - - for (i = 0; i < cpu_post_twox_size && ret == 0; i++) - { - struct cpu_post_twox_s *test = cpu_post_twox_table + i; - - for (reg = 0; reg < 32 && ret == 0; reg++) - { - unsigned int reg0 = (reg + 0) % 32; - unsigned int reg1 = (reg + 1) % 32; - unsigned int stk = reg < 16 ? 31 : 15; - unsigned long code[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11X(test->cmd, reg1, reg0), - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - unsigned long codecr[] = - { - ASM_STW(stk, 1, -4), - ASM_ADDI(stk, 1, -16), - ASM_STW(3, stk, 8), - ASM_STW(reg0, stk, 4), - ASM_STW(reg1, stk, 0), - ASM_LWZ(reg0, stk, 8), - ASM_11X(test->cmd, reg1, reg0) | BIT_C, - ASM_STW(reg1, stk, 8), - ASM_LWZ(reg1, stk, 0), - ASM_LWZ(reg0, stk, 4), - ASM_LWZ(3, stk, 8), - ASM_ADDI(1, stk, 16), - ASM_LWZ(stk, 1, -4), - ASM_BLR, - }; - ulong res; - ulong cr; - - if (ret == 0) - { - cr = 0; - cpu_post_exec_21 (code, & cr, & res, test->op); - - ret = res == test->res && cr == 0 ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at twox test %d !\n", i); - } - } - - if (ret == 0) - { - cpu_post_exec_21 (codecr, & cr, & res, test->op); - - ret = res == test->res && - (cr & 0xe0000000) == cpu_post_makecr (res) ? 0 : -1; - - if (ret != 0) - { - post_log ("Error at twox test %d !\n", i); - } - } - } - } - - if (flag) - enable_interrupts(); - - return ret; -} - -#endif -#endif diff --git a/post/dsp.c b/post/dsp.c deleted file mode 100644 index 63531a2..0000000 --- a/post/dsp.c +++ /dev/null @@ -1,48 +0,0 @@ -/* - * (C) Copyright 2004 - * Pantelis Antoniou, Intracom S.A. , panto@intracom.gr - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * DSP test - * - * This test verifies the connection and performs a memory test - * on any connected DSP(s). The meat of the work is done - * in the board specific function. - */ - -#ifdef CONFIG_POST - -#include <post.h> - -#if CONFIG_POST & CFG_POST_DSP - -extern int board_post_dsp(int flags); - -int dsp_post_test (int flags) -{ - return board_post_dsp(flags); -} - -#endif /* CONFIG_POST & CFG_POST_DSP */ -#endif /* CONFIG_POST */ diff --git a/post/ether.c b/post/ether.c deleted file mode 100644 index 8c87b59..0000000 --- a/post/ether.c +++ /dev/null @@ -1,631 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * Ethernet test - * - * The Serial Communication Controllers (SCC) listed in ctlr_list array below - * are tested in the loopback ethernet mode. - * The controllers are configured accordingly and several packets - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#ifdef CONFIG_POST - -#include <post.h> -#if CONFIG_POST & CFG_POST_ETHER -#if defined(CONFIG_8xx) -#include <commproc.h> -#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#else -#error "Apparently a bad configuration, please fix." -#endif - -#include <command.h> -#include <net.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define MIN_PACKET_LENGTH 64 -#define MAX_PACKET_LENGTH 256 -#define TEST_NUM 1 - -#define CTLR_SCC 0 - -extern void spi_init_f (void); -extern void spi_init_r (void); - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = { {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) - -static struct { - void (*init) (int index); - void (*halt) (int index); - int (*send) (int index, volatile void *packet, int length); - int (*recv) (int index, void *packet, int length); -} ctlr_proc[1]; - -static char *ctlr_name[1] = { "SCC" }; - -/* Ethernet Transmit and Receive Buffers */ -#define DBUF_LENGTH 1520 - -#define TX_BUF_CNT 2 - -#define TOUT_LOOP 100 - -static char txbuf[DBUF_LENGTH]; - -static uint rxIdx; /* index of the current RX buffer */ -static uint txIdx; /* index of the current TX buffer */ - -/* - * SCC Ethernet Tx and Rx buffer descriptors allocated at the - * immr->udata_bd address on Dual-Port RAM - * Provide for Double Buffering - */ - -typedef volatile struct CommonBufferDescriptor { - cbd_t rxbd[PKTBUFSRX]; /* Rx BD */ - cbd_t txbd[TX_BUF_CNT]; /* Tx BD */ -} RTXBD; - -static RTXBD *rtx; - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - bd_t *bd = gd->bd; - - static int proff[] = - { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; - static unsigned int cpm_cr[] = - { CPM_CR_CH_SCC1, CPM_CR_CH_SCC2, CPM_CR_CH_SCC3, -CPM_CR_CH_SCC4 }; - - int i; - scc_enet_t *pram_ptr; - - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - -#if defined(CONFIG_FADS) -#if defined(CONFIG_MPC860T) || defined(CONFIG_MPC86xADS) - /* The FADS860T and MPC86xADS don't use the MODEM_EN or DATA_VOICE signals. */ - *((uint *) BCSR4) &= ~BCSR4_ETHLOOP; - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#else - *((uint *) BCSR4) &= ~(BCSR4_ETHLOOP | BCSR4_MODEM_EN); - *((uint *) BCSR4) |= BCSR4_TFPLDL | BCSR4_TPSQEL | BCSR4_DATA_VOICE; - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif -#endif - - pram_ptr = (scc_enet_t *) & (immr->im_cpm.cp_dparam[proff[scc_index]]); - - rxIdx = 0; - txIdx = 0; - -#ifdef CFG_ALLOC_DPRAM - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + - dpram_alloc_align (sizeof (RTXBD), 8)); -#else - rtx = (RTXBD *) (immr->im_cpm.cp_dpmem + CPM_SCC_BASE); -#endif - -#if 0 - -#if (defined(PA_ENET_RXD) && defined(PA_ENET_TXD)) - /* Configure port A pins for Txd and Rxd. - */ - immr->im_ioport.iop_papar |= (PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_padir &= ~(PA_ENET_RXD | PA_ENET_TXD); - immr->im_ioport.iop_paodr &= ~PA_ENET_TXD; -#elif (defined(PB_ENET_RXD) && defined(PB_ENET_TXD)) - /* Configure port B pins for Txd and Rxd. - */ - immr->im_cpm.cp_pbpar |= (PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbdir &= ~(PB_ENET_RXD | PB_ENET_TXD); - immr->im_cpm.cp_pbodr &= ~PB_ENET_TXD; -#else -#error Configuration Error: exactly ONE of PA_ENET_[RT]XD, PB_ENET_[RT]XD must be defined -#endif - -#if defined(PC_ENET_LBK) - /* Configure port C pins to disable External Loopback - */ - immr->im_ioport.iop_pcpar &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdir |= PC_ENET_LBK; - immr->im_ioport.iop_pcso &= ~PC_ENET_LBK; - immr->im_ioport.iop_pcdat &= ~PC_ENET_LBK; /* Disable Loopback */ -#endif /* PC_ENET_LBK */ - - /* Configure port C pins to enable CLSN and RENA. - */ - immr->im_ioport.iop_pcpar &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcdir &= ~(PC_ENET_CLSN | PC_ENET_RENA); - immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); - - /* Configure port A for TCLK and RCLK. - */ - immr->im_ioport.iop_papar |= (PA_ENET_TCLK | PA_ENET_RCLK); - immr->im_ioport.iop_padir &= ~(PA_ENET_TCLK | PA_ENET_RCLK); - - /* - * Configure Serial Interface clock routing -- see section 16.7.5.3 - * First, clear all SCC bits to zero, then set the ones we want. - */ - - immr->im_cpm.cp_sicr &= ~SICR_ENET_MASK; - immr->im_cpm.cp_sicr |= SICR_ENET_CLKRT; -#else - /* - * SCC2 receive clock is BRG2 - * SCC2 transmit clock is BRG3 - */ - immr->im_cpm.cp_brgc2 = 0x0001000C; - immr->im_cpm.cp_brgc3 = 0x0001000C; - - immr->im_cpm.cp_sicr &= ~0x00003F00; - immr->im_cpm.cp_sicr |= 0x00000a00; -#endif /* 0 */ - - - /* - * Initialize SDCR -- see section 16.9.23.7 - * SDMA configuration register - */ - immr->im_siu_conf.sc_sdcr = 0x01; - - - /* - * Setup SCC Ethernet Parameter RAM - */ - - pram_ptr->sen_genscc.scc_rfcr = 0x18; /* Normal Operation and Mot byte ordering */ - pram_ptr->sen_genscc.scc_tfcr = 0x18; /* Mot byte ordering, Normal access */ - - pram_ptr->sen_genscc.scc_mrblr = DBUF_LENGTH; /* max. ET package len 1520 */ - - pram_ptr->sen_genscc.scc_rbase = (unsigned int) (&rtx->rxbd[0]); /* Set RXBD tbl start at Dual Port */ - pram_ptr->sen_genscc.scc_tbase = (unsigned int) (&rtx->txbd[0]); /* Set TXBD tbl start at Dual Port */ - - /* - * Setup Receiver Buffer Descriptors (13.14.24.18) - * Settings: - * Empty, Wrap - */ - - for (i = 0; i < PKTBUFSRX; i++) { - rtx->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; - rtx->rxbd[i].cbd_datlen = 0; /* Reset */ - rtx->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; - } - - rtx->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; - - /* - * Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) - * Settings: - * Add PADs to Short FRAMES, Wrap, Last, Tx CRC - */ - - for (i = 0; i < TX_BUF_CNT; i++) { - rtx->txbd[i].cbd_sc = - (BD_ENET_TX_PAD | BD_ENET_TX_LAST | BD_ENET_TX_TC); - rtx->txbd[i].cbd_datlen = 0; /* Reset */ - rtx->txbd[i].cbd_bufaddr = (uint) (&txbuf[0]); - } - - rtx->txbd[TX_BUF_CNT - 1].cbd_sc |= BD_ENET_TX_WRAP; - - /* - * Enter Command: Initialize Rx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_RX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Ethernet Specific Parameter RAM - * see table 13-16, pg. 660, - * pg. 681 (example with suggested settings) - */ - - pram_ptr->sen_cpres = ~(0x0); /* Preset CRC */ - pram_ptr->sen_cmask = 0xdebb20e3; /* Constant Mask for CRC */ - pram_ptr->sen_crcec = 0x0; /* Error Counter CRC (unused) */ - pram_ptr->sen_alec = 0x0; /* Alignment Error Counter (unused) */ - pram_ptr->sen_disfc = 0x0; /* Discard Frame Counter (unused) */ - pram_ptr->sen_pads = 0x8888; /* Short Frame PAD Characters */ - - pram_ptr->sen_retlim = 15; /* Retry Limit Threshold */ - pram_ptr->sen_maxflr = 1518; /* MAX Frame Length Register */ - pram_ptr->sen_minflr = 64; /* MIN Frame Length Register */ - - pram_ptr->sen_maxd1 = DBUF_LENGTH; /* MAX DMA1 Length Register */ - pram_ptr->sen_maxd2 = DBUF_LENGTH; /* MAX DMA2 Length Register */ - - pram_ptr->sen_gaddr1 = 0x0; /* Group Address Filter 1 (unused) */ - pram_ptr->sen_gaddr2 = 0x0; /* Group Address Filter 2 (unused) */ - pram_ptr->sen_gaddr3 = 0x0; /* Group Address Filter 3 (unused) */ - pram_ptr->sen_gaddr4 = 0x0; /* Group Address Filter 4 (unused) */ - -#define ea bd->bi_enetaddr - pram_ptr->sen_paddrh = (ea[5] << 8) + ea[4]; - pram_ptr->sen_paddrm = (ea[3] << 8) + ea[2]; - pram_ptr->sen_paddrl = (ea[1] << 8) + ea[0]; -#undef ea - - pram_ptr->sen_pper = 0x0; /* Persistence (unused) */ - pram_ptr->sen_iaddr1 = 0x0; /* Individual Address Filter 1 (unused) */ - pram_ptr->sen_iaddr2 = 0x0; /* Individual Address Filter 2 (unused) */ - pram_ptr->sen_iaddr3 = 0x0; /* Individual Address Filter 3 (unused) */ - pram_ptr->sen_iaddr4 = 0x0; /* Individual Address Filter 4 (unused) */ - pram_ptr->sen_taddrh = 0x0; /* Tmp Address (MSB) (unused) */ - pram_ptr->sen_taddrm = 0x0; /* Tmp Address (unused) */ - pram_ptr->sen_taddrl = 0x0; /* Tmp Address (LSB) (unused) */ - - /* - * Enter Command: Initialize Tx Params for SCC - */ - - do { /* Spin until ready to issue command */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - /* Issue command */ - immr->im_cpm.cp_cpcr = - ((CPM_CR_INIT_TX << 8) | (cpm_cr[scc_index] << 4) | - CPM_CR_FLG); - do { /* Spin until command processed */ - __asm__ ("eieio"); - } while (immr->im_cpm.cp_cpcr & CPM_CR_FLG); - - /* - * Mask all Events in SCCM - we use polling mode - */ - immr->im_cpm.cp_scc[scc_index].scc_sccm = 0; - - /* - * Clear Events in SCCE -- Clear bits by writing 1's - */ - - immr->im_cpm.cp_scc[scc_index].scc_scce = ~(0x0); - - - /* - * Initialize GSMR High 32-Bits - * Settings: Normal Mode - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrh = 0; - - /* - * Initialize GSMR Low 32-Bits, but do not Enable Transmit/Receive - * Settings: - * TCI = Invert - * TPL = 48 bits - * TPP = Repeating 10's - * LOOP = Loopback - * MODE = Ethernet - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl = (SCC_GSMRL_TCI | - SCC_GSMRL_TPL_48 | - SCC_GSMRL_TPP_10 | - SCC_GSMRL_DIAG_LOOP | - SCC_GSMRL_MODE_ENET); - - /* - * Initialize the DSR -- see section 13.14.4 (pg. 513) v0.4 - */ - - immr->im_cpm.cp_scc[scc_index].scc_dsr = 0xd555; - - /* - * Initialize the PSMR - * Settings: - * CRC = 32-Bit CCITT - * NIB = Begin searching for SFD 22 bits after RENA - * LPB = Loopback Enable (Needed when FDE is set) - */ - immr->im_cpm.cp_scc[scc_index].scc_psmr = SCC_PSMR_ENCRC | - SCC_PSMR_NIB22 | SCC_PSMR_LPB; - -#if 0 - /* - * Configure Ethernet TENA Signal - */ - -#if (defined(PC_ENET_TENA) && !defined(PB_ENET_TENA)) - immr->im_ioport.iop_pcpar |= PC_ENET_TENA; - immr->im_ioport.iop_pcdir &= ~PC_ENET_TENA; -#elif (defined(PB_ENET_TENA) && !defined(PC_ENET_TENA)) - immr->im_cpm.cp_pbpar |= PB_ENET_TENA; - immr->im_cpm.cp_pbdir |= PB_ENET_TENA; -#else -#error Configuration Error: exactly ONE of PB_ENET_TENA, PC_ENET_TENA must be defined -#endif - -#if defined(CONFIG_ADS) && defined(CONFIG_MPC860) - /* - * Port C is used to control the PHY,MC68160. - */ - immr->im_ioport.iop_pcdir |= - (PC_ENET_ETHLOOP | PC_ENET_TPFLDL | PC_ENET_TPSQEL); - - immr->im_ioport.iop_pcdat |= PC_ENET_TPFLDL; - immr->im_ioport.iop_pcdat &= ~(PC_ENET_ETHLOOP | PC_ENET_TPSQEL); - *((uint *) BCSR1) &= ~BCSR1_ETHEN; -#endif /* MPC860ADS */ - -#if defined(CONFIG_AMX860) - /* - * Port B is used to control the PHY,MC68160. - */ - immr->im_cpm.cp_pbdir |= - (PB_ENET_ETHLOOP | PB_ENET_TPFLDL | PB_ENET_TPSQEL); - - immr->im_cpm.cp_pbdat |= PB_ENET_TPFLDL; - immr->im_cpm.cp_pbdat &= ~(PB_ENET_ETHLOOP | PB_ENET_TPSQEL); - - immr->im_ioport.iop_pddir |= PD_ENET_ETH_EN; - immr->im_ioport.iop_pddat &= ~PD_ENET_ETH_EN; -#endif /* AMX860 */ - -#endif /* 0 */ - -#ifdef CONFIG_RPXCLASSIC - *((uchar *) BCSR0) &= ~BCSR0_ETHLPBK; - *((uchar *) BCSR0) |= (BCSR0_ETHEN | BCSR0_COLTEST | BCSR0_FULLDPLX); -#endif - -#ifdef CONFIG_RPXLITE - *((uchar *) BCSR0) |= BCSR0_ETHEN; -#endif - -#ifdef CONFIG_MBX - board_ether_init (); -#endif - - /* - * Set the ENT/ENR bits in the GSMR Low -- Enable Transmit/Receive - */ - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl |= - (SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - /* - * Work around transmit problem with first eth packet - */ -#if defined (CONFIG_FADS) - udelay (10000); /* wait 10 ms */ -#elif defined (CONFIG_AMX860) || defined(CONFIG_RPXCLASSIC) - udelay (100000); /* wait 100 ms */ -#endif -} - -static void scc_halt (int scc_index) -{ - volatile immap_t *immr = (immap_t *) CFG_IMMR; - - immr->im_cpm.cp_scc[scc_index].scc_gsmrl &= - ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - immr->im_ioport.iop_pcso &= ~(PC_ENET_CLSN | PC_ENET_RENA); -} - -static int scc_send (int index, volatile void *packet, int length) -{ - int i, j = 0; - - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX not ready\n"); - rtx->txbd[txIdx].cbd_bufaddr = (uint) packet; - rtx->txbd[txIdx].cbd_datlen = length; - rtx->txbd[txIdx].cbd_sc |= - (BD_ENET_TX_READY | BD_ENET_TX_LAST | BD_ENET_TX_WRAP); - while ((rtx->txbd[txIdx].cbd_sc & BD_ENET_TX_READY) && (j < TOUT_LOOP)) { - udelay (1); /* will also trigger Wd if needed */ - j++; - } - if (j >= TOUT_LOOP) - printf ("TX timeout\n"); - i = (rtx->txbd[txIdx]. - cbd_sc & BD_ENET_TX_STATS) /* return only status bits */ ; - return i; -} - -static int scc_recv (int index, void *packet, int max_length) -{ - int length = -1; - - if (rtx->rxbd[rxIdx].cbd_sc & BD_ENET_RX_EMPTY) { - goto Done; /* nothing received */ - } - - if (!(rtx->rxbd[rxIdx].cbd_sc & 0x003f)) { - length = rtx->rxbd[rxIdx].cbd_datlen - 4; - memcpy (packet, - (void *) (NetRxPackets[rxIdx]), - length < max_length ? length : max_length); - } - - /* Give the buffer back to the SCC. */ - rtx->rxbd[rxIdx].cbd_datlen = 0; - - /* wrap around buffer index when necessary */ - if ((rxIdx + 1) >= PKTBUFSRX) { - rtx->rxbd[PKTBUFSRX - 1].cbd_sc = - (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); - rxIdx = 0; - } else { - rtx->rxbd[rxIdx].cbd_sc = BD_ENET_RX_EMPTY; - rxIdx++; - } - -Done: - return length; -} - - /* - * Test routines - */ - -static void packet_fill (char *packet, int length) -{ - char c = (char) length; - int i; - - packet[0] = 0xFF; - packet[1] = 0xFF; - packet[2] = 0xFF; - packet[3] = 0xFF; - packet[4] = 0xFF; - packet[5] = 0xFF; - - for (i = 6; i < length; i++) { - packet[i] = c++; - } -} - -static int packet_check (char *packet, int length) -{ - char c = (char) length; - int i; - - for (i = 6; i < length; i++) { - if (packet[i] != c++) - return -1; - } - - return 0; -} - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char packet_send[MAX_PACKET_LENGTH]; - char packet_recv[MAX_PACKET_LENGTH]; - int length; - int i; - int l; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < TEST_NUM; i++) { - for (l = MIN_PACKET_LENGTH; l <= MAX_PACKET_LENGTH; l++) { - packet_fill (packet_send, l); - - ctlr_proc[ctlr].send (index, packet_send, l); - - length = ctlr_proc[ctlr].recv (index, packet_recv, - MAX_PACKET_LENGTH); - - if (length != l || packet_check (packet_recv, length) < 0) { - goto Done; - } - } - } - - res = 0; - -Done: - - ctlr_proc[ctlr].halt (index); - - /* - * SCC2 Ethernet parameter RAM space overlaps - * the SPI parameter RAM space. So we need to restore - * the SPI configuration after SCC2 ethernet test. - */ -#if defined(CONFIG_SPI) - if (ctlr == CTLR_SCC && index == 1) { - spi_init_f (); - spi_init_r (); - } -#endif - - if (res != 0) { - post_log ("ethernet %s%d test failed\n", ctlr_name[ctlr], - index + 1); - } - - return res; -} - -int ether_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].send = scc_send; - ctlr_proc[CTLR_SCC].recv = scc_recv; - - for (i = 0; i < CTRL_LIST_SIZE; i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - return res; -} - -#endif /* CONFIG_POST & CFG_POST_ETHER */ - -#endif /* CONFIG_POST */ diff --git a/post/i2c.c b/post/i2c.c deleted file mode 100644 index 1b2e644..0000000 --- a/post/i2c.c +++ /dev/null @@ -1,94 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -#ifdef CONFIG_POST - -/* - * I2C test - * - * For verifying the I2C bus, a full I2C bus scanning is performed. - * - * #ifdef I2C_ADDR_LIST - * The test is considered as passed if all the devices and - * only the devices in the list are found. - * #else [ ! I2C_ADDR_LIST ] - * The test is considered as passed if any I2C device is found. - * #endif - */ - -#include <post.h> -#include <i2c.h> - -#if CONFIG_POST & CFG_POST_I2C - -int i2c_post_test (int flags) -{ - unsigned int i; - unsigned int good = 0; -#ifdef I2C_ADDR_LIST - unsigned int bad = 0; - int j; - unsigned char i2c_addr_list[] = I2C_ADDR_LIST; - unsigned char i2c_miss_list[] = I2C_ADDR_LIST; -#endif - - for (i = 0; i < 128; i++) { - if (i2c_probe (i) == 0) { -#ifndef I2C_ADDR_LIST - good++; -#else /* I2C_ADDR_LIST */ - for (j=0; j<sizeof(i2c_addr_list); ++j) { - if (i == i2c_addr_list[j]) { - good++; - i2c_miss_list[j] = 0xFF; - break; - } - } - if (j == sizeof(i2c_addr_list)) { - bad++; - post_log ("I2C: addr %02X not expected\n", - i); - } -#endif /* I2C_ADDR_LIST */ - } - } - -#ifndef I2C_ADDR_LIST - return good > 0 ? 0 : -1; -#else /* I2C_ADDR_LIST */ - if (good != sizeof(i2c_addr_list)) { - for (j=0; j<sizeof(i2c_miss_list); ++j) { - if (i2c_miss_list[j] != 0xFF) { - post_log ("I2C: addr %02X did not respond\n", - i2c_miss_list[j]); - } - } - } - return ((good == sizeof(i2c_addr_list)) && (bad == 0)) ? 0 : -1; -#endif -} - -#endif /* CONFIG_POST & CFG_POST_I2C */ -#endif /* CONFIG_POST */ diff --git a/post/memory.c b/post/memory.c deleted file mode 100644 index a2c088b..0000000 --- a/post/memory.c +++ /dev/null @@ -1,483 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* Memory test - * - * General observations: - * o The recommended test sequence is to test the data lines: if they are - * broken, nothing else will work properly. Then test the address - * lines. Finally, test the cells in the memory now that the test - * program knows that the address and data lines work properly. - * This sequence also helps isolate and identify what is faulty. - * - * o For the address line test, it is a good idea to use the base - * address of the lowest memory location, which causes a '1' bit to - * walk through a field of zeros on the address lines and the highest - * memory location, which causes a '0' bit to walk through a field of - * '1's on the address line. - * - * o Floating buses can fool memory tests if the test routine writes - * a value and then reads it back immediately. The problem is, the - * write will charge the residual capacitance on the data bus so the - * bus retains its state briefely. When the test program reads the - * value back immediately, the capacitance of the bus can allow it - * to read back what was written, even though the memory circuitry - * is broken. To avoid this, the test program should write a test - * pattern to the target location, write a different pattern elsewhere - * to charge the residual capacitance in a differnt manner, then read - * the target location back. - * - * o Always read the target location EXACTLY ONCE and save it in a local - * variable. The problem with reading the target location more than - * once is that the second and subsequent reads may work properly, - * resulting in a failed test that tells the poor technician that - * "Memory error at 00000000, wrote aaaaaaaa, read aaaaaaaa" which - * doesn't help him one bit and causes puzzled phone calls. Been there, - * done that. - * - * Data line test: - * --------------- - * This tests data lines for shorts and opens by forcing adjacent data - * to opposite states. Because the data lines could be routed in an - * arbitrary manner the must ensure test patterns ensure that every case - * is tested. By using the following series of binary patterns every - * combination of adjacent bits is test regardless of routing. - * - * ...101010101010101010101010 - * ...110011001100110011001100 - * ...111100001111000011110000 - * ...111111110000000011111111 - * - * Carrying this out, gives us six hex patterns as follows: - * - * 0xaaaaaaaaaaaaaaaa - * 0xcccccccccccccccc - * 0xf0f0f0f0f0f0f0f0 - * 0xff00ff00ff00ff00 - * 0xffff0000ffff0000 - * 0xffffffff00000000 - * - * To test for short and opens to other signals on our boards, we - * simply test with the 1's complemnt of the paterns as well, resulting - * in twelve patterns total. - * - * After writing a test pattern. a special pattern 0x0123456789ABCDEF is - * written to a different address in case the data lines are floating. - * Thus, if a byte lane fails, you will see part of the special - * pattern in that byte lane when the test runs. For example, if the - * xx__xxxxxxxxxxxx byte line fails, you will see aa23aaaaaaaaaaaa - * (for the 'a' test pattern). - * - * Address line test: - * ------------------ - * This function performs a test to verify that all the address lines - * hooked up to the RAM work properly. If there is an address line - * fault, it usually shows up as two different locations in the address - * map (related by the faulty address line) mapping to one physical - * memory storage location. The artifact that shows up is writing to - * the first location "changes" the second location. - * - * To test all address lines, we start with the given base address and - * xor the address with a '1' bit to flip one address line. For each - * test, we shift the '1' bit left to test the next address line. - * - * In the actual code, we start with address sizeof(ulong) since our - * test pattern we use is a ulong and thus, if we tried to test lower - * order address bits, it wouldn't work because our pattern would - * overwrite itself. - * - * Example for a 4 bit address space with the base at 0000: - * 0000 <- base - * 0001 <- test 1 - * 0010 <- test 2 - * 0100 <- test 3 - * 1000 <- test 4 - * Example for a 4 bit address space with the base at 0010: - * 0010 <- base - * 0011 <- test 1 - * 0000 <- (below the base address, skipped) - * 0110 <- test 2 - * 1010 <- test 3 - * - * The test locations are successively tested to make sure that they are - * not "mirrored" onto the base address due to a faulty address line. - * Note that the base and each test location are related by one address - * line flipped. Note that the base address need not be all zeros. - * - * Memory tests 1-4: - * ----------------- - * These tests verify RAM using sequential writes and reads - * to/from RAM. There are several test cases that use different patterns to - * verify RAM. Each test case fills a region of RAM with one pattern and - * then reads the region back and compares its contents with the pattern. - * The following patterns are used: - * - * 1a) zero pattern (0x00000000) - * 1b) negative pattern (0xffffffff) - * 1c) checkerboard pattern (0x55555555) - * 1d) checkerboard pattern (0xaaaaaaaa) - * 2) bit-flip pattern ((1 << (offset % 32)) - * 3) address pattern (offset) - * 4) address pattern (~offset) - * - * Being run in normal mode, the test verifies only small 4Kb - * regions of RAM around each 1Mb boundary. For example, for 64Mb - * RAM the following areas are verified: 0x00000000-0x00000800, - * 0x000ff800-0x00100800, 0x001ff800-0x00200800, ..., 0x03fff800- - * 0x04000000. If the test is run in slow-test mode, it verifies - * the whole RAM. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include <watchdog.h> - -#if CONFIG_POST & CFG_POST_MEMORY - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Define INJECT_*_ERRORS for testing error detection in the presence of - * _good_ hardware. - */ -#undef INJECT_DATA_ERRORS -#undef INJECT_ADDRESS_ERRORS - -#ifdef INJECT_DATA_ERRORS -#warning "Injecting data line errors for testing purposes" -#endif - -#ifdef INJECT_ADDRESS_ERRORS -#warning "Injecting address line errors for testing purposes" -#endif - - -/* - * This function performs a double word move from the data at - * the source pointer to the location at the destination pointer. - * This is helpful for testing memory on processors which have a 64 bit - * wide data bus. - * - * On those PowerPC with FPU, use assembly and a floating point move: - * this does a 64 bit move. - * - * For other processors, let the compiler generate the best code it can. - */ -static void move64(unsigned long long *src, unsigned long long *dest) -{ -#if defined(CONFIG_MPC8260) || defined(CONFIG_MPC824X) - asm ("lfd 0, 0(3)\n\t" /* fpr0 = *scr */ - "stfd 0, 0(4)" /* *dest = fpr0 */ - : : : "fr0" ); /* Clobbers fr0 */ - return; -#else - *dest = *src; -#endif -} - -/* - * This is 64 bit wide test patterns. Note that they reside in ROM - * (which presumably works) and the tests write them to RAM which may - * not work. - * - * The "otherpattern" is written to drive the data bus to values other - * than the test pattern. This is for detecting floating bus lines. - * - */ -const static unsigned long long pattern[] = { - 0xaaaaaaaaaaaaaaaaULL, - 0xccccccccccccccccULL, - 0xf0f0f0f0f0f0f0f0ULL, - 0xff00ff00ff00ff00ULL, - 0xffff0000ffff0000ULL, - 0xffffffff00000000ULL, - 0x00000000ffffffffULL, - 0x0000ffff0000ffffULL, - 0x00ff00ff00ff00ffULL, - 0x0f0f0f0f0f0f0f0fULL, - 0x3333333333333333ULL, - 0x5555555555555555ULL -}; -const unsigned long long otherpattern = 0x0123456789abcdefULL; - - -static int memory_post_dataline(unsigned long long * pmem) -{ - unsigned long long temp64 = 0; - int num_patterns = sizeof(pattern)/ sizeof(pattern[0]); - int i; - unsigned int hi, lo, pathi, patlo; - int ret = 0; - - for ( i = 0; i < num_patterns; i++) { - move64((unsigned long long *)&(pattern[i]), pmem++); - /* - * Put a different pattern on the data lines: otherwise they - * may float long enough to read back what we wrote. - */ - move64((unsigned long long *)&otherpattern, pmem--); - move64(pmem, &temp64); - -#ifdef INJECT_DATA_ERRORS - temp64 ^= 0x00008000; -#endif - - if (temp64 != pattern[i]){ - pathi = (pattern[i]>>32) & 0xffffffff; - patlo = pattern[i] & 0xffffffff; - - hi = (temp64>>32) & 0xffffffff; - lo = temp64 & 0xffffffff; - - post_log ("Memory (date line) error at %08x, " - "wrote %08x%08x, read %08x%08x !\n", - pmem, pathi, patlo, hi, lo); - ret = -1; - } - } - return ret; -} - -static int memory_post_addrline(ulong *testaddr, ulong *base, ulong size) -{ - ulong *target; - ulong *end; - ulong readback; - ulong xor; - int ret = 0; - - end = (ulong *)((ulong)base + size); /* pointer arith! */ - xor = 0; - for(xor = sizeof(ulong); xor > 0; xor <<= 1) { - target = (ulong *)((ulong)testaddr ^ xor); - if((target >= base) && (target < end)) { - *testaddr = ~*target; - readback = *target; - -#ifdef INJECT_ADDRESS_ERRORS - if(xor == 0x00008000) { - readback = *testaddr; - } -#endif - if(readback == *testaddr) { - post_log ("Memory (address line) error at %08x<->%08x, " - "XOR value %08x !\n", - testaddr, target, xor); - ret = -1; - } - } - } - return ret; -} - -static int memory_post_test1 (unsigned long start, - unsigned long size, - unsigned long val) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = val; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != val) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, val, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test2 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = 1 << (i % 32); - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != (1 << (i % 32))) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, 1 << (i % 32), readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test3 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_test4 (unsigned long start, unsigned long size) -{ - unsigned long i; - ulong *mem = (ulong *) start; - ulong readback; - int ret = 0; - - for (i = 0; i < size / sizeof (ulong); i++) { - mem[i] = ~i; - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - for (i = 0; i < size / sizeof (ulong) && ret == 0; i++) { - readback = mem[i]; - if (readback != ~i) { - post_log ("Memory error at %08x, " - "wrote %08x, read %08x !\n", - mem + i, ~i, readback); - - ret = -1; - break; - } - if (i % 1024 == 0) - WATCHDOG_RESET (); - } - - return ret; -} - -static int memory_post_tests (unsigned long start, unsigned long size) -{ - int ret = 0; - - if (ret == 0) - ret = memory_post_dataline ((unsigned long long *)start); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)start, (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_addrline ((ulong *)(start + size - 8), - (ulong *)start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x00000000); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xffffffff); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0x55555555); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test1 (start, size, 0xaaaaaaaa); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test2 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test3 (start, size); - WATCHDOG_RESET (); - if (ret == 0) - ret = memory_post_test4 (start, size); - WATCHDOG_RESET (); - - return ret; -} - -int memory_post_test (int flags) -{ - int ret = 0; - bd_t *bd = gd->bd; - unsigned long memsize = (bd->bi_memsize >= 256 << 20 ? - 256 << 20 : bd->bi_memsize) - (1 << 20); - - - if (flags & POST_SLOWTEST) { - ret = memory_post_tests (CFG_SDRAM_BASE, memsize); - } else { /* POST_NORMAL */ - - unsigned long i; - - for (i = 0; i < (memsize >> 20) && ret == 0; i++) { - if (ret == 0) - ret = memory_post_tests (i << 20, 0x800); - if (ret == 0) - ret = memory_post_tests ((i << 20) + 0xff800, 0x800); - } - } - - return ret; -} - -#endif /* CONFIG_POST & CFG_POST_MEMORY */ -#endif /* CONFIG_POST */ diff --git a/post/rtc.c b/post/rtc.c deleted file mode 100644 index 7d4f9b8..0000000 --- a/post/rtc.c +++ /dev/null @@ -1,183 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * RTC test - * - * The Real Time Clock (RTC) operation is verified by this test. - * The following features are verified: - * o) Time uniformity - * This is verified by reading RTC in polling within - * a short period of time. - * o) Passing month boundaries - * This is checked by setting RTC to a second before - * a month boundary and reading it after its passing the - * boundary. The test is performed for both leap- and - * nonleap-years. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include <rtc.h> - -#if CONFIG_POST & CFG_POST_RTC - -static int rtc_post_skip (ulong * diff) -{ - struct rtc_time tm1; - struct rtc_time tm2; - ulong start1; - ulong start2; - - rtc_get (&tm1); - start1 = get_timer (0); - - while (1) { - rtc_get (&tm2); - start2 = get_timer (0); - if (tm1.tm_sec != tm2.tm_sec) - break; - if (start2 - start1 > 1500) - break; - } - - if (tm1.tm_sec != tm2.tm_sec) { - *diff = start2 - start1; - - return 0; - } else { - return -1; - } -} - -static void rtc_post_restore (struct rtc_time *tm, unsigned int sec) -{ - time_t t = mktime (tm->tm_year, tm->tm_mon, tm->tm_mday, tm->tm_hour, - tm->tm_min, tm->tm_sec) + sec; - struct rtc_time ntm; - - to_tm (t, &ntm); - - rtc_set (&ntm); -} - -int rtc_post_test (int flags) -{ - ulong diff; - unsigned int i; - struct rtc_time svtm; - static unsigned int daysnl[] = - { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; - static unsigned int daysl[] = - { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; - unsigned int ynl = 1999; - unsigned int yl = 2000; - unsigned int skipped = 0; - - /* Time uniformity */ - if (rtc_post_skip (&diff) != 0) { - post_log ("Timeout while waiting for a new second !\n"); - - return -1; - } - - for (i = 0; i < 5; i++) { - if (rtc_post_skip (&diff) != 0) { - post_log ("Timeout while waiting for a new second !\n"); - - return -1; - } - - if (diff < 950 || diff > 1050) { - post_log ("Invalid second duration !\n"); - - return -1; - } - } - - /* Passing month boundaries */ - - if (rtc_post_skip (&diff) != 0) { - post_log ("Timeout while waiting for a new second !\n"); - - return -1; - } - rtc_get (&svtm); - - for (i = 0; i < 12; i++) { - time_t t = mktime (ynl, i + 1, daysnl[i], 23, 59, 59); - struct rtc_time tm; - - to_tm (t, &tm); - rtc_set (&tm); - - skipped++; - if (rtc_post_skip (&diff) != 0) { - rtc_post_restore (&svtm, skipped); - post_log ("Timeout while waiting for a new second !\n"); - - return -1; - } - - rtc_get (&tm); - if (tm.tm_mon == i + 1) { - rtc_post_restore (&svtm, skipped); - post_log ("Month %d boundary is not passed !\n", i + 1); - - return -1; - } - } - - for (i = 0; i < 12; i++) { - time_t t = mktime (yl, i + 1, daysl[i], 23, 59, 59); - struct rtc_time tm; - - to_tm (t, &tm); - rtc_set (&tm); - - skipped++; - if (rtc_post_skip (&diff) != 0) { - rtc_post_restore (&svtm, skipped); - post_log ("Timeout while waiting for a new second !\n"); - - return -1; - } - - rtc_get (&tm); - if (tm.tm_mon == i + 1) { - rtc_post_restore (&svtm, skipped); - post_log ("Month %d boundary is not passed !\n", i + 1); - - return -1; - } - } - rtc_post_restore (&svtm, skipped); - - return 0; -} - -#endif /* CONFIG_POST & CFG_POST_RTC */ -#endif /* CONFIG_POST */ diff --git a/post/spr.c b/post/spr.c deleted file mode 100644 index 330b977..0000000 --- a/post/spr.c +++ /dev/null @@ -1,152 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * SPR test - * - * The test checks the contents of Special Purpose Registers (SPR) listed - * in the spr_test_list array below. - * Each SPR value is read using mfspr instruction, some bits are masked - * according to the table and the resulting value is compared to the - * corresponding table value. - */ - -#ifdef CONFIG_POST - -#include <post.h> - -#if CONFIG_POST & CFG_POST_SPR - -static struct -{ - int number; - char * name; - unsigned long mask; - unsigned long value; -} spr_test_list [] = { - /* Standard Special-Purpose Registers */ - - {1, "XER", 0x00000000, 0x00000000}, - {8, "LR", 0x00000000, 0x00000000}, - {9, "CTR", 0x00000000, 0x00000000}, - {18, "DSISR", 0x00000000, 0x00000000}, - {19, "DAR", 0x00000000, 0x00000000}, - {22, "DEC", 0x00000000, 0x00000000}, - {26, "SRR0", 0x00000000, 0x00000000}, - {27, "SRR1", 0x00000000, 0x00000000}, - {272, "SPRG0", 0x00000000, 0x00000000}, - {273, "SPRG1", 0x00000000, 0x00000000}, - {274, "SPRG2", 0x00000000, 0x00000000}, - {275, "SPRG3", 0x00000000, 0x00000000}, - {287, "PVR", 0xFFFF0000, 0x00500000}, - - /* Additional Special-Purpose Registers */ - - {144, "CMPA", 0x00000000, 0x00000000}, - {145, "CMPB", 0x00000000, 0x00000000}, - {146, "CMPC", 0x00000000, 0x00000000}, - {147, "CMPD", 0x00000000, 0x00000000}, - {148, "ICR", 0xFFFFFFFF, 0x00000000}, - {149, "DER", 0x00000000, 0x00000000}, - {150, "COUNTA", 0xFFFFFFFF, 0x00000000}, - {151, "COUNTB", 0xFFFFFFFF, 0x00000000}, - {152, "CMPE", 0x00000000, 0x00000000}, - {153, "CMPF", 0x00000000, 0x00000000}, - {154, "CMPG", 0x00000000, 0x00000000}, - {155, "CMPH", 0x00000000, 0x00000000}, - {156, "LCTRL1", 0xFFFFFFFF, 0x00000000}, - {157, "LCTRL2", 0xFFFFFFFF, 0x00000000}, - {158, "ICTRL", 0xFFFFFFFF, 0x00000007}, - {159, "BAR", 0x00000000, 0x00000000}, - {630, "DPDR", 0x00000000, 0x00000000}, - {631, "DPIR", 0x00000000, 0x00000000}, - {638, "IMMR", 0xFFFF0000, CFG_IMMR }, - {560, "IC_CST", 0x8E380000, 0x00000000}, - {561, "IC_ADR", 0x00000000, 0x00000000}, - {562, "IC_DAT", 0x00000000, 0x00000000}, - {568, "DC_CST", 0xEF380000, 0x00000000}, - {569, "DC_ADR", 0x00000000, 0x00000000}, - {570, "DC_DAT", 0x00000000, 0x00000000}, - {784, "MI_CTR", 0xFFFFFFFF, 0x00000000}, - {786, "MI_AP", 0x00000000, 0x00000000}, - {787, "MI_EPN", 0x00000000, 0x00000000}, - {789, "MI_TWC", 0xFFFFFE02, 0x00000000}, - {790, "MI_RPN", 0x00000000, 0x00000000}, - {816, "MI_DBCAM", 0x00000000, 0x00000000}, - {817, "MI_DBRAM0", 0x00000000, 0x00000000}, - {818, "MI_DBRAM1", 0x00000000, 0x00000000}, - {792, "MD_CTR", 0xFFFFFFFF, 0x04000000}, - {793, "M_CASID", 0xFFFFFFF0, 0x00000000}, - {794, "MD_AP", 0x00000000, 0x00000000}, - {795, "MD_EPN", 0x00000000, 0x00000000}, - {796, "M_TWB", 0x00000003, 0x00000000}, - {797, "MD_TWC", 0x00000003, 0x00000000}, - {798, "MD_RPN", 0x00000000, 0x00000000}, - {799, "M_TW", 0x00000000, 0x00000000}, - {824, "MD_DBCAM", 0x00000000, 0x00000000}, - {825, "MD_DBRAM0", 0x00000000, 0x00000000}, - {826, "MD_DBRAM1", 0x00000000, 0x00000000}, -}; - -static int spr_test_list_size = - sizeof (spr_test_list) / sizeof (spr_test_list[0]); - -int spr_post_test (int flags) -{ - int ret = 0; - int ic = icache_status (); - int i; - - unsigned long code[] = { - 0x7c6002a6, /* mfspr r3,SPR */ - 0x4e800020 /* blr */ - }; - unsigned long (*get_spr) (void) = (void *) code; - - if (ic) - icache_disable (); - - for (i = 0; i < spr_test_list_size; i++) { - int num = spr_test_list[i].number; - - /* mfspr r3,num */ - code[0] = 0x7c6002a6 | ((num & 0x1F) << 16) | ((num & 0x3E0) << 6); - - if ((get_spr () & spr_test_list[i].mask) != - (spr_test_list[i].value & spr_test_list[i].mask)) { - post_log ("The value of %s special register " - "is incorrect: 0x%08X\n", - spr_test_list[i].name, get_spr ()); - ret = -1; - } - } - - if (ic) - icache_enable (); - - return ret; -} -#endif /* CONFIG_POST & CFG_POST_SPR */ -#endif /* CONFIG_POST */ diff --git a/post/sysmon.c b/post/sysmon.c deleted file mode 100644 index f61d598..0000000 --- a/post/sysmon.c +++ /dev/null @@ -1,331 +0,0 @@ -/* - * (C) Copyright 2003 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <post.h> -#include <common.h> - -#ifdef CONFIG_POST - -/* - * SYSMON test - * - * This test performs the system hardware monitoring. - * The test passes when all the following voltages and temperatures - * are within allowed ranges: - * - * Board temperature - * Front temperature - * +3.3V CPU logic - * +5V logic - * +12V PCMCIA - * +12V CCFL - * +5V standby - * - * CCFL is not enabled if temperature values are not within allowed ranges - * - * See the list off all parameters in the sysmon_table below - */ - -#include <post.h> -#include <watchdog.h> -#include <i2c.h> - -#if CONFIG_POST & CFG_POST_SYSMON - -DECLARE_GLOBAL_DATA_PTR; - -static int sysmon_temp_invalid = 0; - -/* #define DEBUG */ - -#define RELOC(x) if (x != NULL) x = (void *) ((ulong) (x) + gd->reloc_off) - -typedef struct sysmon_s sysmon_t; -typedef struct sysmon_table_s sysmon_table_t; - -static void sysmon_lm87_init (sysmon_t * this); -static void sysmon_pic_init (sysmon_t * this); -static uint sysmon_i2c_read (sysmon_t * this, uint addr); -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr); -static void sysmon_ccfl_disable (sysmon_table_t * this); -static void sysmon_ccfl_enable (sysmon_table_t * this); - -struct sysmon_s -{ - uchar chip; - void (*init)(sysmon_t *); - uint (*read)(sysmon_t *, uint); -}; - -static sysmon_t sysmon_lm87 = - {CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read}; -static sysmon_t sysmon_lm87_sgn = - {CFG_I2C_SYSMON_ADDR, sysmon_lm87_init, sysmon_i2c_read_sgn}; -static sysmon_t sysmon_pic = - {CFG_I2C_PICIO_ADDR, sysmon_pic_init, sysmon_i2c_read}; - -static sysmon_t * sysmon_list[] = -{ - &sysmon_lm87, - &sysmon_lm87_sgn, - &sysmon_pic, - NULL -}; - -struct sysmon_table_s -{ - char * name; - char * unit_name; - sysmon_t * sysmon; - void (*exec_before)(sysmon_table_t *); - void (*exec_after)(sysmon_table_t *); - - int unit_precision; - int unit_div; - int unit_min; - int unit_max; - uint val_mask; - uint val_min; - uint val_max; - int val_valid; - uint val_min_alt; - uint val_max_alt; - int val_valid_alt; - uint addr; -}; - -static sysmon_table_t sysmon_table[] = -{ - {"Board temperature", " C", &sysmon_lm87_sgn, NULL, sysmon_ccfl_disable, - 1, 1, -128, 127, 0xFF, 0x58, 0xD5, 0, 0x6C, 0xC6, 0, 0x27}, - - {"Front temperature", " C", &sysmon_lm87, NULL, sysmon_ccfl_disable, - 1, 100, -27316, 8984, 0xFF, 0xA4, 0xFC, 0, 0xB2, 0xF1, 0, 0x29}, - - {"+3.3V CPU logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 4386, 0xFF, 0xB6, 0xC9, 0, 0xB6, 0xC9, 0, 0x22}, - - {"+ 5 V logic", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 6630, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x23}, - - {"+12 V PCMCIA", "V", &sysmon_lm87, NULL, NULL, - 100, 1000, 0, 15460, 0xFF, 0xBC, 0xD0, 0, 0xBC, 0xD0, 0, 0x21}, - - {"+12 V CCFL", "V", &sysmon_lm87, NULL, sysmon_ccfl_enable, - 100, 1000, 0, 15900, 0xFF, 0xB6, 0xCA, 0, 0xB6, 0xCA, 0, 0x24}, - - {"+ 5 V standby", "V", &sysmon_pic, NULL, NULL, - 100, 1000, 0, 6040, 0xFF, 0xC8, 0xDE, 0, 0xC8, 0xDE, 0, 0x7C}, -}; -static int sysmon_table_size = sizeof(sysmon_table) / sizeof(sysmon_table[0]); - -static int conversion_done = 0; - - -int sysmon_init_f (void) -{ - sysmon_t ** l; - ulong reg; - - /* Power on CCFL, PCMCIA */ - reg = pic_read (0x60); - reg |= 0x09; - pic_write (0x60, reg); - - for (l = sysmon_list; *l; l++) { - (*l)->init(*l); - } - - return 0; -} - -void sysmon_reloc (void) -{ - sysmon_t ** l; - sysmon_table_t * t; - - for (l = sysmon_list; *l; l++) { - RELOC(*l); - RELOC((*l)->init); - RELOC((*l)->read); - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - RELOC(t->exec_before); - RELOC(t->exec_after); - RELOC(t->sysmon); - } -} - -static char *sysmon_unit_value (sysmon_table_t *s, uint val) -{ - static char buf[32]; - int unit_val = - s->unit_min + (s->unit_max - s->unit_min) * val / s->val_mask; - char *p, sign; - int dec, frac; - - if (val == -1) { - return "I/O ERROR"; - } - - if (unit_val < 0) { - sign = '-'; - unit_val = -unit_val; - } else { - sign = '+'; - } - - p = buf + sprintf(buf, "%c%2d", sign, unit_val / s->unit_div); - - - frac = unit_val % s->unit_div; - - frac /= (s->unit_div / s->unit_precision); - - dec = s->unit_precision; - - if (dec != 1) { - *p++ = '.'; - } - for (dec /= 10; dec != 0; dec /= 10) { - *p++ = '0' + (frac / dec) % 10; - } - strcpy(p, s->unit_name); - - return buf; -} - -static void sysmon_lm87_init (sysmon_t * this) -{ - uchar val; - - /* Detect LM87 chip */ - if (i2c_read(this->chip, 0x40, 1, &val, 1) || (val & 0x80) != 0 || - i2c_read(this->chip, 0x3E, 1, &val, 1) || val != 0x02) { - printf("Error: LM87 not found at 0x%02X\n", this->chip); - return; - } - - /* Configure pins 5,6 as AIN */ - val = 0x03; - if (i2c_write(this->chip, 0x16, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } - - /* Start monitoring */ - val = 0x01; - if (i2c_write(this->chip, 0x40, 1, &val, 1)) { - printf("Error: can't write LM87 config register\n"); - return; - } -} - -static void sysmon_pic_init (sysmon_t * this) -{ -} - -static uint sysmon_i2c_read (sysmon_t * this, uint addr) -{ - uchar val; - uint res = i2c_read(this->chip, addr, 1, &val, 1); - - return res == 0 ? val : -1; -} - -static uint sysmon_i2c_read_sgn (sysmon_t * this, uint addr) -{ - uchar val; - return i2c_read(this->chip, addr, 1, &val, 1) == 0 ? - 128 + (signed char)val : -1; -} - -static void sysmon_ccfl_disable (sysmon_table_t * this) -{ - if (!this->val_valid_alt) { - sysmon_temp_invalid = 1; - } -} - -static void sysmon_ccfl_enable (sysmon_table_t * this) -{ - ulong reg; - - if (!sysmon_temp_invalid) { - reg = pic_read (0x60); - reg |= 0x06; - pic_write (0x60, reg); - } -} - -int sysmon_post_test (int flags) -{ - int res = 0; - sysmon_table_t * t; - uint val; - - /* - * The A/D conversion on the LM87 sensor takes 300 ms. - */ - if (! conversion_done) { - while (post_time_ms(gd->post_init_f_time) < 300) WATCHDOG_RESET (); - conversion_done = 1; - } - - for (t = sysmon_table; t < sysmon_table + sysmon_table_size; t ++) { - if (t->exec_before) { - t->exec_before(t); - } - - val = t->sysmon->read(t->sysmon, t->addr); - if (val != -1) { - t->val_valid = val >= t->val_min && val <= t->val_max; - t->val_valid_alt = val >= t->val_min_alt && val <= t->val_max_alt; - } else { - t->val_valid = 0; - t->val_valid_alt = 0; - } - - if (t->exec_after) { - t->exec_after(t); - } - - if ((!t->val_valid) || (flags & POST_MANUAL)) { - printf("%-17s = %-10s ", t->name, sysmon_unit_value(t, val)); - printf("allowed range"); - printf(" %-8s ..", sysmon_unit_value(t, t->val_min)); - printf(" %-8s", sysmon_unit_value(t, t->val_max)); - printf(" %s\n", t->val_valid ? "OK" : "FAIL"); - } - - if (!t->val_valid) { - res = -1; - } - } - - return res; -} - -#endif /* CONFIG_POST & CFG_POST_SYSMON */ -#endif /* CONFIG_POST */ diff --git a/post/uart.c b/post/uart.c deleted file mode 100644 index fd97e38..0000000 --- a/post/uart.c +++ /dev/null @@ -1,560 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * UART test - * - * The Serial Management Controllers (SMC) and the Serial Communication - * Controllers (SCC) listed in ctlr_list array below are tested in - * the loopback UART mode. - * The controllers are configured accordingly and several characters - * are transmitted. The configurable test parameters are: - * MIN_PACKET_LENGTH - minimum size of packet to transmit - * MAX_PACKET_LENGTH - maximum size of packet to transmit - * TEST_NUM - number of tests - */ - -#ifdef CONFIG_POST - -#include <post.h> -#if CONFIG_POST & CFG_POST_UART -#if defined(CONFIG_8xx) -#include <commproc.h> -#elif defined(CONFIG_MPC8260) -#include <asm/cpm_8260.h> -#else -#error "Apparently a bad configuration, please fix." -#endif -#include <command.h> -#include <serial.h> - -DECLARE_GLOBAL_DATA_PTR; - -#define CTLR_SMC 0 -#define CTLR_SCC 1 - -/* The list of controllers to test */ -#if defined(CONFIG_MPC823) -static int ctlr_list[][2] = - { {CTLR_SMC, 0}, {CTLR_SMC, 1}, {CTLR_SCC, 1} }; -#else -static int ctlr_list[][2] = { }; -#endif - -#define CTRL_LIST_SIZE (sizeof(ctlr_list) / sizeof(ctlr_list[0])) - -static struct { - void (*init) (int index); - void (*halt) (int index); - void (*putc) (int index, const char c); - int (*getc) (int index); -} ctlr_proc[2]; - -static char *ctlr_name[2] = { "SMC", "SCC" }; - -static int proff_smc[] = { PROFF_SMC1, PROFF_SMC2 }; -static int proff_scc[] = - { PROFF_SCC1, PROFF_SCC2, PROFF_SCC3, PROFF_SCC4 }; - -/* - * SMC callbacks - */ - -static void smc_init (int smc_index) -{ - static int cpm_cr_ch[] = { CPM_CR_CH_SMC1, CPM_CR_CH_SMC2 }; - - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile smc_t *sp; - volatile smc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SMC */ - - sp = (smc_t *) & (cp->cp_smc[smc_index]); - up = (smc_uart_t *) & cp->cp_dparam[proff_smc[smc_index]]; - - /* Disable transmitter/receiver. - */ - sp->smc_smcmr &= ~(SMCMR_REN | SMCMR_TEN); - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 1; - - /* clear error conditions */ -#ifdef CFG_SDSR - im->im_sdma.sdma_sdsr = CFG_SDSR; -#else - im->im_sdma.sdma_sdsr = 0x83; -#endif - - /* clear SDMA interrupt mask */ -#ifdef CFG_SDMR - im->im_sdma.sdma_sdmr = CFG_SDMR; -#else - im->im_sdma.sdma_sdmr = 0x00; -#endif - -#if defined(CONFIG_FADS) - /* Enable RS232 */ - *((uint *) BCSR1) &= - ~(smc_index == 1 ? BCSR1_RS232EN_1 : BCSR1_RS232EN_2); -#endif - -#if defined(CONFIG_RPXLITE) || defined(CONFIG_RPXCLASSIC) - /* Enable Monitor Port Transceiver */ - *((uchar *) BCSR0) |= BCSR0_ENMONXCVR; -#endif - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8); -#else - dpaddr = CPM_POST_BASE; -#endif - - /* Allocate space for two buffer descriptors in the DP ram. - * For now, this address seems OK, but it may have to - * change with newer versions of the firmware. - * damm: allocating space after the two buffers for rx/tx data - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the uart parameters in the parameter ram. - */ - up->smc_rbase = dpaddr; - up->smc_tbase = dpaddr + sizeof (cbd_t); - up->smc_rfcr = SMC_EB; - up->smc_tfcr = SMC_EB; - -#if defined(CONFIG_MBX) - board_serial_init (); -#endif - - /* Set UART mode, 8 bit, no parity, one stop. - * Enable receive and transmit. - * Set local loopback mode. - */ - sp->smc_smcmr = smcr_mk_clen (9) | SMCMR_SM_UART | (ushort) 0x0004; - - /* Mask all interrupts and remove anything pending. - */ - sp->smc_smcm = 0; - sp->smc_smce = 0xff; - - /* Set up the baud rate generator. - */ - cp->cp_simode = 0x00000000; - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Single character receive. - */ - up->smc_mrblr = 1; - up->smc_maxidl = 0; - - /* Initialize Tx/Rx parameters. - */ - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[smc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - /* Enable transmitter/receiver. - */ - sp->smc_smcmr |= SMCMR_REN | SMCMR_TEN; -} - -static void smc_halt(int smc_index) -{ -} - -static void smc_putc (int smc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int smc_getc (int smc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile smc_uart_t *up; - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (smc_uart_t *) & cpmp->cp_dparam[proff_smc[smc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->smc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * SCC callbacks - */ - -static void scc_init (int scc_index) -{ - static int cpm_cr_ch[] = { - CPM_CR_CH_SCC1, - CPM_CR_CH_SCC2, - CPM_CR_CH_SCC3, - CPM_CR_CH_SCC4, - }; - - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile scc_t *sp; - volatile scc_uart_t *up; - volatile cbd_t *tbdf, *rbdf; - volatile cpm8xx_t *cp = &(im->im_cpm); - uint dpaddr; - - /* initialize pointers to SCC */ - - sp = (scc_t *) & (cp->cp_scc[scc_index]); - up = (scc_uart_t *) & cp->cp_dparam[proff_scc[scc_index]]; - - /* Disable transmitter/receiver. - */ - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT); - - - /* Allocate space for two buffer descriptors in the DP ram. - */ - -#ifdef CFG_ALLOC_DPRAM - dpaddr = dpram_alloc_align (sizeof (cbd_t) * 2 + 2, 8); -#else - dpaddr = CPM_POST_BASE; -#endif - - /* Enable SDMA. - */ - im->im_siu_conf.sc_sdcr = 0x0001; - - /* Set the physical address of the host memory buffers in - * the buffer descriptors. - */ - - rbdf = (cbd_t *) & cp->cp_dpmem[dpaddr]; - rbdf->cbd_bufaddr = (uint) (rbdf + 2); - rbdf->cbd_sc = 0; - tbdf = rbdf + 1; - tbdf->cbd_bufaddr = ((uint) (rbdf + 2)) + 1; - tbdf->cbd_sc = 0; - - /* Set up the baud rate generator. - */ - cp->cp_sicr &= ~(0x000000FF << (8 * scc_index)); - /* no |= needed, since BRG1 is 000 */ - - cp->cp_brgc1 = - (((gd->cpu_clk / 16 / gd->baudrate) - - 1) << 1) | CPM_BRG_EN; - - /* Set up the uart parameters in the parameter ram. - */ - up->scc_genscc.scc_rbase = dpaddr; - up->scc_genscc.scc_tbase = dpaddr + sizeof (cbd_t); - - /* Initialize Tx/Rx parameters. - */ - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - cp->cp_cpcr = - mk_cr_cmd (cpm_cr_ch[scc_index], CPM_CR_INIT_TRX) | CPM_CR_FLG; - - while (cp->cp_cpcr & CPM_CR_FLG) /* wait if cp is busy */ - ; - - up->scc_genscc.scc_rfcr = SCC_EB | 0x05; - up->scc_genscc.scc_tfcr = SCC_EB | 0x05; - - up->scc_genscc.scc_mrblr = 1; /* Single character receive */ - up->scc_maxidl = 0; /* disable max idle */ - up->scc_brkcr = 1; /* send one break character on stop TX */ - up->scc_parec = 0; - up->scc_frmec = 0; - up->scc_nosec = 0; - up->scc_brkec = 0; - up->scc_uaddr1 = 0; - up->scc_uaddr2 = 0; - up->scc_toseq = 0; - up->scc_char1 = 0x8000; - up->scc_char2 = 0x8000; - up->scc_char3 = 0x8000; - up->scc_char4 = 0x8000; - up->scc_char5 = 0x8000; - up->scc_char6 = 0x8000; - up->scc_char7 = 0x8000; - up->scc_char8 = 0x8000; - up->scc_rccm = 0xc0ff; - - /* Set low latency / small fifo. - */ - sp->scc_gsmrh = SCC_GSMRH_RFW; - - /* Set UART mode - */ - sp->scc_gsmrl &= ~0xF; - sp->scc_gsmrl |= SCC_GSMRL_MODE_UART; - - /* Set local loopback mode. - */ - sp->scc_gsmrl &= ~SCC_GSMRL_DIAG_LE; - sp->scc_gsmrl |= SCC_GSMRL_DIAG_LOOP; - - /* Set clock divider 16 on Tx and Rx - */ - sp->scc_gsmrl |= (SCC_GSMRL_TDCR_16 | SCC_GSMRL_RDCR_16); - - sp->scc_psmr |= SCU_PSMR_CL; - - /* Mask all interrupts and remove anything pending. - */ - sp->scc_sccm = 0; - sp->scc_scce = 0xffff; - sp->scc_dsr = 0x7e7e; - sp->scc_psmr = 0x3000; - - /* Make the first buffer the only buffer. - */ - tbdf->cbd_sc |= BD_SC_WRAP; - rbdf->cbd_sc |= BD_SC_EMPTY | BD_SC_WRAP; - - /* Enable transmitter/receiver. - */ - sp->scc_gsmrl |= (SCC_GSMRL_ENR | SCC_GSMRL_ENT); -} - -static void scc_halt(int scc_index) -{ - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile scc_t *sp = (scc_t *) & (cp->cp_scc[scc_index]); - - sp->scc_gsmrl &= ~(SCC_GSMRL_ENR | SCC_GSMRL_ENT | SCC_GSMRL_DIAG_LE); -} - -static void scc_putc (int scc_index, const char c) -{ - volatile cbd_t *tbdf; - volatile char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - tbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_tbase]; - - /* Wait for last character to go. - */ - - buf = (char *) tbdf->cbd_bufaddr; -#if 0 - __asm__ ("eieio"); - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif - - *buf = c; - tbdf->cbd_datlen = 1; - tbdf->cbd_sc |= BD_SC_READY; - __asm__ ("eieio"); -#if 1 - while (tbdf->cbd_sc & BD_SC_READY) - __asm__ ("eieio"); -#endif -} - -static int scc_getc (int scc_index) -{ - volatile cbd_t *rbdf; - volatile unsigned char *buf; - volatile scc_uart_t *up; - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cpmp = &(im->im_cpm); - unsigned char c; - int i; - - up = (scc_uart_t *) & cpmp->cp_dparam[proff_scc[scc_index]]; - - rbdf = (cbd_t *) & cpmp->cp_dpmem[up->scc_genscc.scc_rbase]; - - /* Wait for character to show up. - */ - buf = (unsigned char *) rbdf->cbd_bufaddr; -#if 0 - while (rbdf->cbd_sc & BD_SC_EMPTY); -#else - for (i = 100; i > 0; i--) { - if (!(rbdf->cbd_sc & BD_SC_EMPTY)) - break; - udelay (1000); - } - - if (i == 0) - return -1; -#endif - c = *buf; - rbdf->cbd_sc |= BD_SC_EMPTY; - - return (c); -} - - /* - * Test routines - */ - -static int test_ctlr (int ctlr, int index) -{ - int res = -1; - char test_str[] = "*** UART Test String ***\r\n"; - int i; - - ctlr_proc[ctlr].init (index); - - for (i = 0; i < sizeof (test_str) - 1; i++) { - ctlr_proc[ctlr].putc (index, test_str[i]); - if (ctlr_proc[ctlr].getc (index) != test_str[i]) - goto Done; - } - - res = 0; - -Done: - ctlr_proc[ctlr].halt (index); - - if (res != 0) { - post_log ("uart %s%d test failed\n", - ctlr_name[ctlr], index + 1); - } - - return res; -} - -int uart_post_test (int flags) -{ - int res = 0; - int i; - - ctlr_proc[CTLR_SMC].init = smc_init; - ctlr_proc[CTLR_SMC].halt = smc_halt; - ctlr_proc[CTLR_SMC].putc = smc_putc; - ctlr_proc[CTLR_SMC].getc = smc_getc; - - ctlr_proc[CTLR_SCC].init = scc_init; - ctlr_proc[CTLR_SCC].halt = scc_halt; - ctlr_proc[CTLR_SCC].putc = scc_putc; - ctlr_proc[CTLR_SCC].getc = scc_getc; - - for (i = 0; i < CTRL_LIST_SIZE; i++) { - if (test_ctlr (ctlr_list[i][0], ctlr_list[i][1]) != 0) { - res = -1; - } - } - -#if !defined(CONFIG_8xx_CONS_NONE) - serial_reinit_all (); -#endif - - return res; -} - -#endif /* CONFIG_POST & CFG_POST_UART */ - -#endif /* CONFIG_POST */ diff --git a/post/usb.c b/post/usb.c deleted file mode 100644 index 0c74cfa..0000000 --- a/post/usb.c +++ /dev/null @@ -1,269 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * USB test - * - * The USB controller is tested in the local loopback mode. - * It is configured so that endpoint 0 operates as host and endpoint 1 - * operates as function endpoint. After that an IN token transaction - * is performed. - * Refer to MPC850 User Manual, Section 32.11.1 USB Host Controller - * Initialization Example. - */ - -#ifdef CONFIG_POST - -#include <post.h> - -#if CONFIG_POST & CFG_POST_USB - -#include <commproc.h> -#include <command.h> - -#define TOUT_LOOP 100 - -#define PROFF_USB ((uint)0x0000) - -#define CPM_USB_EP0_BASE 0x0a00 -#define CPM_USB_EP1_BASE 0x0a20 - -#define CPM_USB_DT0_BASE 0x0a80 -#define CPM_USB_DT1_BASE 0x0a90 -#define CPM_USB_DR0_BASE 0x0aa0 -#define CPM_USB_DR1_BASE 0x0ab0 - -#define CPM_USB_RX0_BASE 0x0b00 -#define CPM_USB_RX1_BASE 0x0b08 -#define CPM_USB_TX0_BASE 0x0b20 -#define CPM_USB_TX1_BASE 0x0b28 - -#define USB_EXPECT(x) if (!(x)) goto Done; - -typedef struct usb_param { - ushort ep0ptr; - ushort ep1ptr; - ushort ep2ptr; - ushort ep3ptr; - uint rstate; - uint rptr; - ushort frame_n; - ushort rbcnt; - ushort rtemp; -} usb_param_t; - -typedef struct usb_param_block { - ushort rbase; - ushort tbase; - uchar rfcr; - uchar tfcr; - ushort mrblr; - ushort rbptr; - ushort tbptr; - uint tstate; - uint tptr; - ushort tcrc; - ushort tbcnt; - uint res[2]; -} usb_param_block_t; - -typedef struct usb { - uchar usmod; - uchar usadr; - uchar uscom; - uchar res1; - ushort usep[4]; - uchar res2[4]; - ushort usber; - uchar res3[2]; - ushort usbmr; - uchar res4; - uchar usbs; - uchar res5[8]; -} usb_t; - -int usb_post_test (int flags) -{ - int res = -1; - volatile immap_t *im = (immap_t *) CFG_IMMR; - volatile cpm8xx_t *cp = &(im->im_cpm); - volatile usb_param_t *pram_ptr; - uint dpram; - ushort DPRAM; - volatile cbd_t *tx; - volatile cbd_t *rx; - volatile usb_t *usbr; - volatile usb_param_block_t *ep0; - volatile usb_param_block_t *ep1; - int j; - - pram_ptr = (usb_param_t *) & (im->im_cpm.cp_dparam[PROFF_USB]); - dpram = (uint) im->im_cpm.cp_dpmem; - DPRAM = dpram; - tx = (cbd_t *) (dpram + CPM_USB_TX0_BASE); - rx = (cbd_t *) (dpram + CPM_USB_RX0_BASE); - ep0 = (usb_param_block_t *) (dpram + CPM_USB_EP0_BASE); - ep1 = (usb_param_block_t *) (dpram + CPM_USB_EP1_BASE); - usbr = (usb_t *) & (im->im_cpm.cp_scc[0]); - - /* 01 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0200; - im->im_ioport.iop_papar |= (ushort) 0x0200; - - cp->cp_sicr &= ~0x000000FF; - cp->cp_sicr |= 0x00000018; - - cp->cp_brgc4 = 0x00010001; - - /* 02 */ - im->im_ioport.iop_padir &= ~(ushort) 0x0002; - im->im_ioport.iop_padir &= ~(ushort) 0x0001; - - im->im_ioport.iop_papar |= (ushort) 0x0002; - im->im_ioport.iop_papar |= (ushort) 0x0001; - - /* 03 */ - im->im_ioport.iop_pcdir &= ~(ushort) 0x0020; - im->im_ioport.iop_pcdir &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcpar &= ~(ushort) 0x0020; - im->im_ioport.iop_pcpar &= ~(ushort) 0x0010; - - im->im_ioport.iop_pcso |= (ushort) 0x0020; - im->im_ioport.iop_pcso |= (ushort) 0x0010; - - /* 04 */ - im->im_ioport.iop_pcdir |= (ushort) 0x0200; - im->im_ioport.iop_pcdir |= (ushort) 0x0100; - - im->im_ioport.iop_pcpar |= (ushort) 0x0200; - im->im_ioport.iop_pcpar |= (ushort) 0x0100; - - /* 05 */ - pram_ptr->frame_n = 0; - - /* 06 */ - pram_ptr->ep0ptr = DPRAM + CPM_USB_EP0_BASE; - pram_ptr->ep1ptr = DPRAM + CPM_USB_EP1_BASE; - - /* 07-10 */ - tx[0].cbd_sc = 0xB800; - tx[0].cbd_datlen = 3; - tx[0].cbd_bufaddr = dpram + CPM_USB_DT0_BASE; - - tx[1].cbd_sc = 0xBC80; - tx[1].cbd_datlen = 3; - tx[1].cbd_bufaddr = dpram + CPM_USB_DT1_BASE; - - rx[0].cbd_sc = 0xA000; - rx[0].cbd_datlen = 0; - rx[0].cbd_bufaddr = dpram + CPM_USB_DR0_BASE; - - rx[1].cbd_sc = 0xA000; - rx[1].cbd_datlen = 0; - rx[1].cbd_bufaddr = dpram + CPM_USB_DR1_BASE; - - /* 11-12 */ - *(volatile int *) (dpram + CPM_USB_DT0_BASE) = 0x69856000; - *(volatile int *) (dpram + CPM_USB_DT1_BASE) = 0xABCD1234; - - *(volatile int *) (dpram + CPM_USB_DR0_BASE) = 0; - *(volatile int *) (dpram + CPM_USB_DR1_BASE) = 0; - - /* 13-16 */ - ep0->rbase = DPRAM + CPM_USB_RX0_BASE; - ep0->tbase = DPRAM + CPM_USB_TX0_BASE; - ep0->rfcr = 0x18; - ep0->tfcr = 0x18; - ep0->mrblr = 0x100; - ep0->rbptr = DPRAM + CPM_USB_RX0_BASE; - ep0->tbptr = DPRAM + CPM_USB_TX0_BASE; - ep0->tstate = 0; - - /* 17-20 */ - ep1->rbase = DPRAM + CPM_USB_RX1_BASE; - ep1->tbase = DPRAM + CPM_USB_TX1_BASE; - ep1->rfcr = 0x18; - ep1->tfcr = 0x18; - ep1->mrblr = 0x100; - ep1->rbptr = DPRAM + CPM_USB_RX1_BASE; - ep1->tbptr = DPRAM + CPM_USB_TX1_BASE; - ep1->tstate = 0; - - /* 21-24 */ - usbr->usep[0] = 0x0000; - usbr->usep[1] = 0x1100; - usbr->usep[2] = 0x2200; - usbr->usep[3] = 0x3300; - - /* 25 */ - usbr->usmod = 0x06; - - /* 26 */ - usbr->usadr = 0x05; - - /* 27 */ - usbr->uscom = 0; - - /* 28 */ - usbr->usmod |= 0x01; - udelay (1); - - /* 29-30 */ - usbr->uscom = 0x80; - usbr->uscom = 0x81; - - /* Wait for the data packet to be transmitted */ - for (j = 0; j < TOUT_LOOP; j++) { - if (tx[1].cbd_sc & (ushort) 0x8000) - udelay (1); - else - break; - } - - USB_EXPECT (j < TOUT_LOOP); - - USB_EXPECT (tx[0].cbd_sc == 0x3800); - USB_EXPECT (tx[0].cbd_datlen == 3); - - USB_EXPECT (tx[1].cbd_sc == 0x3C80); - USB_EXPECT (tx[1].cbd_datlen == 3); - - USB_EXPECT (rx[0].cbd_sc == 0x2C00); - USB_EXPECT (rx[0].cbd_datlen == 5); - - USB_EXPECT (*(volatile int *) (dpram + CPM_USB_DR0_BASE) == - 0xABCD122B); - USB_EXPECT (*(volatile char *) (dpram + CPM_USB_DR0_BASE + 4) == 0x42); - - res = 0; - Done: - - return res; -} - -#endif /* CONFIG_POST & CFG_POST_USB */ - -#endif /* CONFIG_POST */ diff --git a/post/watchdog.c b/post/watchdog.c deleted file mode 100644 index 48c4282..0000000 --- a/post/watchdog.c +++ /dev/null @@ -1,78 +0,0 @@ -/* - * (C) Copyright 2002 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -/* - * Watchdog test - * - * The test verifies the watchdog timer operation. - * On the first iteration, the test routine disables interrupts and - * makes a 10-second delay. If the system does not reboot during this delay, - * the watchdog timer is not operational and the test fails. If the system - * reboots, on the second iteration the test routine reports a success. - */ - -#ifdef CONFIG_POST - -#include <post.h> -#include <watchdog.h> - -#if CONFIG_POST & CFG_POST_WATCHDOG - -static ulong gettbl (void) -{ - ulong r; - - asm ("mftbl %0":"=r" (r)); - - return r; -} - -int watchdog_post_test (int flags) -{ - if (flags & POST_REBOOT) { - /* Test passed */ - - return 0; - } else { - /* 10-second delay */ - int ints = disable_interrupts (); - ulong base = gettbl (); - ulong clk = get_tbclk (); - - while ((gettbl () - base) / 10 < clk); - - if (ints) - enable_interrupts (); - - /* - * If we have reached this point, the watchdog timer - * does not work - */ - return -1; - } -} - -#endif /* CONFIG_POST & CFG_POST_WATCHDOG */ -#endif /* CONFIG_POST */ |