diff options
| -rw-r--r-- | drivers/usb/host/ehci-fsl.c | 20 | ||||
| -rw-r--r-- | include/usb/ehci-fsl.h | 7 |
2 files changed, 27 insertions, 0 deletions
diff --git a/drivers/usb/host/ehci-fsl.c b/drivers/usb/host/ehci-fsl.c index 1d012db..6cb4d98 100644 --- a/drivers/usb/host/ehci-fsl.c +++ b/drivers/usb/host/ehci-fsl.c @@ -18,6 +18,8 @@ #include "ehci.h" +static void set_txfifothresh(struct usb_ehci *, u32); + /* Check USB PHY clock valid */ static int usb_phy_clk_valid(struct usb_ehci *ehci) { @@ -123,6 +125,10 @@ int ehci_hcd_init(int index, enum usb_init_type init, in_le32(&ehci->usbmode); + if (SVR_SOC_VER(get_svr()) == SVR_T4240 && + IS_SVR_REV(get_svr(), 2, 0)) + set_txfifothresh(ehci, TXFIFOTHRESH); + return 0; } @@ -134,3 +140,17 @@ int ehci_hcd_stop(int index) { return 0; } + +/* + * Setting the value of TXFIFO_THRESH field in TXFILLTUNING register + * to counter DDR latencies in writing data into Tx buffer. + * This prevents Tx buffer from getting underrun + */ +static void set_txfifothresh(struct usb_ehci *ehci, u32 txfifo_thresh) +{ + u32 cmd; + cmd = ehci_readl(&ehci->txfilltuning); + cmd &= ~TXFIFO_THRESH_MASK; + cmd |= TXFIFO_THRESH(txfifo_thresh); + ehci_writel(&ehci->txfilltuning, cmd); +} diff --git a/include/usb/ehci-fsl.h b/include/usb/ehci-fsl.h index 734305b..c9ee1d5 100644 --- a/include/usb/ehci-fsl.h +++ b/include/usb/ehci-fsl.h @@ -164,6 +164,13 @@ #endif /* + * Increasing TX FIFO threshold value from 2 to 4 decreases + * data burst rate with which data packets are posted from the TX + * latency FIFO to compensate for latencies in DDR pipeline during DMA + */ +#define TXFIFOTHRESH 4 + +/* * USB Registers */ struct usb_ehci { |