diff options
95 files changed, 1730 insertions, 1172 deletions
diff --git a/arch/arm/cpu/arm926ejs/mxs/Makefile b/arch/arm/cpu/arm926ejs/mxs/Makefile index 13b5a54..152546e 100644 --- a/arch/arm/cpu/arm926ejs/mxs/Makefile +++ b/arch/arm/cpu/arm926ejs/mxs/Makefile @@ -14,11 +14,11 @@ obj-y += spl_boot.o spl_lradc_init.o spl_mem_init.o spl_power_init.o endif # Specify the target for use in elftosb call -ELFTOSB_TARGET-$(CONFIG_MX23) = imx23 -ELFTOSB_TARGET-$(CONFIG_MX28) = imx28 +MKIMAGE_TARGET-$(CONFIG_MX23) = mx23 +MKIMAGE_TARGET-$(CONFIG_MX28) = mx28 -$(OBJTREE)/u-boot.bd: $(SRCTREE)/$(CPUDIR)/$(SOC)/u-boot-$(ELFTOSB_TARGET-y).bd +$(OBJTREE)/mxsimage.cfg: $(SRCTREE)/$(CPUDIR)/$(SOC)/mxsimage.$(MKIMAGE_TARGET-y).cfg sed "s@OBJTREE@$(OBJTREE)@g" $^ > $@ -$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/u-boot.bd - elftosb -zf $(ELFTOSB_TARGET-y) -c $(OBJTREE)/u-boot.bd -o $(OBJTREE)/u-boot.sb +$(OBJTREE)/u-boot.sb: $(OBJTREE)/u-boot.bin $(OBJTREE)/spl/u-boot-spl.bin $(OBJTREE)/mxsimage.cfg + $(OBJTREE)/tools/mkimage -n $(OBJTREE)/mxsimage.cfg -T mxsimage $@ diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg index 8118767..c9cf4b3 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx23.cfg @@ -1,6 +1,6 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin CALL 0x14 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin CALL 0x40000100 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg index ea772f0..676f5c8 100644 --- a/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg +++ b/arch/arm/cpu/arm926ejs/mxs/mxsimage.mx28.cfg @@ -1,8 +1,8 @@ SECTION 0x0 BOOTABLE TAG LAST - LOAD 0x0 spl/u-boot-spl.bin + LOAD 0x0 OBJTREE/spl/u-boot-spl.bin LOAD IVT 0x8000 0x14 CALL HAB 0x8000 0x0 - LOAD 0x40000100 u-boot.bin + LOAD 0x40000100 OBJTREE/u-boot.bin LOAD IVT 0x8000 0x40000100 CALL HAB 0x8000 0x0 diff --git a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c index 8ea45be..d25019a 100644 --- a/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c +++ b/arch/arm/cpu/arm926ejs/mxs/spl_power_init.c @@ -654,6 +654,8 @@ static void mxs_batt_boot(void) clrsetbits_le32(&power_regs->hw_power_5vctrl, POWER_5VCTRL_CHARGE_4P2_ILIMIT_MASK, 0x8 << POWER_5VCTRL_CHARGE_4P2_ILIMIT_OFFSET); + + mxs_power_enable_4p2(); } /** diff --git a/arch/arm/cpu/arm926ejs/mxs/start.S b/arch/arm/cpu/arm926ejs/mxs/start.S index 3e454ae..5de2bad 100644 --- a/arch/arm/cpu/arm926ejs/mxs/start.S +++ b/arch/arm/cpu/arm926ejs/mxs/start.S @@ -150,6 +150,15 @@ IRQ_STACK_START_IN: _reset: /* + * If the CPU is configured in "Wait JTAG connection mode", the stack + * pointer is not configured and is zero. This will cause crash when + * trying to push data onto stack right below here. Load the SP and make + * it point to the end of OCRAM if the SP is zero. + */ + cmp sp, #0x00000000 + ldreq sp, =CONFIG_SYS_INIT_SP_ADDR + + /* * Store all registers on old stack pointer, this will allow us later to * return to the BootROM and let the BootROM load U-Boot into RAM. * diff --git a/arch/arm/cpu/armv7/am33xx/board.c b/arch/arm/cpu/armv7/am33xx/board.c index a31bf40..453effa 100644 --- a/arch/arm/cpu/armv7/am33xx/board.c +++ b/arch/arm/cpu/armv7/am33xx/board.c @@ -32,6 +32,7 @@ #include <linux/usb/gadget.h> #include <linux/usb/musb.h> #include <asm/omap_musb.h> +#include <asm/davinci_rtc.h> DECLARE_GLOBAL_DATA_PTR; @@ -150,15 +151,15 @@ __weak void am33xx_spl_board_init(void) static void rtc32k_enable(void) { - struct rtc_regs *rtc = (struct rtc_regs *)RTC_BASE; + struct davinci_rtc *rtc = (struct davinci_rtc *)RTC_BASE; /* * Unlock the RTC's registers. For more details please see the * RTC_SS section of the TRM. In order to unlock we need to * write these specific values (keys) in this order. */ - writel(0x83e70b13, &rtc->kick0r); - writel(0x95a4f1e0, &rtc->kick1r); + writel(RTC_KICK0R_WE, &rtc->kick0r); + writel(RTC_KICK1R_WE, &rtc->kick1r); /* Enable the RTC 32K OSC by setting bits 3 and 6. */ writel((1 << 3) | (1 << 6), &rtc->osc); diff --git a/arch/arm/cpu/armv7/mx5/lowlevel_init.S b/arch/arm/cpu/armv7/mx5/lowlevel_init.S index 25fadf6..f5bc672 100644 --- a/arch/arm/cpu/armv7/mx5/lowlevel_init.S +++ b/arch/arm/cpu/armv7/mx5/lowlevel_init.S @@ -45,6 +45,12 @@ #endif mcr 15, 1, r0, c9, c0, 2 + + /* enable L2 cache */ + mrc 15, 0, r0, c1, c0, 1 + orr r0, r0, #2 + mcr 15, 0, r0, c1, c0, 1 + .endm /* init_l2cc */ /* AIPS setup - Only setup MPROTx registers. @@ -369,12 +375,6 @@ setup_pll_func: #endif /* CONFIG_MX53 */ .endm -.macro setup_wdog - ldr r0, =WDOG1_BASE_ADDR - mov r1, #0x30 - strh r1, [r0] -.endm - ENTRY(lowlevel_init) mov r10, lr mov r4, #0 /* Fix R4 to 0 */ diff --git a/arch/arm/cpu/armv7/mx6/clock.c b/arch/arm/cpu/armv7/mx6/clock.c index cf3a38e..873d9d0 100644 --- a/arch/arm/cpu/armv7/mx6/clock.c +++ b/arch/arm/cpu/armv7/mx6/clock.c @@ -100,6 +100,32 @@ static u32 decode_pll(enum pll_clocks pll, u32 infreq) } /* NOTREACHED */ } +static u32 mxc_get_pll_pfd(enum pll_clocks pll, int pfd_num) +{ + u32 div; + u64 freq; + + switch (pll) { + case PLL_BUS: + if (pfd_num == 3) { + /* No PFD3 on PPL2 */ + return 0; + } + div = __raw_readl(&imx_ccm->analog_pfd_528); + freq = (u64)decode_pll(PLL_BUS, MXC_HCLK); + break; + case PLL_USBOTG: + div = __raw_readl(&imx_ccm->analog_pfd_480); + freq = (u64)decode_pll(PLL_USBOTG, MXC_HCLK); + break; + default: + /* No PFD on other PLL */ + return 0; + } + + return (freq * 18) / ((div & ANATOP_PFD_FRAC_MASK(pfd_num)) >> + ANATOP_PFD_FRAC_SHIFT(pfd_num)); +} static u32 get_mcu_main_clk(void) { @@ -144,13 +170,14 @@ u32 get_periph_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; break; default: break; @@ -184,7 +211,7 @@ static u32 get_ipg_per_clk(void) static u32 get_uart_clk(void) { u32 reg, uart_podf; - u32 freq = PLL3_80M; + u32 freq = decode_pll(PLL_USBOTG, MXC_HCLK) / 6; /* static divider */ reg = __raw_readl(&imx_ccm->cscdr1); #ifdef CONFIG_MX6SL if (reg & MXC_CCM_CSCDR1_UART_CLK_SEL) @@ -204,7 +231,7 @@ static u32 get_cspi_clk(void) reg &= MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK; cspi_podf = reg >> MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET; - return PLL3_60M / (cspi_podf + 1); + return decode_pll(PLL_USBOTG, MXC_HCLK) / (8 * (cspi_podf + 1)); } static u32 get_axi_clk(void) @@ -217,9 +244,9 @@ static u32 get_axi_clk(void) if (cbcdr & MXC_CCM_CBCDR_AXI_SEL) { if (cbcdr & MXC_CCM_CBCDR_AXI_ALT_SEL) - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); else - root_freq = PLL3_PFD1_FREQ; + root_freq = mxc_get_pll_pfd(PLL_USBOTG, 1); } else root_freq = get_periph_clk(); @@ -244,10 +271,10 @@ static u32 get_emi_slow_clk(void) root_freq = decode_pll(PLL_USBOTG, MXC_HCLK); break; case 2: - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 3: - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); break; } @@ -270,13 +297,14 @@ static u32 get_mmdc_ch0_clk(void) freq = decode_pll(PLL_BUS, MXC_HCLK); break; case 1: - freq = PLL2_PFD2_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 2); break; case 2: - freq = PLL2_PFD0_FREQ; + freq = mxc_get_pll_pfd(PLL_BUS, 0); break; case 3: - freq = PLL2_PFD2_DIV_FREQ; + /* static / 2 divider */ + freq = mxc_get_pll_pfd(PLL_BUS, 2) / 2; } return freq / (podf + 1); @@ -359,9 +387,9 @@ static u32 get_usdhc_clk(u32 port) } if (clk_sel) - root_freq = PLL2_PFD0_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 0); else - root_freq = PLL2_PFD2_FREQ; + root_freq = mxc_get_pll_pfd(PLL_BUS, 2); return root_freq / (usdhc_podf + 1); } diff --git a/arch/arm/cpu/armv7/omap-common/boot-common.c b/arch/arm/cpu/armv7/omap-common/boot-common.c index 0ffa03a..69fff32 100644 --- a/arch/arm/cpu/armv7/omap-common/boot-common.c +++ b/arch/arm/cpu/armv7/omap-common/boot-common.c @@ -14,6 +14,7 @@ #include <asm/arch/omap.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/sys_proto.h> +#include <watchdog.h> DECLARE_GLOBAL_DATA_PTR; @@ -76,6 +77,9 @@ void spl_board_init(void) #if defined(CONFIG_AM33XX) && defined(CONFIG_SPL_MUSB_NEW_SUPPORT) arch_misc_init(); #endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif #ifdef CONFIG_AM33XX am33xx_spl_board_init(); #endif diff --git a/arch/arm/cpu/armv7/zynq/cpu.c b/arch/arm/cpu/armv7/zynq/cpu.c index 4914986..2bb3843 100644 --- a/arch/arm/cpu/armv7/zynq/cpu.c +++ b/arch/arm/cpu/armv7/zynq/cpu.c @@ -11,6 +11,10 @@ void lowlevel_init(void) { +} + +int arch_cpu_init(void) +{ zynq_slcr_unlock(); /* remap DDR to zero, FILTERSTART */ writel(0, &scu_base->filter_start); @@ -31,6 +35,8 @@ void lowlevel_init(void) writel(0xC, &slcr_base->ddr_urgent); zynq_slcr_lock(); + + return 0; } void reset_cpu(ulong addr) diff --git a/arch/arm/include/asm/arch-am33xx/cpu.h b/arch/arm/include/asm/arch-am33xx/cpu.h index 52fa128..05752ce 100644 --- a/arch/arm/include/asm/arch-am33xx/cpu.h +++ b/arch/arm/include/asm/arch-am33xx/cpu.h @@ -457,15 +457,6 @@ struct gptimer { unsigned int tcar2; /* offset 0x58 */ }; -/* RTC Registers */ -struct rtc_regs { - unsigned int res[21]; - unsigned int osc; /* offset 0x54 */ - unsigned int res2[5]; - unsigned int kick0r; /* offset 0x6c */ - unsigned int kick1r; /* offset 0x70 */ -}; - /* UART Registers */ struct uart_sys { unsigned int resv1[21]; diff --git a/arch/arm/include/asm/arch-at91/at91_pmc.h b/arch/arm/include/asm/arch-at91/at91_pmc.h index 003920c..7b36f74 100644 --- a/arch/arm/include/asm/arch-at91/at91_pmc.h +++ b/arch/arm/include/asm/arch-at91/at91_pmc.h @@ -233,6 +233,8 @@ typedef struct at91_pmc { #endif #define AT91_PMC_USBS_USB_PLLA (0x0) /* USB Clock Input is PLLA */ #define AT91_PMC_USBS_USB_UPLL (0x1) /* USB Clock Input is UPLL */ +#define AT91_PMC_USBS_USB_PLLB (0x1) /* USB Clock Input is PLLB, AT91SAM9N12 only */ +#define AT91_PMC_USB_DIV_2 (0x1 << 8) /* USB Clock divided by 2 */ #define AT91_PMC_USBDIV_8 (0x7 << 8) /* USB Clock divided by 8 */ #define AT91_PMC_USBDIV_10 (0x9 << 8) /* USB Clock divided by 10 */ diff --git a/arch/arm/include/asm/arch-at91/at91_rstc.h b/arch/arm/include/asm/arch-at91/at91_rstc.h index 423cf51..a942342 100644 --- a/arch/arm/include/asm/arch-at91/at91_rstc.h +++ b/arch/arm/include/asm/arch-at91/at91_rstc.h @@ -38,4 +38,11 @@ typedef struct at91_rstc { #define AT91_RSTC_SR_NRSTL 0x00010000 +#define AT91_RSTC_RSTTYP (7 << 8) /* Reset Type */ +#define AT91_RSTC_RSTTYP_GENERAL (0 << 8) +#define AT91_RSTC_RSTTYP_WAKEUP (1 << 8) +#define AT91_RSTC_RSTTYP_WATCHDOG (2 << 8) +#define AT91_RSTC_RSTTYP_SOFTWARE (3 << 8) +#define AT91_RSTC_RSTTYP_USER (4 << 8) + #endif diff --git a/arch/arm/include/asm/arch-davinci/hardware.h b/arch/arm/include/asm/arch-davinci/hardware.h index 05ecc78..7aaf4bf 100644 --- a/arch/arm/include/asm/arch-davinci/hardware.h +++ b/arch/arm/include/asm/arch-davinci/hardware.h @@ -613,42 +613,4 @@ static inline enum davinci_clk_ids get_async3_src(void) #endif -struct davinci_rtc { - dv_reg second; - dv_reg minutes; - dv_reg hours; - dv_reg day; - dv_reg month; /* 0x10 */ - dv_reg year; - dv_reg dotw; - dv_reg resv1; - dv_reg alarmsecond; /* 0x20 */ - dv_reg alarmminute; - dv_reg alarmhour; - dv_reg alarmday; - dv_reg alarmmonth; /* 0x30 */ - dv_reg alarmyear; - dv_reg resv2[2]; - dv_reg ctrl; /* 0x40 */ - dv_reg status; - dv_reg irq; - dv_reg complsb; - dv_reg compmsb; /* 0x50 */ - dv_reg osc; - dv_reg resv3[2]; - dv_reg scratch0; /* 0x60 */ - dv_reg scratch1; - dv_reg scratch2; - dv_reg kick0r; - dv_reg kick1r; /* 0x70 */ -}; - -#define RTC_STATE_BUSY 0x01 -#define RTC_STATE_RUN 0x02 - -#define RTC_KICK0R_WE 0x83e70b13 -#define RTC_KICK1R_WE 0x95a4f1e0 - -#define davinci_rtc_base ((struct davinci_rtc *)DAVINCI_RTC_BASE) - #endif /* __ASM_ARCH_HARDWARE_H */ diff --git a/arch/arm/include/asm/arch-mx6/crm_regs.h b/arch/arm/include/asm/arch-mx6/crm_regs.h index 2813593..7202073 100644 --- a/arch/arm/include/asm/arch-mx6/crm_regs.h +++ b/arch/arm/include/asm/arch-mx6/crm_regs.h @@ -890,15 +890,4 @@ struct mxc_ccm_reg { #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \ (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC) -#define PLL2_PFD0_FREQ 352000000 -#define PLL2_PFD1_FREQ 594000000 -#define PLL2_PFD2_FREQ 396000000 -#define PLL2_PFD2_DIV_FREQ 200000000 -#define PLL3_PFD0_FREQ 720000000 -#define PLL3_PFD1_FREQ 540000000 -#define PLL3_PFD2_FREQ 508200000 -#define PLL3_PFD3_FREQ 454700000 -#define PLL3_80M 80000000 -#define PLL3_60M 60000000 - #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h index b5df68a..7373407 100644 --- a/arch/arm/include/asm/arch-mx6/mx6dl_pins.h +++ b/arch/arm/include/asm/arch-mx6/mx6dl_pins.h @@ -210,7 +210,7 @@ enum { MX6_PAD_DI0_PIN3__MMDC_MMDC_DEBUG_3 = IOMUX_PAD(0x03BC, 0x00A8, 6, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__PL301_SIM_MX6DL_PER1_HADDR_10 = IOMUX_PAD(0x03BC, 0x00A8, 7, 0x0000, 0, 0), MX6_PAD_DI0_PIN3__LCDIF_CS = IOMUX_PAD(0x03BC, 0x00A8, 8, 0x0000, 0, 0), - MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, PAD_CTL_DSE_120ohm), + MX6_PAD_DI0_PIN4__IPU1_DI0_PIN4 = IOMUX_PAD(0x03C0, 0x00AC, 0, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__LCDIF_BUSY = IOMUX_PAD(0x03C0, 0x00AC, 1, 0x08D8, 1, 0), MX6_PAD_DI0_PIN4__AUDMUX_AUD6_RXD = IOMUX_PAD(0x03C0, 0x00AC, 2, 0x0000, 0, 0), MX6_PAD_DI0_PIN4__USDHC1_WP = IOMUX_PAD(0x03C0, 0x00AC, 3, 0x092C, 0, 0), diff --git a/arch/arm/include/asm/arch-mxs/sys_proto.h b/arch/arm/include/asm/arch-mxs/sys_proto.h index 43c7dd6..09dfc90 100644 --- a/arch/arm/include/asm/arch-mxs/sys_proto.h +++ b/arch/arm/include/asm/arch-mxs/sys_proto.h @@ -46,6 +46,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x02, 0x1f, "SSP SPI #1, master, NOR" }, { 0x03, 0x1f, "SSP SPI #2, master, NOR" }, { 0x04, 0x1f, "NAND" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0" }, { 0x0a, 0x1f, "SSP SD/MMC #1" }, @@ -60,6 +61,7 @@ static const struct mxs_pair mxs_boot_modes[] = { { 0x13, 0x1f, "SSP SPI #3, master, 1V8 NOR" }, { 0x04, 0x1f, "NAND, 3V3" }, { 0x14, 0x1f, "NAND, 1V8" }, + { 0x06, 0x1f, "JTAG" }, { 0x08, 0x1f, "SSP SPI #3, master, 3V3 EEPROM" }, { 0x18, 0x1f, "SSP SPI #3, master, 1V8 EEPROM" }, { 0x09, 0x1f, "SSP SD/MMC #0, 3V3" }, diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 414d37a..3c2306f 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -145,9 +145,9 @@ struct s32ktimer { #define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 #define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x7C7C7C7C -#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64656465 +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL_ES2 0x64646464 #define DDR_IO_0_VREF_CELLS_DDR3_VALUE_ES2 0xBAE8C631 -#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xB46318D8 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE_ES2 0xBC6318DC #define DDR_IO_2_VREF_CELLS_DDR3_VALUE_ES2 0x84210000 #define EFUSE_1 0x45145100 diff --git a/arch/arm/include/asm/arch-omap5/spl.h b/arch/arm/include/asm/arch-omap5/spl.h index 57f0de5..2d5a62e 100644 --- a/arch/arm/include/asm/arch-omap5/spl.h +++ b/arch/arm/include/asm/arch-omap5/spl.h @@ -16,6 +16,7 @@ #define BOOT_DEVICE_MMC2 6 #define BOOT_DEVICE_MMC2_2 7 #define BOOT_DEVICE_SPI 10 +#define BOOT_DEVICE_UART 0x43 #define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC1 #define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC2_2 diff --git a/arch/arm/include/asm/davinci_rtc.h b/arch/arm/include/asm/davinci_rtc.h new file mode 100644 index 0000000..575b590 --- /dev/null +++ b/arch/arm/include/asm/davinci_rtc.h @@ -0,0 +1,52 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi@koi8.net> + * + * Based on: + * + * ------------------------------------------------------------------------- + * + * linux/include/asm-arm/arch-davinci/hardware.h + * + * Copyright (C) 2006 Texas Instruments. + * + * SPDX-License-Identifier: GPL-2.0 + */ +#ifndef __ASM_DAVINCI_RTC_H +#define __ASM_DAVINCI_RTC_H + +struct davinci_rtc { + unsigned int second; + unsigned int minutes; + unsigned int hours; + unsigned int day; + unsigned int month; /* 0x10 */ + unsigned int year; + unsigned int dotw; + unsigned int resv1; + unsigned int alarmsecond; /* 0x20 */ + unsigned int alarmminute; + unsigned int alarmhour; + unsigned int alarmday; + unsigned int alarmmonth; /* 0x30 */ + unsigned int alarmyear; + unsigned int resv2[2]; + unsigned int ctrl; /* 0x40 */ + unsigned int status; + unsigned int irq; + unsigned int complsb; + unsigned int compmsb; /* 0x50 */ + unsigned int osc; + unsigned int resv3[2]; + unsigned int scratch0; /* 0x60 */ + unsigned int scratch1; + unsigned int scratch2; + unsigned int kick0r; + unsigned int kick1r; /* 0x70 */ +}; + +#define RTC_STATE_BUSY 0x01 +#define RTC_STATE_RUN 0x02 + +#define RTC_KICK0R_WE 0x83e70b13 +#define RTC_KICK1R_WE 0x95a4f1e0 +#endif diff --git a/board/Barix/ipam390/ipam390-ais-uart.cfg b/board/Barix/ipam390/ipam390-ais-uart.cfg index e1a99f2..709cf23 100644 --- a/board/Barix/ipam390/ipam390-ais-uart.cfg +++ b/board/Barix/ipam390/ipam390-ais-uart.cfg @@ -109,7 +109,7 @@ CLK2XSRC = 0x00000000 ;NANDFCR = 0x00000000 [EMIF25ASYNC] A1CR = 0x00000000 -A2CR = 0x3FFFFFFE +A2CR = 0x04202110 A3CR = 0x00000000 A4CR = 0x00000000 NANDFCR = 0x00000012 diff --git a/board/Barix/ipam390/ipam390.c b/board/Barix/ipam390/ipam390.c index f3f276e..ae88b42 100644 --- a/board/Barix/ipam390/ipam390.c +++ b/board/Barix/ipam390/ipam390.c @@ -264,7 +264,7 @@ void show_boot_progress(int status) static int green; if (red == 0) - red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); + red = init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); if (red != CONFIG_IPAM390_GPIO_LED_RED) return; if (green == 0) @@ -277,10 +277,10 @@ void show_boot_progress(int status) case BOOTSTAGE_ID_RUN_OS: /* * set normal state - * LED Red : off + * LED Red : on * LED green: off */ - gpio_set_value(red, LED_OFF); + gpio_set_value(red, LED_ON); gpio_set_value(green, LED_OFF); break; case BOOTSTAGE_ID_MAIN_LOOP: @@ -326,23 +326,12 @@ int spl_start_uboot(void) if (!bootmode) if (ret == 0) bootmode = 1; - if (bootmode) { - /* - * Booting U-Boot - * LED Red : on - * LED green: off - */ - init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); - init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); - } else { - /* - * Booting Linux - * LED Red : off - * LED green: off - */ - init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_OFF); - init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); - } + /* + * LED red : on + * LED green: off + */ + init_led(CONFIG_IPAM390_GPIO_LED_RED, "red", LED_ON); + init_led(CONFIG_IPAM390_GPIO_LED_GREEN, "green", LED_OFF); return bootmode; } #endif diff --git a/board/atmel/at91sam9n12ek/at91sam9n12ek.c b/board/atmel/at91sam9n12ek/at91sam9n12ek.c index 2ec32eb..9adc992 100644 --- a/board/atmel/at91sam9n12ek/at91sam9n12ek.c +++ b/board/atmel/at91sam9n12ek/at91sam9n12ek.c @@ -199,6 +199,13 @@ void at91sam9n12ek_ks8851_hw_init(void) } #endif +#ifdef CONFIG_USB_ATMEL +void at91sam9n12ek_usb_hw_init(void) +{ + at91_set_pio_output(AT91_PIO_PORTB, 7, 0); +} +#endif + int board_early_init_f(void) { /* Enable clocks for all PIOs */ @@ -230,6 +237,10 @@ int board_init(void) at91sam9n12ek_ks8851_hw_init(); #endif +#ifdef CONFIG_USB_ATMEL + at91sam9n12ek_usb_hw_init(); +#endif + return 0; } diff --git a/board/boundary/nitrogen6x/6x_upgrade.txt b/board/boundary/nitrogen6x/6x_upgrade.txt index 1f9a889..1a62bbf 100644 --- a/board/boundary/nitrogen6x/6x_upgrade.txt +++ b/board/boundary/nitrogen6x/6x_upgrade.txt @@ -17,7 +17,7 @@ if ${fs}load ${dtype} ${disk}:1 12000000 u-boot.imx || ${fs}load ${dtype} ${disk sleep 1 ; done echo "erasing" ; - sf erase 0 0x50000 ; + sf erase 0 0xC0000 ; # two steps to prevent bricking echo "programming" ; sf write 0x12000000 $offset $filesize ; diff --git a/board/compulab/cm_t35/Makefile b/board/compulab/cm_t35/Makefile index 66b264a..6e2e1cb 100644 --- a/board/compulab/cm_t35/Makefile +++ b/board/compulab/cm_t35/Makefile @@ -7,7 +7,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o -obj-$(CONFIG_LCD) += display.o - obj-y += cm_t35.o leds.o diff --git a/board/compulab/cm_t35/cm_t35.c b/board/compulab/cm_t35/cm_t35.c index 19945c1..b9a9965 100644 --- a/board/compulab/cm_t35/cm_t35.c +++ b/board/compulab/cm_t35/cm_t35.c @@ -33,7 +33,7 @@ #include <asm/ehci-omap.h> #include <asm/gpio.h> -#include "eeprom.h" +#include "../common/eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -160,7 +160,7 @@ static u32 cm_t3x_rev; u32 get_board_rev(void) { if (!cm_t3x_rev) - cm_t3x_rev = cm_t3x_eeprom_get_board_rev(); + cm_t3x_rev = cl_eeprom_get_board_rev(); return cm_t3x_rev; }; @@ -509,7 +509,7 @@ static int handle_mac_address(void) if (rc) return 0; - rc = cm_t3x_eeprom_read_mac_addr(enetaddr); + rc = cl_eeprom_read_mac_addr(enetaddr); if (rc) return rc; @@ -599,5 +599,4 @@ int ehci_hcd_stop(void) { return omap_ehci_hcd_stop(); } - #endif /* CONFIG_USB_EHCI_OMAP */ diff --git a/board/compulab/common/Makefile b/board/compulab/common/Makefile new file mode 100644 index 0000000..831be2e --- /dev/null +++ b/board/compulab/common/Makefile @@ -0,0 +1,10 @@ +# +# (C) Copyright 2011 - 2013 CompuLab, Ltd. <www.compulab.co.il> +# +# Author: Igor Grinberg <grinberg@compulab.co.il> +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-$(CONFIG_DRIVER_OMAP34XX_I2C) += eeprom.o +obj-$(CONFIG_LCD) += omap3_display.o diff --git a/board/compulab/cm_t35/eeprom.c b/board/compulab/common/eeprom.c index df91acd..5aa3dbd 100644 --- a/board/compulab/cm_t35/eeprom.c +++ b/board/compulab/common/eeprom.c @@ -22,30 +22,30 @@ #define LAYOUT_INVALID 0 #define LAYOUT_LEGACY 0xff -static int eeprom_layout; /* Implicitly LAYOUT_INVALID */ +static int cl_eeprom_layout; /* Implicitly LAYOUT_INVALID */ -static int cm_t3x_eeprom_read(uint offset, uchar *buf, int len) +static int cl_eeprom_read(uint offset, uchar *buf, int len) { return i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, offset, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, buf, len); } -static int eeprom_setup_layout(void) +static int cl_eeprom_setup_layout(void) { int res; - if (eeprom_layout != LAYOUT_INVALID) + if (cl_eeprom_layout != LAYOUT_INVALID) return 0; - res = cm_t3x_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, - (uchar *)&eeprom_layout, 1); + res = cl_eeprom_read(EEPROM_LAYOUT_VER_OFFSET, + (uchar *)&cl_eeprom_layout, 1); if (res) { - eeprom_layout = LAYOUT_INVALID; + cl_eeprom_layout = LAYOUT_INVALID; return res; } - if (eeprom_layout == 0 || eeprom_layout >= 0x20) - eeprom_layout = LAYOUT_LEGACY; + if (cl_eeprom_layout == 0 || cl_eeprom_layout >= 0x20) + cl_eeprom_layout = LAYOUT_LEGACY; return 0; } @@ -56,12 +56,14 @@ void get_board_serial(struct tag_serialnr *serialnr) uint offset; memset(serialnr, 0, sizeof(*serialnr)); - if (eeprom_setup_layout()) + + if (cl_eeprom_setup_layout()) return; - offset = (eeprom_layout != LAYOUT_LEGACY) ? - BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; - if (cm_t3x_eeprom_read(offset, (uchar *)serial, 8)) + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? + BOARD_SERIAL_OFFSET : BOARD_SERIAL_OFFSET_LEGACY; + + if (cl_eeprom_read(offset, (uchar *)serial, 8)) return; if (serial[0] != 0xffffffff && serial[1] != 0xffffffff) { @@ -71,45 +73,46 @@ void get_board_serial(struct tag_serialnr *serialnr) } /* - * Routine: cm_t3x_eeprom_read_mac_addr + * Routine: cl_eeprom_read_mac_addr * Description: read mac address and store it in buf. */ -int cm_t3x_eeprom_read_mac_addr(uchar *buf) +int cl_eeprom_read_mac_addr(uchar *buf) { uint offset; - if (eeprom_setup_layout()) + if (cl_eeprom_setup_layout()) return 0; - offset = (eeprom_layout != LAYOUT_LEGACY) ? + offset = (cl_eeprom_layout != LAYOUT_LEGACY) ? MAC_ADDR_OFFSET : MAC_ADDR_OFFSET_LEGACY; - return cm_t3x_eeprom_read(offset, buf, 6); + + return cl_eeprom_read(offset, buf, 6); } /* - * Routine: cm_t3x_eeprom_get_board_rev + * Routine: cl_eeprom_get_board_rev * Description: read system revision from eeprom */ -u32 cm_t3x_eeprom_get_board_rev(void) +u32 cl_eeprom_get_board_rev(void) { u32 rev = 0; char str[5]; /* Legacy representation can contain at most 4 digits */ uint offset = BOARD_REV_OFFSET_LEGACY; - if (eeprom_setup_layout()) + if (cl_eeprom_setup_layout()) return 0; - if (eeprom_layout != LAYOUT_LEGACY) + if (cl_eeprom_layout != LAYOUT_LEGACY) offset = BOARD_REV_OFFSET; - if (cm_t3x_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) + if (cl_eeprom_read(offset, (uchar *)&rev, BOARD_REV_SIZE)) return 0; /* * Convert legacy syntactic representation to semantic * representation. i.e. for rev 1.00: 0x100 --> 0x64 */ - if (eeprom_layout == LAYOUT_LEGACY) { + if (cl_eeprom_layout == LAYOUT_LEGACY) { sprintf(str, "%x", rev); rev = simple_strtoul(str, NULL, 10); } diff --git a/board/compulab/cm_t35/eeprom.h b/board/compulab/common/eeprom.h index 02ffbb1..cf8c302 100644 --- a/board/compulab/cm_t35/eeprom.h +++ b/board/compulab/common/eeprom.h @@ -11,14 +11,14 @@ #define _EEPROM_ #ifdef CONFIG_DRIVER_OMAP34XX_I2C -int cm_t3x_eeprom_read_mac_addr(uchar *buf); -u32 cm_t3x_eeprom_get_board_rev(void); +int cl_eeprom_read_mac_addr(uchar *buf); +u32 cl_eeprom_get_board_rev(void); #else -static inline int cm_t3x_eeprom_read_mac_addr(uchar *buf) +static inline int cl_eeprom_read_mac_addr(uchar *buf) { return 1; } -static inline u32 cm_t3x_eeprom_get_board_rev(void) +static inline u32 cl_eeprom_get_board_rev(void) { return 0; } diff --git a/board/compulab/cm_t35/display.c b/board/compulab/common/omap3_display.c index fae8d95..ead821e 100644 --- a/board/compulab/cm_t35/display.c +++ b/board/compulab/common/omap3_display.c @@ -51,6 +51,7 @@ static const struct panel_config preset_dvi_640X480 = { .lcd_size = PANEL_LCD_SIZE(640, 480), .timing_h = DSS_HBP(48) | DSS_HFP(16) | DSS_HSW(96), .timing_v = DSS_VBP(33) | DSS_VFP(10) | DSS_VSW(2), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, .divisor = 12 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, @@ -62,6 +63,7 @@ static const struct panel_config preset_dvi_800X600 = { .lcd_size = PANEL_LCD_SIZE(800, 600), .timing_h = DSS_HBP(88) | DSS_HFP(40) | DSS_HSW(128), .timing_v = DSS_VBP(23) | DSS_VFP(1) | DSS_VSW(4), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, .divisor = 8 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, @@ -73,6 +75,7 @@ static const struct panel_config preset_dvi_1024X768 = { .lcd_size = PANEL_LCD_SIZE(1024, 768), .timing_h = DSS_HBP(160) | DSS_HFP(24) | DSS_HSW(136), .timing_v = DSS_VBP(29) | DSS_VFP(3) | DSS_VSW(6), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, .divisor = 5 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, @@ -84,7 +87,8 @@ static const struct panel_config preset_dvi_1152X864 = { .lcd_size = PANEL_LCD_SIZE(1152, 864), .timing_h = DSS_HBP(256) | DSS_HFP(64) | DSS_HSW(128), .timing_v = DSS_VBP(32) | DSS_VFP(1) | DSS_VSW(3), - .divisor = 3 | (1 << 16), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, + .divisor = 4 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, .load_mode = 2, @@ -95,6 +99,7 @@ static const struct panel_config preset_dvi_1280X960 = { .lcd_size = PANEL_LCD_SIZE(1280, 960), .timing_h = DSS_HBP(312) | DSS_HFP(96) | DSS_HSW(112), .timing_v = DSS_VBP(36) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, .divisor = 3 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, @@ -106,6 +111,7 @@ static const struct panel_config preset_dvi_1280X1024 = { .lcd_size = PANEL_LCD_SIZE(1280, 1024), .timing_h = DSS_HBP(248) | DSS_HFP(48) | DSS_HSW(112), .timing_v = DSS_VBP(38) | DSS_VFP(1) | DSS_VSW(3), + .pol_freq = DSS_IHS | DSS_IVS | DSS_IPC, .divisor = 3 | (1 << 16), .data_lines = LCD_INTERFACE_24_BIT, .panel_type = ACTIVE_DISPLAY, diff --git a/board/corscience/tricorder/Makefile b/board/corscience/tricorder/Makefile index d5316f8..266432d 100644 --- a/board/corscience/tricorder/Makefile +++ b/board/corscience/tricorder/Makefile @@ -8,4 +8,4 @@ # SPDX-License-Identifier: GPL-2.0+ # -obj-y := tricorder.o +obj-y := tricorder.o tricorder-eeprom.o led.o diff --git a/board/corscience/tricorder/led.c b/board/corscience/tricorder/led.c new file mode 100644 index 0000000..30f2f50 --- /dev/null +++ b/board/corscience/tricorder/led.c @@ -0,0 +1,80 @@ +/* + * Copyright (c) 2013 Corscience GmbH & Co.KG + * Andreas Bießmann <andreas.biessmann@corscience.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <status_led.h> +#include <twl4030.h> +#include <asm/arch/cpu.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> + +#define TRICORDER_STATUS_LED_YELLOW 42 +#define TRICORDER_STATUS_LED_GREEN 43 + +void __led_init(led_id_t mask, int state) +{ + __led_set(mask, state); +} + +void __led_toggle(led_id_t mask) +{ + int toggle_gpio = 0; +#ifdef STATUS_LED_BIT + if (!toggle_gpio && STATUS_LED_BIT & mask) + toggle_gpio = TRICORDER_STATUS_LED_GREEN; +#endif +#ifdef STATUS_LED_BIT1 + if (!toggle_gpio && STATUS_LED_BIT1 & mask) + toggle_gpio = TRICORDER_STATUS_LED_YELLOW; +#endif +#ifdef STATUS_LED_BIT2 + if (!toggle_gpio && STATUS_LED_BIT2 & mask) { + uint8_t val; + twl4030_i2c_read_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, + &val); + val ^= (TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDAPWM); + twl4030_i2c_write_u8(TWL4030_CHIP_LED, TWL4030_LED_LEDEN, + val); + } +#endif + if (toggle_gpio) { + int state; + gpio_request(toggle_gpio, ""); + state = gpio_get_value(toggle_gpio); + gpio_set_value(toggle_gpio, !state); + } +} + +void __led_set(led_id_t mask, int state) +{ +#ifdef STATUS_LED_BIT + if (STATUS_LED_BIT & mask) { + gpio_request(TRICORDER_STATUS_LED_GREEN, ""); + gpio_direction_output(TRICORDER_STATUS_LED_GREEN, 0); + gpio_set_value(TRICORDER_STATUS_LED_GREEN, state); + } +#endif +#ifdef STATUS_LED_BIT1 + if (STATUS_LED_BIT1 & mask) { + gpio_request(TRICORDER_STATUS_LED_YELLOW, ""); + gpio_direction_output(TRICORDER_STATUS_LED_YELLOW, 0); + gpio_set_value(TRICORDER_STATUS_LED_YELLOW, state); + } +#endif +#ifdef STATUS_LED_BIT2 + if (STATUS_LED_BIT2 & mask) { + if (STATUS_LED_OFF == state) + twl4030_i2c_write_u8(TWL4030_CHIP_LED, + TWL4030_LED_LEDEN, 0); + else + twl4030_i2c_write_u8(TWL4030_CHIP_LED, + TWL4030_LED_LEDEN, + (TWL4030_LED_LEDEN_LEDAON | + TWL4030_LED_LEDEN_LEDAPWM)); + } +#endif +} diff --git a/board/corscience/tricorder/tricorder-eeprom.c b/board/corscience/tricorder/tricorder-eeprom.c new file mode 100644 index 0000000..1c74a0f --- /dev/null +++ b/board/corscience/tricorder/tricorder-eeprom.c @@ -0,0 +1,251 @@ +/* + * (C) Copyright 2013 + * Corscience GmbH & Co. KG, <www.corscience.de> + * Andreas Bießmann <andreas.biessmann@corscience.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <common.h> +#include <i2c.h> + +#include "tricorder-eeprom.h" + +static inline void warn_wrong_value(const char *msg, unsigned int a, + unsigned int b) +{ + printf("Expected EEPROM %s %08x, got %08x\n", msg, a, b); +} + +static int handle_eeprom_v0(struct tricorder_eeprom *eeprom) +{ + struct tricorder_eeprom_v0 { + uint32_t magic; + uint16_t length; + uint16_t version; + char board_name[TRICORDER_BOARD_NAME_LENGTH]; + char board_version[TRICORDER_BOARD_VERSION_LENGTH]; + char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; + uint32_t crc32; + } __packed eepromv0; + uint32_t crc; + + printf("Old EEPROM (v0), consider rewrite!\n"); + + if (be16_to_cpu(eeprom->length) != sizeof(eepromv0)) { + warn_wrong_value("length", sizeof(eepromv0), + be16_to_cpu(eeprom->length)); + return 1; + } + + memcpy(&eepromv0, eeprom, sizeof(eepromv0)); + + crc = crc32(0L, (unsigned char *)&eepromv0, + sizeof(eepromv0) - sizeof(eepromv0.crc32)); + if (be32_to_cpu(eepromv0.crc32) != crc) { + warn_wrong_value("CRC", be32_to_cpu(eepromv0.crc32), + crc); + return 1; + } + + /* Ok the content is correct, do the conversion */ + memset(eeprom->interface_version, 0x0, + TRICORDER_INTERFACE_VERSION_LENGTH); + crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); + eeprom->crc32 = cpu_to_be32(crc); + + return 0; +} + +static int handle_eeprom_v1(struct tricorder_eeprom *eeprom) +{ + uint32_t crc; + + if (be16_to_cpu(eeprom->length) != TRICORDER_EEPROM_SIZE) { + warn_wrong_value("length", TRICORDER_EEPROM_SIZE, + be16_to_cpu(eeprom->length)); + return 1; + } + + crc = crc32(0L, (unsigned char *)eeprom, TRICORDER_EEPROM_CRC_SIZE); + if (be32_to_cpu(eeprom->crc32) != crc) { + warn_wrong_value("CRC", be32_to_cpu(eeprom->crc32), crc); + return 1; + } + + return 0; +} + +int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom) +{ +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); + + i2c_read(addr, 0, 2, (unsigned char *)eeprom, TRICORDER_EEPROM_SIZE); +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + + if (be32_to_cpu(eeprom->magic) != TRICORDER_EEPROM_MAGIC) { + warn_wrong_value("magic", TRICORDER_EEPROM_MAGIC, + be32_to_cpu(eeprom->magic)); + return 1; + } + + switch (be16_to_cpu(eeprom->version)) { + case 0: + return handle_eeprom_v0(eeprom); + case 1: + return handle_eeprom_v1(eeprom); + default: + warn_wrong_value("version", TRICORDER_EEPROM_VERSION, + be16_to_cpu(eeprom->version)); + return 1; + } +} + +#if !defined(CONFIG_SPL) +int tricorder_eeprom_read(unsigned devaddr) +{ + struct tricorder_eeprom eeprom; + int ret = tricorder_get_eeprom(devaddr, &eeprom); + + if (ret) + return ret; + + printf("Board type: %.*s\n", + sizeof(eeprom.board_name), eeprom.board_name); + printf("Board version: %.*s\n", + sizeof(eeprom.board_version), eeprom.board_version); + printf("Board serial: %.*s\n", + sizeof(eeprom.board_serial), eeprom.board_serial); + printf("Board interface version: %.*s\n", + sizeof(eeprom.interface_version), + eeprom.interface_version); + + return ret; +} + +int tricorder_eeprom_write(unsigned devaddr, const char *name, + const char *version, const char *serial, const char *interface) +{ + struct tricorder_eeprom eeprom, eeprom_verify; + size_t length; + uint32_t crc; + int ret; + unsigned char *p; + int i; +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + unsigned int bus; +#endif + + memset(eeprom, 0, TRICORDER_EEPROM_SIZE); + memset(eeprom_verify, 0, TRICORDER_EEPROM_SIZE); + + eeprom.magic = cpu_to_be32(TRICORDER_EEPROM_MAGIC); + eeprom.length = cpu_to_be16(TRICORDER_EEPROM_SIZE); + eeprom.version = cpu_to_be16(TRICORDER_EEPROM_VERSION); + + length = min(sizeof(eeprom.board_name), strlen(name)); + strncpy(eeprom.board_name, name, length); + + length = min(sizeof(eeprom.board_version), strlen(version)); + strncpy(eeprom.board_version, version, length); + + length = min(sizeof(eeprom.board_serial), strlen(serial)); + strncpy(eeprom.board_serial, serial, length); + + if (interface) { + length = min(sizeof(eeprom.interface_version), + strlen(interface)); + strncpy(eeprom.interface_version, interface, length); + } + + crc = crc32(0L, (unsigned char *)&eeprom, TRICORDER_EEPROM_CRC_SIZE); + eeprom.crc32 = cpu_to_be32(crc); + +#if defined(DEBUG) + puts("Tricorder EEPROM content:\n"); + print_buffer(0, &eeprom, 1, sizeof(eeprom), 16); +#endif + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + bus = i2c_get_bus_num(); + i2c_set_bus_num(CONFIG_SYS_EEPROM_BUS_NUM); +#endif + + /* do page write to the eeprom */ + for (i = 0, p = (unsigned char *)&eeprom; + i < sizeof(eeprom); + i += 32, p += 32) { + ret = i2c_write(devaddr, i, CONFIG_SYS_I2C_EEPROM_ADDR_LEN, + p, min(sizeof(eeprom) - i, 32)); + if (ret) + break; + udelay(5000); /* 5ms write cycle timing */ + } + + ret = i2c_read(devaddr, 0, 2, (unsigned char *)&eeprom_verify, + TRICORDER_EEPROM_SIZE); + + if (memcmp(&eeprom, &eeprom_verify, sizeof(eeprom)) != 0) { + printf("Tricorder: Could not verify EEPROM content!\n"); + ret = 1; + } + +#ifdef CONFIG_SYS_EEPROM_BUS_NUM + i2c_set_bus_num(bus); +#endif + return ret; +} + +int do_tricorder_eeprom(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + if (argc == 3) { + ulong dev_addr = simple_strtoul(argv[2], NULL, 16); + eeprom_init(); + if (strcmp(argv[1], "read") == 0) { + int rcode; + + rcode = tricorder_eeprom_read(dev_addr); + + return rcode; + } + } else if (argc == 6 || argc == 7) { + ulong dev_addr = simple_strtoul(argv[2], NULL, 16); + char *name = argv[3]; + char *version = argv[4]; + char *serial = argv[5]; + char *interface = NULL; + eeprom_init(); + + if (argc == 7) + interface = argv[6]; + + if (strcmp(argv[1], "write") == 0) { + int rcode; + + rcode = tricorder_eeprom_write(dev_addr, name, version, + serial, interface); + + return rcode; + } + } + + return CMD_RET_USAGE; +} + +U_BOOT_CMD( + tricordereeprom, 7, 1, do_tricorder_eeprom, + "Tricorder EEPROM", + "read devaddr\n" + " - read Tricorder EEPROM at devaddr and print content\n" + "tricordereeprom write devaddr name version serial [interface]\n" + " - write Tricorder EEPROM at devaddr with 'name', 'version'" + "and 'serial'\n" + " optional add an HW interface parameter" +); +#endif /* CONFIG_SPL */ diff --git a/board/corscience/tricorder/tricorder-eeprom.h b/board/corscience/tricorder/tricorder-eeprom.h new file mode 100644 index 0000000..06ed9a5 --- /dev/null +++ b/board/corscience/tricorder/tricorder-eeprom.h @@ -0,0 +1,41 @@ +/* + * (C) Copyright 2013 + * Corscience GmbH & Co. KG, <www.corscience.de> + * Andreas Bießmann <andreas.biessmann@corscience.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef TRICORDER_EEPROM_H_ +#define TRICORDER_EEPROM_H_ + +#include <linux/compiler.h> + +#define TRICORDER_EEPROM_MAGIC 0xc2a94f52 +#define TRICORDER_EEPROM_VERSION 1 + +#define TRICORDER_BOARD_NAME_LENGTH 12 +#define TRICORDER_BOARD_VERSION_LENGTH 4 +#define TRICORDER_BOARD_SERIAL_LENGTH 12 +#define TRICORDER_INTERFACE_VERSION_LENGTH 4 + +struct tricorder_eeprom { + uint32_t magic; + uint16_t length; + uint16_t version; + char board_name[TRICORDER_BOARD_NAME_LENGTH]; + char board_version[TRICORDER_BOARD_VERSION_LENGTH]; + char board_serial[TRICORDER_BOARD_SERIAL_LENGTH]; + char interface_version[TRICORDER_INTERFACE_VERSION_LENGTH]; + uint32_t crc32; +} __packed; + +#define TRICORDER_EEPROM_SIZE sizeof(struct tricorder_eeprom) +#define TRICORDER_EEPROM_CRC_SIZE (TRICORDER_EEPROM_SIZE - \ + sizeof(uint32_t)) + +/** + * @brief read eeprom information from a specific eeprom address + */ +int tricorder_get_eeprom(int addr, struct tricorder_eeprom *eeprom); + +#endif /* TRICORDER_EEPROM_H_ */ diff --git a/board/corscience/tricorder/tricorder.c b/board/corscience/tricorder/tricorder.c index c7099e5..2dfcb27 100644 --- a/board/corscience/tricorder/tricorder.c +++ b/board/corscience/tricorder/tricorder.c @@ -13,11 +13,13 @@ #include <common.h> #include <twl4030.h> #include <asm/io.h> +#include <asm/gpio.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> #include <asm/arch/sys_proto.h> #include <asm/arch/mem.h> #include "tricorder.h" +#include "tricorder-eeprom.h" DECLARE_GLOBAL_DATA_PTR; @@ -34,16 +36,91 @@ int board_init(void) return 0; } +/** + * get_eeprom - read the eeprom + * + * @eeprom - pointer to a eeprom struct to fill + * + * This function will panic() on wrong EEPROM content + */ +static void get_eeprom(struct tricorder_eeprom *eeprom) +{ + int ret; + + if (!eeprom) + panic("No eeprom given!\n"); + + ret = gpio_request(7, "BMS"); + if (ret) + panic("gpio: requesting BMS pin failed\n"); + + ret = gpio_direction_input(7); + if (ret) + panic("gpio: set BMS as input failed\n"); + + ret = gpio_get_value(7); + if (ret < 0) + panic("gpio: get BMS pin state failed\n"); + + gpio_free(7); + + if (ret == 0) { + /* BMS is _not_ set, do the EEPROM check */ + ret = tricorder_get_eeprom(0x51, eeprom); + if (!ret) { + if (strncmp(eeprom->board_name, "CS10411", 7) != 0) + panic("Wrong board name '%.*s'\n", + sizeof(eeprom->board_name), + eeprom->board_name); + if (eeprom->board_version[0] < 'D') + panic("Wrong board version '%.*s'\n", + sizeof(eeprom->board_version), + eeprom->board_version); + } else { + panic("Could not get board revision\n"); + } + } +} + +/** + * print_hwversion - print out a HW version string + * + * @eeprom - pointer to the eeprom + */ +static void print_hwversion(struct tricorder_eeprom *eeprom) +{ + size_t len; + if (!eeprom) + panic("No eeprom given!"); + + printf("Board %.*s:%.*s serial %.*s", + sizeof(eeprom->board_name), eeprom->board_name, + sizeof(eeprom->board_version), eeprom->board_version, + sizeof(eeprom->board_serial), eeprom->board_serial); + + len = strnlen(eeprom->interface_version, + sizeof(eeprom->interface_version)); + if (len > 0) + printf(" HW interface version %.*s", + sizeof(eeprom->interface_version), + eeprom->interface_version); + puts("\n"); +} + /* * Routine: misc_init_r * Description: Configure board specific parts */ int misc_init_r(void) { + struct tricorder_eeprom eeprom; + get_eeprom(&eeprom); + print_hwversion(&eeprom); + twl4030_power_init(); -#ifdef CONFIG_TWL4030_LED - twl4030_led_init(TWL4030_LED_LEDEN_LEDAON | TWL4030_LED_LEDEN_LEDBON); -#endif + status_led_set(0, STATUS_LED_ON); + status_led_set(1, STATUS_LED_ON); + status_led_set(2, STATUS_LED_ON); dieid_num_r(); @@ -77,12 +154,43 @@ int board_mmc_init(bd_t *bis) */ void get_board_mem_timings(struct board_sdrc_timings *timings) { + struct tricorder_eeprom eeprom; + get_eeprom(&eeprom); + /* General SDRC config */ - timings->mcfg = MICRON_V_MCFG_165(128 << 20); - timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + if (eeprom.board_version[0] > 'D') { + /* use optimized timings for our SDRAM device */ + timings->mcfg = MCFG((256 << 20), 14); +#define MT46H64M32_TDAL 6 /* Twr/Tck + Trp/tck */ + /* 15/6 + 18/6 = 5.5 -> 6 */ +#define MT46H64M32_TDPL 3 /* 15/6 = 2.5 -> 3 (Twr) */ +#define MT46H64M32_TRRD 2 /* 12/6 = 2 */ +#define MT46H64M32_TRCD 3 /* 18/6 = 3 */ +#define MT46H64M32_TRP 3 /* 18/6 = 3 */ +#define MT46H64M32_TRAS 7 /* 42/6 = 7 */ +#define MT46H64M32_TRC 10 /* 60/6 = 10 */ +#define MT46H64M32_TRFC 12 /* 72/6 = 12 */ + timings->ctrla = ACTIM_CTRLA(MT46H64M32_TRFC, MT46H64M32_TRC, + MT46H64M32_TRAS, MT46H64M32_TRP, + MT46H64M32_TRCD, MT46H64M32_TRRD, + MT46H64M32_TDPL, + MT46H64M32_TDAL); + +#define MT46H64M32_TWTR 1 +#define MT46H64M32_TCKE 1 +#define MT46H64M32_XSR 19 /* 112.5/6 = 18.75 => ~19 */ +#define MT46H64M32_TXP 1 + timings->ctrlb = ACTIM_CTRLB(MT46H64M32_TWTR, MT46H64M32_TCKE, + MT46H64M32_TXP, MT46H64M32_XSR); - /* AC timings */ - timings->ctrla = MICRON_V_ACTIMA_165; - timings->ctrlb = MICRON_V_ACTIMB_165; - timings->mr = MICRON_V_MR_165; + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } else { + /* use conservative beagleboard timings as default */ + timings->mcfg = MICRON_V_MCFG_165(128 << 20); + timings->ctrla = MICRON_V_ACTIMA_165; + timings->ctrlb = MICRON_V_ACTIMB_165; + timings->mr = MICRON_V_MR_165; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } } diff --git a/board/corscience/tricorder/tricorder.h b/board/corscience/tricorder/tricorder.h index 820a50c..67c35c5 100644 --- a/board/corscience/tricorder/tricorder.h +++ b/board/corscience/tricorder/tricorder.h @@ -75,8 +75,8 @@ const omap3_sysinfo sysinfo = { MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ - MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ - MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTU | EN | M4)) /*GPIO 42*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTU | EN | M4)) /*GPIO 43*/\ MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ diff --git a/board/enbw/enbw_cmc/enbw_cmc.c b/board/enbw/enbw_cmc/enbw_cmc.c index c477962..39efe20 100644 --- a/board/enbw/enbw_cmc/enbw_cmc.c +++ b/board/enbw/enbw_cmc/enbw_cmc.c @@ -36,6 +36,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/sdmmc_defs.h> #include <asm/arch/timer_defs.h> +#include <asm/davinci_rtc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/prodrive/pdnb3/Makefile b/board/ppcag/bg0900/Makefile index 06120f3..74c6db5 100644 --- a/board/prodrive/pdnb3/Makefile +++ b/board/ppcag/bg0900/Makefile @@ -1,8 +1,12 @@ # -# (C) Copyright 2006 +# (C) Copyright 2000-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # # SPDX-License-Identifier: GPL-2.0+ # -obj-y := flash.o pdnb3.o nand.o +ifndef CONFIG_SPL_BUILD +obj-y := bg0900.o +else +obj-y := spl_boot.o +endif diff --git a/board/ppcag/bg0900/bg0900.c b/board/ppcag/bg0900/bg0900.c new file mode 100644 index 0000000..06612fa --- /dev/null +++ b/board/ppcag/bg0900/bg0900.c @@ -0,0 +1,86 @@ +/* + * PPC-AG BG0900 board + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/clock.h> +#include <asm/arch/sys_proto.h> +#include <linux/mii.h> +#include <miiphy.h> +#include <netdev.h> +#include <errno.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Functions + */ +int board_early_init_f(void) +{ + /* IO0 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK0, 480000); + /* IO1 clock at 480MHz */ + mxs_set_ioclk(MXC_IOCLK1, 480000); + + /* SSP2 clock at 160MHz */ + mxs_set_sspclk(MXC_SSPCLK2, 160000, 0); + + return 0; +} + +int dram_init(void) +{ + return mxs_dram_init(); +} + +int board_init(void) +{ + /* Adress of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +#ifdef CONFIG_CMD_NET +int board_eth_init(bd_t *bis) +{ + struct mxs_clkctrl_regs *clkctrl_regs = + (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE; + struct eth_device *dev; + int ret; + + ret = cpu_eth_init(bis); + + /* BG0900 uses ENET_CLK PAD to drive FEC clock */ + writel(CLKCTRL_ENET_TIME_SEL_RMII_CLK | CLKCTRL_ENET_CLK_OUT_EN, + &clkctrl_regs->hw_clkctrl_enet); + + /* Reset FEC PHYs */ + gpio_direction_output(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 0); + udelay(200); + gpio_set_value(MX28_PAD_ENET0_RX_CLK__GPIO_4_13, 1); + + ret = fecmxc_initialize_multi(bis, 0, 0, MXS_ENET0_BASE); + if (ret) { + puts("FEC MXS: Unable to init FEC0\n"); + return ret; + } + + dev = eth_get_dev_by_name("FEC0"); + if (!dev) { + puts("FEC MXS: Unable to get FEC0 device entry\n"); + return -EINVAL; + } + + return ret; +} + +#endif diff --git a/board/ppcag/bg0900/spl_boot.c b/board/ppcag/bg0900/spl_boot.c new file mode 100644 index 0000000..a04c955 --- /dev/null +++ b/board/ppcag/bg0900/spl_boot.c @@ -0,0 +1,153 @@ +/* + * PPC-AG BG0900 Boot setup + * + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <config.h> +#include <asm/io.h> +#include <asm/arch/iomux-mx28.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/sys_proto.h> + +#define MUX_CONFIG_GPMI (MXS_PAD_3V3 | MXS_PAD_4MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_ENET (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) +#define MUX_CONFIG_EMI (MXS_PAD_3V3 | MXS_PAD_12MA | MXS_PAD_NOPULL) +#define MUX_CONFIG_SSP2 (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP) + +const iomux_cfg_t iomux_setup[] = { + /* DUART */ + MX28_PAD_PWM0__DUART_RX, + MX28_PAD_PWM1__DUART_TX, + + /* GPMI NAND */ + MX28_PAD_GPMI_D00__GPMI_D0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D01__GPMI_D1 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D02__GPMI_D2 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D03__GPMI_D3 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D04__GPMI_D4 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D05__GPMI_D5 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D06__GPMI_D6 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_D07__GPMI_D7 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CE0N__GPMI_CE0N | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDY0__GPMI_READY0 | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RDN__GPMI_RDN | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), + MX28_PAD_GPMI_WRN__GPMI_WRN | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_ALE__GPMI_ALE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_CLE__GPMI_CLE | MUX_CONFIG_GPMI, + MX28_PAD_GPMI_RESETN__GPMI_RESETN | MUX_CONFIG_GPMI, + + /* FEC0 */ + MX28_PAD_ENET0_MDC__ENET0_MDC | MUX_CONFIG_ENET, + MX28_PAD_ENET0_MDIO__ENET0_MDIO | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RX_EN__ENET0_RX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TX_EN__ENET0_TX_EN | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD0__ENET0_RXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_RXD1__ENET0_RXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD0__ENET0_TXD0 | MUX_CONFIG_ENET, + MX28_PAD_ENET0_TXD1__ENET0_TXD1 | MUX_CONFIG_ENET, + MX28_PAD_ENET_CLK__CLKCTRL_ENET | MUX_CONFIG_ENET, + + /* FEC0 Reset */ + MX28_PAD_ENET0_RX_CLK__GPIO_4_13 | + (MXS_PAD_12MA | MXS_PAD_3V3 | MXS_PAD_PULLUP), + + /* EMI */ + MX28_PAD_EMI_D00__EMI_DATA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D01__EMI_DATA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D02__EMI_DATA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D03__EMI_DATA3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D04__EMI_DATA4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D05__EMI_DATA5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D06__EMI_DATA6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D07__EMI_DATA7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D08__EMI_DATA8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D09__EMI_DATA9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D10__EMI_DATA10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D11__EMI_DATA11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D12__EMI_DATA12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D13__EMI_DATA13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D14__EMI_DATA14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_D15__EMI_DATA15 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT0__EMI_ODT0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM0__EMI_DQM0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_ODT1__EMI_ODT1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQM1__EMI_DQM1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN_FB__EMI_DDR_OPEN_FEEDBACK | MUX_CONFIG_EMI, + MX28_PAD_EMI_CLK__EMI_CLK | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS0__EMI_DQS0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DQS1__EMI_DQS1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_DDR_OPEN__EMI_DDR_OPEN | MUX_CONFIG_EMI, + + MX28_PAD_EMI_A00__EMI_ADDR0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A01__EMI_ADDR1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A02__EMI_ADDR2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A03__EMI_ADDR3 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A04__EMI_ADDR4 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A05__EMI_ADDR5 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A06__EMI_ADDR6 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A07__EMI_ADDR7 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A08__EMI_ADDR8 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A09__EMI_ADDR9 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A10__EMI_ADDR10 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A11__EMI_ADDR11 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A12__EMI_ADDR12 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A13__EMI_ADDR13 | MUX_CONFIG_EMI, + MX28_PAD_EMI_A14__EMI_ADDR14 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA0__EMI_BA0 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA1__EMI_BA1 | MUX_CONFIG_EMI, + MX28_PAD_EMI_BA2__EMI_BA2 | MUX_CONFIG_EMI, + MX28_PAD_EMI_CASN__EMI_CASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_RASN__EMI_RASN | MUX_CONFIG_EMI, + MX28_PAD_EMI_WEN__EMI_WEN | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE0N__EMI_CE0N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CE1N__EMI_CE1N | MUX_CONFIG_EMI, + MX28_PAD_EMI_CKE__EMI_CKE | MUX_CONFIG_EMI, + + /* SPI2 (for SPI flash) */ + MX28_PAD_SSP2_SCK__SSP2_SCK | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MOSI__SSP2_CMD | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_MISO__SSP2_D0 | MUX_CONFIG_SSP2, + MX28_PAD_SSP2_SS0__SSP2_D3 | + (MXS_PAD_3V3 | MXS_PAD_8MA | MXS_PAD_PULLUP), +}; + +void mxs_adjust_memory_params(uint32_t *dram_vals) +{ + /* + * DDR Controller Registers + * Manufacturer: Winbond + * Device Part Number: W972GG6JB-25I + * Clock Freq.: 200MHz + * Density: 2Gb + * Chip Selects: 1 + * Number of Banks: 8 + * Row address: 14 + * Column address: 10 + */ + + dram_vals[0x74 / 4] = 0x0102010A; + dram_vals[0x98 / 4] = 0x04005003; + dram_vals[0x9c / 4] = 0x090000c8; + + dram_vals[0xa8 / 4] = 0x0036b009; + dram_vals[0xac / 4] = 0x03270612; + + dram_vals[0xb0 / 4] = 0x02020202; + dram_vals[0xb4 / 4] = 0x00c80029; + + dram_vals[0xc0 / 4] = 0x00011900; + + dram_vals[0x12c / 4] = 0x07400300; + dram_vals[0x130 / 4] = 0x07400300; + dram_vals[0x2c4 / 4] = 0x02030303; +} + +void board_init_ll(const uint32_t arg, const uint32_t *resptr) +{ + mxs_common_spl_init(arg, resptr, iomux_setup, ARRAY_SIZE(iomux_setup)); +} diff --git a/board/prodrive/pdnb3/flash.c b/board/prodrive/pdnb3/flash.c deleted file mode 100644 index 75b5d05..0000000 --- a/board/prodrive/pdnb3/flash.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <asm/arch/ixp425.h> - -#if !defined(CONFIG_FLASH_CFI_DRIVER) - -/* - * include common flash code (for esd boards) - */ -#include "../common/flash.c" - -/* - * Prototypes - */ -static ulong flash_get_size (vu_long * addr, flash_info_t * info); - -static inline ulong ld(ulong x) -{ - ulong k = 0; - - while (x >>= 1) - ++k; - - return k; -} - -unsigned long flash_init(void) -{ - unsigned long size; - int i; - - /* Init: no FLASHes known */ - for (i=0; i<CONFIG_SYS_MAX_FLASH_BANKS; i++) - flash_info[i].flash_id = FLASH_UNKNOWN; - - size = flash_get_size((vu_long *)FLASH_BASE0_PRELIM, &flash_info[0]); - - if (flash_info[0].flash_id == FLASH_UNKNOWN) - printf ("## Unknown FLASH on Bank 0 - Size = 0x%08lx = %ld MB\n", - size, size<<20); - - /* Reconfigure CS0 to actual FLASH size */ - *IXP425_EXP_CS0 = (*IXP425_EXP_CS0 & ~0x00003C00) | ((ld(size) - 9) << 10); - - /* Monitor protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_SYS_MONITOR_BASE, CONFIG_SYS_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect(FLAG_PROTECT_SET, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1, - &flash_info[CONFIG_SYS_MAX_FLASH_BANKS - 1]); - - flash_info[0].size = size; - - return size; -} - -#endif /* CONFIG_FLASH_CFI_DRIVER */ diff --git a/board/prodrive/pdnb3/nand.c b/board/prodrive/pdnb3/nand.c deleted file mode 100644 index e1d2c63..0000000 --- a/board/prodrive/pdnb3/nand.c +++ /dev/null @@ -1,129 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> - -#if defined(CONFIG_CMD_NAND) - -#include <nand.h> - -struct pdnb3_ndfc_regs { - uchar cmd; - uchar wait; - uchar addr; - uchar term; - uchar data; -}; - -static u8 hwctl; -static struct pdnb3_ndfc_regs *pdnb3_ndfc; - -#define readb(addr) *(volatile u_char *)(addr) -#define readl(addr) *(volatile u_long *)(addr) -#define writeb(d,addr) *(volatile u_char *)(addr) = (d) - -/* - * The PDNB3 has a NAND Flash Controller (NDFC) that handles all accesses to - * the NAND devices. The NDFC has command, address and data registers that - * when accessed will set up the NAND flash pins appropriately. We'll use the - * hwcontrol function to save the configuration in a global variable. - * We can then use this information in the read and write functions to - * determine which NDFC register to access. - * - * There is one NAND devices on the board, a Hynix HY27US08561A (32 MByte). - */ -static void pdnb3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) -{ - struct nand_chip *this = mtd->priv; - - if (ctrl & NAND_CTRL_CHANGE) { - if ( ctrl & NAND_CLE ) - hwctl |= 0x1; - else - hwctl &= ~0x1; - if ( ctrl & NAND_ALE ) - hwctl |= 0x2; - else - hwctl &= ~0x2; - if ( (ctrl & NAND_NCE) != NAND_NCE) - writeb(0x00, &(pdnb3_ndfc->term)); - } - if (cmd != NAND_CMD_NONE) - writeb(cmd, this->IO_ADDR_W); -} - - -static u_char pdnb3_nand_read_byte(struct mtd_info *mtd) -{ - return readb(&(pdnb3_ndfc->data)); -} - -static void pdnb3_nand_write_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) { - if (hwctl & 0x1) - writeb(buf[i], &(pdnb3_ndfc->cmd)); - else if (hwctl & 0x2) - writeb(buf[i], &(pdnb3_ndfc->addr)); - else - writeb(buf[i], &(pdnb3_ndfc->data)); - } -} - -static void pdnb3_nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - buf[i] = readb(&(pdnb3_ndfc->data)); -} - -static int pdnb3_nand_verify_buf(struct mtd_info *mtd, const u_char *buf, int len) -{ - int i; - - for (i = 0; i < len; i++) - if (buf[i] != readb(&(pdnb3_ndfc->data))) - return i; - - return 0; -} - -static int pdnb3_nand_dev_ready(struct mtd_info *mtd) -{ - /* - * Blocking read to wait for NAND to be ready - */ - readb(&(pdnb3_ndfc->wait)); - - /* - * Return always true - */ - return 1; -} - -int board_nand_init(struct nand_chip *nand) -{ - pdnb3_ndfc = (struct pdnb3_ndfc_regs *)CONFIG_SYS_NAND_BASE; - - nand->ecc.mode = NAND_ECC_SOFT; - - /* Set address of NAND IO lines (Using Linear Data Access Region) */ - nand->IO_ADDR_R = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); - nand->IO_ADDR_W = (void __iomem *) ((ulong) pdnb3_ndfc + 0x4); - /* Reference hardware control function */ - nand->cmd_ctrl = pdnb3_nand_hwcontrol; - nand->read_byte = pdnb3_nand_read_byte; - nand->write_buf = pdnb3_nand_write_buf; - nand->read_buf = pdnb3_nand_read_buf; - nand->verify_buf = pdnb3_nand_verify_buf; - nand->dev_ready = pdnb3_nand_dev_ready; - return 0; -} -#endif diff --git a/board/prodrive/pdnb3/pdnb3.c b/board/prodrive/pdnb3/pdnb3.c deleted file mode 100644 index fa320da..0000000 --- a/board/prodrive/pdnb3/pdnb3.c +++ /dev/null @@ -1,220 +0,0 @@ -/* - * (C) Copyright 2006 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <command.h> -#include <malloc.h> -#include <asm/arch/ixp425.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* predefine these here for FPGA programming (before including fpga.c) */ -#define SET_FPGA(data) *IXP425_GPIO_GPOUTR = (data) -#define FPGA_DONE_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_DONE) -#define FPGA_INIT_STATE (*IXP425_GPIO_GPINR & CONFIG_SYS_FPGA_INIT) -#define OLD_VAL old_val - -static unsigned long old_val = 0; - -/* - * include common fpga code (for prodrive boards) - */ -#include "../common/fpga.c" - -/* - * Miscelaneous platform dependent initialisations - */ -int board_init(void) -{ - /* adress of boot parameters */ - gd->bd->bi_boot_params = 0x00000100; - - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_FPGA_RESET); - - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_SYS_RUNNING); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_SYS_RUNNING); - - /* - * Setup GPIO's for FPGA programming - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_DATA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_INIT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_DONE); - - /* - * Setup GPIO's for interrupts - */ - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTA); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_PCI_INTB); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_PCI_INTB); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTORE_INT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTORE_INT); - GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_RESTART_INT); - GPIO_INT_ACT_LOW_SET(CONFIG_SYS_GPIO_RESTART_INT); - - /* - * Setup GPIO's for 33MHz clock output - */ - *IXP425_GPIO_GPCLKR = 0x01FF0000; - GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_CLK_33M); - - /* - * Setup other chip select's - */ - *IXP425_EXP_CS1 = CONFIG_SYS_EXP_CS1; - - return 0; -} - -/* - * Check Board Identity - */ -int checkboard(void) -{ - char buf[64]; - int i = getenv_f("serial#", buf, sizeof(buf)); - - puts("Board: PDNB3"); - - if (i > 0) { - puts(", serial# "); - puts(buf); - } - putc('\n'); - - return (0); -} - -int dram_init(void) -{ - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; - - return (0); -} - -int do_fpga_boot(unsigned char *fpgadata) -{ - unsigned char *dst; - int status; - int index; - int i; - ulong len = CONFIG_SYS_MALLOC_LEN; - - /* - * Setup GPIO's for FPGA programming - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_PRG); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_CLK); - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_DATA); - - /* - * Save value so no readback is required upon programming - */ - old_val = *IXP425_GPIO_GPOUTR; - - /* - * First try to decompress fpga image (gzip compressed?) - */ - dst = malloc(CONFIG_SYS_FPGA_MAX_SIZE); - if (gunzip(dst, CONFIG_SYS_FPGA_MAX_SIZE, (uchar *)fpgadata, &len) != 0) { - printf("Error: Image has to be gzipp'ed!\n"); - return -1; - } - - status = fpga_boot(dst, len); - if (status != 0) { - printf("\nFPGA: Booting failed "); - switch (status) { - case ERROR_FPGA_PRG_INIT_LOW: - printf("(Timeout: INIT not low after asserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_INIT_HIGH: - printf("(Timeout: INIT not high after deasserting PROGRAM*)\n "); - break; - case ERROR_FPGA_PRG_DONE: - printf("(Timeout: DONE not high after programming FPGA)\n "); - break; - } - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("FPGA: %s\n", &(dst[index+1])); - index += len+3; - } - putc ('\n'); - /* delayed reboot */ - for (i=5; i>0; i--) { - printf("Rebooting in %2d seconds \r",i); - for (index=0;index<1000;index++) - udelay(1000); - } - putc('\n'); - do_reset(NULL, 0, 0, NULL); - } - - puts("FPGA: "); - - /* display infos on fpgaimage */ - index = 15; - for (i=0; i<4; i++) { - len = dst[index]; - printf("%s ", &(dst[index+1])); - index += len+3; - } - putc('\n'); - - free(dst); - - /* - * Reset FPGA - */ - GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_FPGA_RESET); - udelay(10); - GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_FPGA_RESET); - - return (0); -} - -int do_fpga(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) -{ - ulong addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - addr = simple_strtoul(argv[1], NULL, 16); - - return do_fpga_boot((unsigned char *)addr); -} - -U_BOOT_CMD( - fpga, 2, 0, do_fpga, - "boot FPGA", - "address size\n - boot FPGA with gzipped image at <address>" -); - -#if defined(CONFIG_CMD_PCI) || defined(CONFIG_PCI) -extern struct pci_controller hose; -extern void pci_ixp_init(struct pci_controller * hose); - -void pci_init_board(void) -{ - extern void pci_ixp_init (struct pci_controller *hose); - - pci_ixp_init(&hose); -} -#endif diff --git a/board/ti/am335x/board.c b/board/ti/am335x/board.c index c2fc5a6..57fedab 100644 --- a/board/ti/am335x/board.c +++ b/board/ti/am335x/board.c @@ -28,6 +28,8 @@ #include <cpsw.h> #include <power/tps65217.h> #include <power/tps65910.h> +#include <environment.h> +#include <watchdog.h> #include "board.h" DECLARE_GLOBAL_DATA_PTR; @@ -485,6 +487,10 @@ int board_init(void) STNOR_GPMC_CONFIG5, STNOR_GPMC_CONFIG6, STNOR_GPMC_CONFIG7 }; #endif +#if defined(CONFIG_HW_WATCHDOG) + hw_watchdog_init(); +#endif + gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100; gpmc_init(); diff --git a/board/udoo/Makefile b/board/udoo/Makefile new file mode 100644 index 0000000..80efada --- /dev/null +++ b/board/udoo/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2013 Freescale Semiconductor, Inc. +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y := udoo.o diff --git a/board/udoo/udoo.c b/board/udoo/udoo.c new file mode 100644 index 0000000..e9d6375 --- /dev/null +++ b/board/udoo/udoo.c @@ -0,0 +1,110 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Author: Fabio Estevam <fabio.estevam@freescale.com> + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/clock.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/iomux.h> +#include <asm/arch/mx6-pins.h> +#include <asm/errno.h> +#include <asm/gpio.h> +#include <asm/imx-common/iomux-v3.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <asm/arch/crm_regs.h> +#include <asm/io.h> +#include <asm/arch/sys_proto.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ + PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ + PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ + PAD_CTL_SRE_FAST | PAD_CTL_HYS) + +#define WDT_EN IMX_GPIO_NR(5, 4) +#define WDT_TRG IMX_GPIO_NR(3, 19) + +int dram_init(void) +{ + gd->ram_size = (phys_size_t)CONFIG_DDR_MB * 1024 * 1024; + + return 0; +} + +static iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TXD | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RXD | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__USDHC3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__USDHC3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__USDHC3_DAT0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__USDHC3_DAT1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__USDHC3_DAT2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__USDHC3_DAT3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + +static iomux_v3_cfg_t const wdog_pads[] = { + MX6_PAD_EIM_A24__GPIO_5_4 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO_3_19, +}; + +static void setup_iomux_uart(void) +{ + imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); +} + +static void setup_iomux_wdog(void) +{ + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + gpio_direction_output(WDT_TRG, 0); + gpio_direction_output(WDT_EN, 1); +} + +static struct fsl_esdhc_cfg usdhc_cfg = { USDHC3_BASE_ADDR }; + +int board_mmc_getcd(struct mmc *mmc) +{ + return 1; /* Always present */ +} + +int board_mmc_init(bd_t *bis) +{ + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); + usdhc_cfg.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg.max_bus_width = 4; + + return fsl_esdhc_initialize(bis, &usdhc_cfg); +} + +int board_early_init_f(void) +{ + setup_iomux_wdog(); + setup_iomux_uart(); + + return 0; +} + +int board_init(void) +{ + /* address of boot parameters */ + gd->bd->bi_boot_params = PHYS_SDRAM + 0x100; + + return 0; +} + +int checkboard(void) +{ + puts("Board: Udoo\n"); + + return 0; +} diff --git a/board/wandboard/README b/board/wandboard/README index 498db2f..1f678e1 100644 --- a/board/wandboard/README +++ b/board/wandboard/README @@ -3,8 +3,8 @@ U-Boot for Wandboard This file contains information for the port of U-Boot to the Wandboard. -Wandboard is a development board that has two variants: one version based -on mx6 dual lite and another one based on mx6 solo. +Wandboard is a development board that has three variants based on the following +SoCs: mx6 quad, mx6 dual lite and mx6 solo. For more details about Wandboard, please refer to: http://www.wandboard.org/ @@ -207,6 +207,7 @@ Active arm arm926ejs mxs freescale mx28evk Active arm arm926ejs mxs freescale mx28evk mx28evk_auart_console mx28evk:MXS_AUART,MXS_AUART_BASE=MXS_UARTAPP3_BASE,ENV_IS_IN_MMC Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs freescale mx28evk mx28evk_nand mx28evk:ENV_IS_IN_NAND Fabio Estevam <fabio.estevam@freescale.com> Active arm arm926ejs mxs olimex mx23_olinuxino mx23_olinuxino mx23_olinuxino Marek Vasut <marek.vasut@gmail.com> +Active arm arm926ejs mxs ppcag bg0900 bg0900 bg0900 Marek Vasut <marex@denx.de> Active arm arm926ejs mxs sandisk sansa_fuze_plus sansa_fuze_plus - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs mxs schulercontrol sc_sps_1 sc_sps_1 - Marek Vasut <marek.vasut@gmail.com> Active arm arm926ejs nomadik st nhk8815 nhk8815 - Nomadik Linux Team <STN_WMM_nomadik_linux@list.st.com>:Alessandro Rubini <rubini@unipv.it> @@ -246,7 +247,7 @@ Active arm arm946es - armltd integrator Active arm armv7 - armltd vexpress vexpress_ca15_tc2 - - Active arm armv7 - armltd vexpress vexpress_ca5x2 - Matt Waddel <matt.waddel@linaro.org> Active arm armv7 - armltd vexpress vexpress_ca9x4 - Matt Waddel <matt.waddel@linaro.org> -Active arm armv7 am33xx isee igep0033 igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com> +Active arm armv7 am33xx isee igep0033 am335x_igep0033 - Enric Balletbo i Serra <eballetbo@iseebcn.com> Active arm armv7 am33xx phytec pcm051 pcm051 pcm051 Lars Poeschel <poeschel@lemonage.de> Active arm armv7 am33xx siemens dxr2 dxr2 - Roger Meier <r.meier@siemens.com> Active arm armv7 am33xx siemens pxm2 pxm2 - Roger Meier <r.meier@siemens.com> @@ -287,6 +288,7 @@ Active arm armv7 mx5 freescale mx53smd Active arm armv7 mx5 genesi mx51_efikamx mx51_efikamx mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg - Active arm armv7 mx5 genesi mx51_efikamx mx51_efikasb mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg - Active arm armv7 mx5 ttcontrol vision2 vision2 vision2:IMX_CONFIG=board/ttcontrol/vision2/imximage_hynix.cfg Stefano Babic <sbabic@denx.de> +Active arm armv7 mx6 - udoo udoo_quad udoo:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q.cfg,MX6Q,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_dl wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL,DDR_MB=1024 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_quad wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6q2g.cfg,MX6Q,DDR_MB=2048 Fabio Estevam <fabio.estevam@freescale.com> Active arm armv7 mx6 - wandboard wandboard_solo wandboard:IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6s.cfg,MX6S,DDR_MB=512 Fabio Estevam <fabio.estevam@freescale.com> @@ -310,12 +312,13 @@ Active arm armv7 omap3 8dtech eco5pk Active arm armv7 omap3 comelit dig297 dig297 - Luca Ceresoli <luca.ceresoli@comelit.it> Active arm armv7 omap3 compulab cm_t35 cm_t35 - Igor Grinberg <grinberg@compulab.co.il> Active arm armv7 omap3 corscience tricorder tricorder - Thomas Weber <weber@corscience.de> +Active arm armv7 omap3 corscience tricorder tricorder_flash tricorder:FLASHCARD Thomas Weber <weber@corscience.de> Active arm armv7 omap3 htkw mcx mcx - Ilya Yanok <yanok@emcraft.com> -Active arm armv7 omap3 isee igep00x0 igep0020 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> -Active arm armv7 omap3 isee igep00x0 igep0020_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - -Active arm armv7 omap3 isee igep00x0 igep0030 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> -Active arm armv7 omap3 isee igep00x0 igep0030_nand igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - -Active arm armv7 omap3 isee igep00x0 igep0032 igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> +Active arm armv7 omap3 isee igep00x0 igep0020 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> +Active arm armv7 omap3 isee igep00x0 igep0020_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0020,BOOT_NAND - +Active arm armv7 omap3 isee igep00x0 igep0030 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> +Active arm armv7 omap3 isee igep00x0 igep0030_nand omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0030,BOOT_NAND - +Active arm armv7 omap3 isee igep00x0 igep0032 omap3_igep00x0:MACH_TYPE=MACH_TYPE_IGEP0032,BOOT_ONENAND Enric Balletbo i Serra <eballetbo@iseebcn.com> Active arm armv7 omap3 logicpd am3517evm am3517_evm - Vaibhav Hiremath <hvaibhav@ti.com> Active arm armv7 omap3 logicpd omap3som omap3_logic - Peter Barada <peter.barada@logicpd.com> Active arm armv7 omap3 logicpd zoom1 omap3_zoom1 - Nishanth Menon <nm@ti.com> @@ -333,7 +336,8 @@ Active arm armv7 omap3 ti sdp3430 Active arm armv7 omap3 timll devkit8000 devkit8000 - Thomas Weber <weber@corscience.de> Active arm armv7 omap4 ti panda omap4_panda - Sricharan R <r.sricharan@ti.com> Active arm armv7 omap4 ti sdp4430 omap4_sdp4430 - Sricharan R <r.sricharan@ti.com> -Active arm armv7 omap5 ti dra7xx dra7xx_evm - Lokesh Vutla <lokeshvutla@ti.com> +Active arm armv7 omap5 ti dra7xx dra7xx_evm dra7xx_evm:CONS_INDEX=1 Lokesh Vutla <lokeshvutla@ti.com> +Active arm armv7 omap5 ti dra7xx dra7xx_evm_uart3 dra7xx_evm:CONS_INDEX=3,SPL_YMODEM_SUPPORT Lokesh Vutla <lokeshvutla@ti.com> Active arm armv7 omap5 ti omap5_uevm omap5_uevm - - Active arm armv7 rmobile atmark-techno armadillo-800eva armadillo-800eva - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> Active arm armv7 rmobile kmc kzm9g kzm9g - Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>:Tetsuyuki Kobayashi <koba@kmckk.co.jp> @@ -366,8 +370,6 @@ Active arm ixp - - actux1 Active arm ixp - - actux1 actux1_4_32 actux1:FLASH2X2,RAM_32MB Michael Schwingen <michael@schwingen.org> Active arm ixp - - actux1 actux1_8_16 actux1:FLASH1X8 Michael Schwingen <michael@schwingen.org> Active arm ixp - - actux1 actux1_8_32 actux1:FLASH1X8,RAM_32MB Michael Schwingen <michael@schwingen.org> -Active arm ixp - prodrive pdnb3 pdnb3 - Stefan Roese <sr@denx.de> -Active arm ixp - prodrive pdnb3 scpu pdnb3:SCPU Stefan Roese <sr@denx.de> Active arm pxa - - - balloon3 - Marek Vasut <marek.vasut@gmail.com> Active arm pxa - - - h2200 - Lukasz Dalek <luk0104@gmail.com> Active arm pxa - - - palmld - Marek Vasut <marek.vasut@gmail.com> diff --git a/doc/README.mxs b/doc/README.mxs index 2919bbf..0235a5a 100644 --- a/doc/README.mxs +++ b/doc/README.mxs @@ -27,9 +27,25 @@ Contents 1) Prerequisites ---------------- -To make a MXS based board bootable, some tools are necessary. The first one is -the "elftosb" tool distributed by Freescale Semiconductor. The other one is the -"mxsboot" tool found in U-Boot source tree. +To make a MXS based board bootable, some tools are necessary. The only +mandatory tool is the "mxsboot" tool found in U-Boot source tree. The +tool is built automatically when compiling U-Boot for i.MX23 or i.MX28. + +The production of BootStream image is handled via "mkimage", which is +also part of the U-Boot source tree. The "mkimage" requires OpenSSL +development libraries to be installed. In case of Debian and derivates, +this is installed by running: + + $ sudo apt-get install libssl-dev + +NOTE: The "elftosb" tool distributed by Freescale Semiconductor is no + longer necessary for general use of U-Boot on i.MX23 and i.MX28. + The mkimage supports generation of BootStream images encrypted + with a zero key, which is the vast majority of use-cases. In + case you do need to produce image encrypted with non-zero key + or other special features, please use the "elftosb" tool, + otherwise continue to section 2). The installation procedure of + the "elftosb" is outlined below: Firstly, obtain the elftosb archive from the following location: @@ -63,11 +79,6 @@ copy the binary by hand: Make sure the "elftosb" binary can be found in your $PATH, in this case this means "/usr/local/bin/" has to be in your $PATH. -Install the 'libssl-dev' package as well. On a Debian-based distribution, this -package can be installed as follows: - - $ sudo apt-get install libssl-dev - 2) Compiling U-Boot for a MXS based board ------------------------------------------- @@ -112,6 +123,18 @@ The code produces "u-boot.sb" file. This file needs to be augmented with a proper header to allow successful boot from SD or NAND. Adding the header is discussed in the following chapters. +NOTE: The process that produces u-boot.sb uses the mkimage to generate the + BootStream. The BootStream is encrypted with zero key. In case you need + some special features of the BootStream and plan on using the "elftosb" + tool instead, the invocation to produce a compatible BootStream with the + one produced by mkimage is outlined below. For further details, refer to + the documentation bundled with the "elftosb" package. + + $ elftosb -zf imx23 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx23.bd \ + -o u-boot.sb + $ elftosb -zf imx28 -c arch/arm/cpu/arm926ejs/mxs/u-boot-imx28.bd \ + -o u-boot.sb + 3) Installation of U-Boot for a MXS based board to SD card ---------------------------------------------------------- diff --git a/doc/README.scrapyard b/doc/README.scrapyard index 7cfb3a3..8ed09c7 100644 --- a/doc/README.scrapyard +++ b/doc/README.scrapyard @@ -11,7 +11,9 @@ easily if here is something they might want to dig for... Board Arch CPU Commit Removed Last known maintainer/contact ================================================================================================= -omap1510inn arm arm925t - - Kshitij Gupta <kshitij@ti.com> +pdnb3 arm ixp - 2013-09-24 Stefan Roese <sr@denx.de> +scpu arm ixp - 2013-09-24 Stefan Roese <sr@denx.de> +omap1510inn arm arm925t 0610a16 2013-09-23 Kshitij Gupta <kshitij@ti.com> CANBT powerpc 405CR fb8f4fd 2013-08-07 Matthias Fuchs <matthias.fuchs@esd.eu> Alaska8220 powerpc mpc8220 d6ed322 2013-05-11 Yukon8220 powerpc mpc8220 d6ed322 2013-05-11 diff --git a/drivers/bootcount/Makefile b/drivers/bootcount/Makefile index 012acef..8256ed0 100644 --- a/drivers/bootcount/Makefile +++ b/drivers/bootcount/Makefile @@ -6,4 +6,5 @@ obj-y += bootcount.o obj-$(CONFIG_AT91SAM9XE) += bootcount_at91.o obj-$(CONFIG_BLACKFIN) += bootcount_blackfin.o obj-$(CONFIG_SOC_DA8XX) += bootcount_davinci.o +obj-$(CONFIG_AM33XX) += bootcount_davinci.o obj-$(CONFIG_BOOTCOUNT_RAM) += bootcount_ram.o diff --git a/drivers/bootcount/bootcount_davinci.c b/drivers/bootcount/bootcount_davinci.c index efa4d42..f0acfad 100644 --- a/drivers/bootcount/bootcount_davinci.c +++ b/drivers/bootcount/bootcount_davinci.c @@ -6,8 +6,7 @@ */ #include <bootcount.h> -#include <asm/arch/da850_lowlevel.h> -#include <asm/arch/davinci_misc.h> +#include <asm/davinci_rtc.h> void bootcount_store(ulong a) { @@ -21,17 +20,19 @@ void bootcount_store(ulong a) */ writel(RTC_KICK0R_WE, ®->kick0r); writel(RTC_KICK1R_WE, ®->kick1r); - raw_bootcount_store(®->scratch0, a); - raw_bootcount_store(®->scratch1, BOOTCOUNT_MAGIC); + raw_bootcount_store(®->scratch2, + (BOOTCOUNT_MAGIC & 0xffff0000) | (a & 0x0000ffff)); } ulong bootcount_load(void) { + unsigned long val; struct davinci_rtc *reg = (struct davinci_rtc *)CONFIG_SYS_BOOTCOUNT_ADDR; - if (raw_bootcount_load(®->scratch1) != BOOTCOUNT_MAGIC) + val = raw_bootcount_load(®->scratch2); + if ((val & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) return 0; else - return raw_bootcount_load(®->scratch0); + return val & 0x0000ffff; } diff --git a/drivers/mtd/nand/davinci_nand.c b/drivers/mtd/nand/davinci_nand.c index d8bb5d3..5b17d7b 100644 --- a/drivers/mtd/nand/davinci_nand.c +++ b/drivers/mtd/nand/davinci_nand.c @@ -266,6 +266,17 @@ static int nand_davinci_correct_data(struct mtd_info *mtd, u_char *dat, static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { #if defined(CONFIG_SYS_NAND_PAGE_2K) .eccbytes = 40, +#ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC + .eccpos = { + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, + }, + .oobfree = { + {2, 4}, {16, 6}, {32, 6}, {48, 6}, + }, +#else .eccpos = { 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, @@ -276,6 +287,7 @@ static struct nand_ecclayout nand_davinci_4bit_layout_oobfirst = { .oobfree = { {.offset = 2, .length = 22, }, }, +#endif /* #ifdef CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC */ #elif defined(CONFIG_SYS_NAND_PAGE_4K) .eccbytes = 80, .eccpos = { diff --git a/drivers/net/macb.c b/drivers/net/macb.c index bf3983a..781a272 100644 --- a/drivers/net/macb.c +++ b/drivers/net/macb.c @@ -621,6 +621,24 @@ static u32 gem_mdc_clk_div(int id, struct macb_device *macb) return config; } +/* + * Get the DMA bus width field of the network configuration register that we + * should program. We find the width from decoding the design configuration + * register to find the maximum supported data bus width. + */ +static u32 macb_dbw(struct macb_device *macb) +{ + switch (GEM_BFEXT(DBWDEF, gem_readl(macb, DCFG1))) { + case 4: + return GEM_BF(DBW, GEM_DBW128); + case 2: + return GEM_BF(DBW, GEM_DBW64); + case 1: + default: + return GEM_BF(DBW, GEM_DBW32); + } +} + int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) { struct macb_device *macb; @@ -665,7 +683,7 @@ int macb_eth_initialize(int id, void *regs, unsigned int phy_addr) */ if (macb_is_gem(macb)) { ncfgr = gem_mdc_clk_div(id, macb); - ncfgr |= GEM_BF(DBW, 1); + ncfgr |= macb_dbw(macb); } else { ncfgr = macb_mdc_clk_div(id, macb); } diff --git a/drivers/net/macb.h b/drivers/net/macb.h index de5214f..06f7c66 100644 --- a/drivers/net/macb.h +++ b/drivers/net/macb.h @@ -58,6 +58,9 @@ #define MACB_WOL 0x00c4 #define MACB_MID 0x00fc +/* GEM specific register offsets */ +#define GEM_DCFG1 0x0280 + /* Bitfields in NCR */ #define MACB_LB_OFFSET 0 #define MACB_LB_SIZE 1 @@ -242,6 +245,14 @@ #define MACB_IDNUM_SIZE 16 /* Bitfields in DCFG1 */ +#define GEM_DBWDEF_OFFSET 25 +#define GEM_DBWDEF_SIZE 3 + +/* constants for data bus width */ +#define GEM_DBW32 0 +#define GEM_DBW64 1 +#define GEM_DBW128 2 + /* Constants for CLK */ #define MACB_CLK_DIV8 0 #define MACB_CLK_DIV16 1 diff --git a/drivers/rtc/davinci.c b/drivers/rtc/davinci.c index e60c0da..f862e2f 100644 --- a/drivers/rtc/davinci.c +++ b/drivers/rtc/davinci.c @@ -8,12 +8,12 @@ #include <command.h> #include <rtc.h> #include <asm/io.h> -#include <asm/arch/hardware.h> +#include <asm/davinci_rtc.h> #if defined(CONFIG_CMD_DATE) int rtc_get(struct rtc_time *tmp) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; unsigned long sec, min, hour, mday, wday, mon_cent, year; unsigned long status; @@ -57,7 +57,7 @@ int rtc_get(struct rtc_time *tmp) int rtc_set(struct rtc_time *tmp) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, @@ -75,7 +75,7 @@ int rtc_set(struct rtc_time *tmp) void rtc_reset(void) { - struct davinci_rtc *rtc = davinci_rtc_base; + struct davinci_rtc *rtc = (struct davinci_rtc *)DAVINCI_RTC_BASE; /* run RTC counter */ writel(0x01, &rtc->ctrl); diff --git a/drivers/usb/host/ohci-at91.c b/drivers/usb/host/ohci-at91.c index 9e90d59..c24505e 100644 --- a/drivers/usb/host/ohci-at91.c +++ b/drivers/usb/host/ohci-at91.c @@ -18,15 +18,15 @@ int usb_cpu_init(void) { at91_pmc_t *pmc = (at91_pmc_t *)ATMEL_BASE_PMC; -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) || \ - defined(CONFIG_AT91SAM9261) +#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB /* Enable PLLB */ writel(get_pllb_init(), &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != AT91_PMC_LOCKB) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3) +#ifdef CONFIG_AT91SAM9N12 + writel(AT91_PMC_USBS_USB_PLLB | AT91_PMC_USB_DIV_2, &pmc->usb); +#endif +#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) /* Enable UPLL */ writel(readl(&pmc->uckr) | AT91_PMC_UPLLEN | AT91_PMC_BIASEN, &pmc->uckr); @@ -70,14 +70,15 @@ int usb_cpu_stop(void) writel(ATMEL_PMC_UHP, &pmc->scdr); #endif -#if defined(CONFIG_AT91CAP9) || defined(CONFIG_AT91SAM9260) || \ - defined(CONFIG_AT91SAM9263) || defined(CONFIG_AT91SAM9G20) +#ifdef CONFIG_USB_ATMEL_CLK_SEL_PLLB +#ifdef CONFIG_AT91SAM9N12 + writel(0, &pmc->usb); +#endif /* Disable PLLB */ writel(0, &pmc->pllbr); while ((readl(&pmc->sr) & AT91_PMC_LOCKB) != 0) ; -#elif defined(CONFIG_AT91SAM9G45) || defined(CONFIG_AT91SAM9M10G45) || \ - defined(CONFIG_AT91SAM9X5) || defined(CONFIG_SAMA5D3) +#elif defined(CONFIG_USB_ATMEL_CLK_SEL_UPLL) /* Disable UPLL */ writel(readl(&pmc->uckr) & (~AT91_PMC_UPLLEN), &pmc->uckr); while ((readl(&pmc->sr) & AT91_PMC_LOCKU) == AT91_PMC_LOCKU) diff --git a/drivers/watchdog/imx_watchdog.c b/drivers/watchdog/imx_watchdog.c index 50e602a..d5993b4 100644 --- a/drivers/watchdog/imx_watchdog.c +++ b/drivers/watchdog/imx_watchdog.c @@ -19,6 +19,7 @@ struct watchdog_regs { #define WCR_WDBG 0x02 #define WCR_WDE 0x04 /* WDOG enable */ #define WCR_WDT 0x08 +#define WCR_SRS 0x10 #define WCR_WDW 0x80 #define SET_WCR_WT(x) (x << 8) @@ -45,7 +46,7 @@ void hw_watchdog_init(void) #define CONFIG_WATCHDOG_TIMEOUT_MSECS 128000 #endif timeout = (CONFIG_WATCHDOG_TIMEOUT_MSECS / 500) - 1; - writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | + writew(WCR_WDZST | WCR_WDBG | WCR_WDE | WCR_WDT | WCR_SRS | WCR_WDW | SET_WCR_WT(timeout), &wdog->wcr); hw_watchdog_reset(); } diff --git a/include/configs/afeb9260.h b/include/configs/afeb9260.h index a3e4fd2..5e71898 100644 --- a/include/configs/afeb9260.h +++ b/include/configs/afeb9260.h @@ -111,6 +111,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/igep0033.h b/include/configs/am335x_igep0033.h index 2c69d4e..2c69d4e 100644 --- a/include/configs/igep0033.h +++ b/include/configs/am335x_igep0033.h diff --git a/include/configs/at91rm9200ek.h b/include/configs/at91rm9200ek.h index c03f385..5d96c31 100644 --- a/include/configs/at91rm9200ek.h +++ b/include/configs/at91rm9200ek.h @@ -153,6 +153,7 @@ * USB Config */ #define CONFIG_USB_ATMEL 1 +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_KEYBOARD 1 #define CONFIG_USB_STORAGE 1 diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index ce0ca80..1c4bb81 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -184,6 +184,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 /* AT91SAM9260_UHP_BASE */ diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index fcdf044..226f8c1 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -145,6 +145,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 5a39392..0a1969d 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -278,6 +278,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 415a997..4ec1799 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -82,6 +82,7 @@ #define CONFIG_CMD_SF #define CONFIG_CMD_MMC #define CONFIG_CMD_FAT +#define CONFIG_CMD_USB #define CONFIG_NR_DRAM_BANKS 1 #define CONFIG_SYS_SDRAM_BASE 0x20000000 @@ -162,6 +163,18 @@ #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE #define CONFIG_SYS_MEMTEST_END 0x26e00000 +/* USB host */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB +#define CONFIG_USB_OHCI_NEW +#define CONFIG_SYS_USB_OHCI_CPU_INIT +#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI +#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9n12" +#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 +#define CONFIG_USB_STORAGE +#endif + #ifdef CONFIG_SYS_USE_SPIFLASH /* bootstrap + u-boot + env + linux in dataflash on CS0 */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index bb126b0..ea9a50e 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -158,13 +158,14 @@ #define CONFIG_USB_EHCI_ATMEL #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 2 #else +#define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9x5" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 3 #endif -#define CONFIG_USB_ATMEL #define CONFIG_USB_STORAGE #endif diff --git a/include/configs/bg0900.h b/include/configs/bg0900.h new file mode 100644 index 0000000..507d972 --- /dev/null +++ b/include/configs/bg0900.h @@ -0,0 +1,97 @@ +/* + * Copyright (C) 2013 Marek Vasut <marex@denx.de> + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef __CONFIGS_BG0900_H__ +#define __CONFIGS_BG0900_H__ + +/* System configurations */ +#define CONFIG_MX28 /* i.MX28 SoC */ + +/* U-Boot Commands */ +#define CONFIG_SYS_NO_FLASH +#include <config_cmd_default.h> +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DOS_PARTITION + +#define CONFIG_CMD_BOOTZ +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_GPIO +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NAND_TRIMFFS +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVEENV +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_SF +#define CONFIG_CMD_SPI + +/* Memory configuration */ +#define CONFIG_NR_DRAM_BANKS 1 /* 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x40000000 /* Base address */ +#define PHYS_SDRAM_1_SIZE 0x10000000 /* Max 256 MB RAM */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 + +/* Environment */ +#define CONFIG_ENV_SIZE (16 * 1024) +#define CONFIG_ENV_OVERWRITE +#define CONFIG_ENV_IS_NOWHERE + +/* FEC Ethernet on SoC */ +#ifdef CONFIG_CMD_NET +#define CONFIG_FEC_MXC +#define CONFIG_NET_MULTI +#endif + +/* SPI */ +#ifdef CONFIG_CMD_SPI +#define CONFIG_DEFAULT_SPI_BUS 2 +#define CONFIG_DEFAULT_SPI_CS 0 +#define CONFIG_DEFAULT_SPI_MODE SPI_MODE_0 + +/* SPI FLASH */ +#ifdef CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_BAR +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SF_DEFAULT_BUS 2 +#define CONFIG_SF_DEFAULT_CS 0 +#define CONFIG_SF_DEFAULT_SPEED 40000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#define CONFIG_ENV_SPI_BUS 2 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 40000000 +#define CONFIG_ENV_SPI_MODE SPI_MODE_0 +#endif + +#endif + +/* Boot Linux */ +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_BOOTARGS "console=ttyAMA0,115200" +#define CONFIG_BOOTCOMMAND "bootm" +#define CONFIG_LOADADDR 0x42000000 +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +/* Extra Environment */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "update_spi_firmware_filename=u-boot.sb\0" \ + "update_spi_firmware_maxsz=0x80000\0" \ + "update_spi_firmware=" /* Update the SPI flash firmware */ \ + "if sf probe 2:0 ; then " \ + "if tftp ${update_spi_firmware_filename} ; then " \ + "sf erase 0x0 +${filesize} ; " \ + "sf write ${loadaddr} 0x0 ${filesize} ; " \ + "fi ; " \ + "fi\0" + +/* The rest of the configuration is shared */ +#include <configs/mxs.h> + +#endif /* __CONFIGS_BG0900_H__ */ diff --git a/include/configs/cm_t35.h b/include/configs/cm_t35.h index 38fe064..516ef7f 100644 --- a/include/configs/cm_t35.h +++ b/include/configs/cm_t35.h @@ -23,6 +23,7 @@ #define CONFIG_OMAP /* in a TI OMAP core */ #define CONFIG_OMAP34XX /* which is a 34XX */ #define CONFIG_OMAP_GPIO +#define CONFIG_CMD_GPIO #define CONFIG_CM_T3X /* working with CM-T35 and CM-T3730 */ #define CONFIG_OMAP_COMMON @@ -169,7 +170,7 @@ #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ /* devices */ /* Environment information */ -#define CONFIG_BOOTDELAY 10 +#define CONFIG_BOOTDELAY 3 #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/cpu9260.h b/include/configs/cpu9260.h index 021be83..ccf36a5 100644 --- a/include/configs/cpu9260.h +++ b/include/configs/cpu9260.h @@ -345,6 +345,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/cpuat91.h b/include/configs/cpuat91.h index 3572ac5..49cfabd 100644 --- a/include/configs/cpuat91.h +++ b/include/configs/cpuat91.h @@ -159,6 +159,7 @@ #if defined(CONFIG_CMD_USB) #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/dra7xx_evm.h b/include/configs/dra7xx_evm.h index a9f39f2..8a69c7d 100644 --- a/include/configs/dra7xx_evm.h +++ b/include/configs/dra7xx_evm.h @@ -22,9 +22,14 @@ #define CONFIG_SYS_REDUNDAND_ENVIRONMENT #define CONFIG_CMD_SAVEENV +#if (CONFIG_CONS_INDEX == 1) #define CONSOLEDEV "ttyO0" -#define CONFIG_CONS_INDEX 1 -#define CONFIG_SYS_NS16550_COM1 UART1_BASE +#elif (CONFIG_CONS_INDEX == 3) +#define CONSOLEDEV "ttyO2" +#endif +#define CONFIG_SYS_NS16550_COM1 UART1_BASE /* Base EVM has UART0 */ +#define CONFIG_SYS_NS16550_COM2 UART2_BASE /* UART2 */ +#define CONFIG_SYS_NS16550_COM3 UART3_BASE /* UART3 */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_OMAP_ABE_SYSCK diff --git a/include/configs/eb_cpux9k2.h b/include/configs/eb_cpux9k2.h index cafaf88..2d8c42c 100644 --- a/include/configs/eb_cpux9k2.h +++ b/include/configs/eb_cpux9k2.h @@ -36,7 +36,7 @@ #define CONFIG_SYS_TEXT_BASE 0x00000000 #else #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SYS_TEXT_BASE 0x21f00000 +#define CONFIG_SYS_TEXT_BASE 0x21800000 #endif #define CONFIG_SYS_LOAD_ADDR 0x21000000 /* default load address */ #define CONFIG_STANDALONE_LOAD_ADDR 0x21000000 @@ -132,6 +132,7 @@ #define CONFIG_CMD_UBI #define CONFIG_CMD_MTDPARTS #define CONFIG_CMD_UBIFS + #define CONFIG_SYS_LONGHELP /* @@ -161,6 +162,7 @@ * Hardware drivers */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_AT91C_PQFP_UHPBUG #define CONFIG_USB_STORAGE diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 5d33c76..252df54 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -177,6 +177,7 @@ /* USB */ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE 0x00500000 diff --git a/include/configs/ipam390.h b/include/configs/ipam390.h index 3b5a1cd..fdd5680 100644 --- a/include/configs/ipam390.h +++ b/include/configs/ipam390.h @@ -121,13 +121,13 @@ (3 << DV_DDR_SDCR_IBANK_SHIFT) | \ (2 << DV_DDR_SDCR_PAGESIZE_SHIFT)) -#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(2) | \ +#define CONFIG_SYS_DA850_CS3CFG (DAVINCI_ABCR_WSETUP(1) | \ DAVINCI_ABCR_WSTROBE(2) | \ - DAVINCI_ABCR_WHOLD(1) | \ + DAVINCI_ABCR_WHOLD(0) | \ DAVINCI_ABCR_RSETUP(1) | \ - DAVINCI_ABCR_RSTROBE(4) | \ - DAVINCI_ABCR_RHOLD(0) | \ - DAVINCI_ABCR_TA(1) | \ + DAVINCI_ABCR_RSTROBE(2) | \ + DAVINCI_ABCR_RHOLD(1) | \ + DAVINCI_ABCR_TA(0) | \ DAVINCI_ABCR_ASIZE_8BIT) @@ -160,6 +160,7 @@ #undef CONFIG_SYS_NAND_HW_ECC #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST +#define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_5_ADDR_CYCLE #define CONFIG_SYS_NAND_PAGE_SIZE (2 << 10) #define CONFIG_SYS_NAND_BLOCK_SIZE (128 << 10) @@ -172,11 +173,10 @@ CONFIG_SYS_MALLOC_LEN - \ GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_NAND_ECCPOS { \ - 24, 25, 26, 27, 28, \ - 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, \ - 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, \ - 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, \ - 59, 60, 61, 62, 63 } + 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, \ + 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, \ + 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, \ + 54, 55, 56, 57, 58, 59, 60, 61, 62, 63} #define CONFIG_SYS_NAND_PAGE_COUNT 64 #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #define CONFIG_SYS_NAND_ECCSIZE 512 @@ -229,15 +229,24 @@ #define CONFIG_CMDLINE_TAG #define CONFIG_REVISION_TAG #define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_BOOTARGS \ - "mem=128M console=ttyS0,115200n8 root=/dev/mtdblock0p4 rw noinitrd ip=dhcp" -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 2 #define CONFIG_EXTRA_ENV_SETTINGS \ + "defbootargs=setenv bootargs mem=128M console=ttyS0,115200n8 " \ + "root=/dev/mtdblock5 rw noinitrd " \ + "rootfstype=jffs2 noinitrd\0" \ "hwconfig=dsp:wake=yes\0" \ + "bootcmd=nboot kernel;run defbootargs addmtd;bootm 0xc0700000\0" \ + "bootfile=uImage\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "mtddevname=uboot-env\0" \ + "mtddevnum=0\0" \ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "u-boot=/tftpboot/ipam390/u-boot.ais\0" \ + "upd_uboot=tftp c0000000 ${u-boot};nand erase.part u-boot;" \ + "nand write c0000000 20000 ${filesize}\0" \ "setbootparms=nand read c0100000 200000 400000;" \ + "run defbootargs addmtd;" \ "spl export atags c0100000;" \ "nand erase.part bootparms;" \ "nand write c0000100 180000 20000\0" \ diff --git a/include/configs/meesc.h b/include/configs/meesc.h index f188102..91f6e2f 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -156,6 +156,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/igep00x0.h b/include/configs/omap3_igep00x0.h index ac36ac6..ac36ac6 100644 --- a/include/configs/igep00x0.h +++ b/include/configs/omap3_igep00x0.h diff --git a/include/configs/omap4_common.h b/include/configs/omap4_common.h index 15f1f4d..ea56eeb 100644 --- a/include/configs/omap4_common.h +++ b/include/configs/omap4_common.h @@ -15,82 +15,61 @@ /* * High Level Configuration Options */ -#define CONFIG_ARMV7 1 /* This is an ARM V7 CPU core */ -#define CONFIG_OMAP 1 /* in a TI OMAP core */ #define CONFIG_OMAP44XX 1 /* which is a 44XX */ #define CONFIG_OMAP4430 1 /* which is in a 4430 */ -#define CONFIG_OMAP_GPIO -#define CONFIG_OMAP_COMMON +#define CONFIG_MISC_INIT_R +#define CONFIG_ARCH_CPU_INIT +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CONFIG_SYS_THUMB_BUILD + +#ifndef CONFIG_SYS_L2CACHE_OFF +#define CONFIG_SYS_L2_PL310 1 +#define CONFIG_SYS_PL310_BASE 0x48242000 +#endif +#define CONFIG_SYS_CACHELINE_SIZE 32 /* Get CPU defs */ #include <asm/arch/cpu.h> #include <asm/arch/omap.h> -/* Display CPU and Board Info */ -#define CONFIG_DISPLAY_CPUINFO 1 -#define CONFIG_DISPLAY_BOARDINFO 1 - -#define CONFIG_MISC_INIT_R - -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_CMD_BOOTZ -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 -#define CONFIG_REVISION_TAG 1 +/* Use General purpose timer 1 */ +#define CONFIG_SYS_TIMERBASE GPT2_BASE /* - * Size of malloc() pool * Total Size Environment - 128k - * Malloc - add 256k */ #define CONFIG_ENV_SIZE (128 << 10) -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (256 << 10)) -/* Vector Base */ -#define CONFIG_SYS_CA9_VECTOR_BASE SRAM_ROM_VECT_BASE /* - * Hardware drivers + * For the DDR timing information we can either dynamically determine + * the timings to use or use pre-determined timings (based on using the + * dynamic method. Default to the static timing infomation. */ +#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS +#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION +#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS +#endif + +#include <configs/ti_armv7_common.h> /* - * serial port - NS16550 compatible + * Hardware drivers */ -#define V_NS16550_CLK 48000000 - #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE (-4) -#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK +#define CONFIG_SYS_NS16550_CLK 48000000 #define CONFIG_CONS_INDEX 3 #define CONFIG_SYS_NS16550_COM3 UART3_BASE -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\ - 115200} - -/* CPU */ -#define CONFIG_ARCH_CPU_INIT - -/* I2C */ -#define CONFIG_HARD_I2C 1 -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 1 -#define CONFIG_DRIVER_OMAP34XX_I2C 1 -#define CONFIG_I2C_MULTI_BUS 1 - /* TWL6030 */ #ifndef CONFIG_SPL_BUILD #define CONFIG_TWL6030_POWER 1 #endif -/* MMC */ -#define CONFIG_GENERIC_MMC 1 -#define CONFIG_MMC 1 -#define CONFIG_OMAP_HSMMC 1 -#define CONFIG_DOS_PARTITION 1 - - /* USB */ #define CONFIG_MUSB_UDC 1 #define CONFIG_USB_OMAP3 1 @@ -100,36 +79,13 @@ #define CONFIG_USB_TTY 1 #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 -/* Flash */ -#define CONFIG_SYS_NO_FLASH 1 - -/* commands to include */ -#include <config_cmd_default.h> - -/* Enabled commands */ -#define CONFIG_CMD_EXT2 /* EXT2 Support */ -#define CONFIG_CMD_FAT /* FAT support */ -#define CONFIG_CMD_I2C /* I2C serial bus support */ -#define CONFIG_CMD_MMC /* MMC support */ - -/* Disabled commands */ +/* Per-Soc commands */ #undef CONFIG_CMD_NET #undef CONFIG_CMD_NFS -#undef CONFIG_CMD_FPGA /* FPGA configuration Support */ -#undef CONFIG_CMD_IMLS /* List all found images */ /* * Environment setup */ - -#define CONFIG_BOOTDELAY 3 -#define CONFIG_ENV_VARS_UBOOT_CONFIG -#define CONFIG_CMD_FS_GENERIC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_EXT4 - -#define CONFIG_ENV_OVERWRITE - #define CONFIG_EXTRA_ENV_SETTINGS \ "loadaddr=0x82000000\0" \ "console=ttyO2,115200n8\0" \ @@ -192,99 +148,10 @@ "fi; " \ "fi" -#define CONFIG_AUTO_COMPLETE 1 - -/* - * Miscellaneous configurable options - */ - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_CBSIZE 512 -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) - -/* - * memtest setup - */ -#define CONFIG_SYS_MEMTEST_START 0x80000000 -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (32 << 20)) - -/* Default load address */ -#define CONFIG_SYS_LOAD_ADDR 0x80000000 - -/* Use General purpose timer 1 */ -#define CONFIG_SYS_TIMERBASE GPT2_BASE -#define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ - -/* - * SDRAM Memory Map - * Even though we use two CS all the memory - * is mapped to one contiguous block - */ -#define CONFIG_NR_DRAM_BANKS 1 - -#define CONFIG_SYS_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_INIT_SP_ADDR (NON_SECURE_SRAM_END - \ - GENERATED_GBL_DATA_SIZE) - -#ifndef CONFIG_SYS_L2CACHE_OFF -#define CONFIG_SYS_L2_PL310 1 -#define CONFIG_SYS_PL310_BASE 0x48242000 -#endif -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* Defines for SDRAM init */ -#define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS - -#ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS -#define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION -#define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS -#endif - /* Defines for SPL */ -#define CONFIG_SPL -#define CONFIG_SPL_FRAMEWORK #define CONFIG_SPL_TEXT_BASE 0x40304350 #define CONFIG_SPL_MAX_SIZE (38 * 1024) -#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR #define CONFIG_SPL_DISPLAY_PRINT - -/* - * 64 bytes before this address should be set aside for u-boot.img's - * header. That is 80E7FFC0--0x80E80000 should not be used for any - * other needs. - */ -#define CONFIG_SYS_TEXT_BASE 0x80E80000 - -/* - * BSS and malloc area 64MB into memory to allow enough - * space for the kernel at the beginning of memory - */ -#define CONFIG_SPL_BSS_START_ADDR 0x84000000 -#define CONFIG_SPL_BSS_MAX_SIZE 0x100000 /* 1 MB */ -#define CONFIG_SYS_SPL_MALLOC_START 0x84100000 -#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ - -#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ -#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ -#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 -#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" - -#define CONFIG_SPL_LIBCOMMON_SUPPORT -#define CONFIG_SPL_LIBDISK_SUPPORT -#define CONFIG_SPL_I2C_SUPPORT -#define CONFIG_SPL_MMC_SUPPORT -#define CONFIG_SPL_FAT_SUPPORT -#define CONFIG_SPL_LIBGENERIC_SUPPORT -#define CONFIG_SPL_SERIAL_SUPPORT -#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" -#define CONFIG_SYS_THUMB_BUILD - #endif /* __CONFIG_OMAP4_COMMON_H */ diff --git a/include/configs/omap4_panda.h b/include/configs/omap4_panda.h index 8294622..6820e42 100644 --- a/include/configs/omap4_panda.h +++ b/include/configs/omap4_panda.h @@ -48,8 +48,6 @@ /* ENV related config options */ #define CONFIG_ENV_IS_NOWHERE -#define CONFIG_SYS_PROMPT "Panda # " - #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG #endif /* __CONFIG_PANDA_H */ diff --git a/include/configs/omap4_sdp4430.h b/include/configs/omap4_sdp4430.h index acced46..b352511 100644 --- a/include/configs/omap4_sdp4430.h +++ b/include/configs/omap4_sdp4430.h @@ -32,6 +32,4 @@ #define CONFIG_ENV_OFFSET 0xE0000 #define CONFIG_CMD_SAVEENV -#define CONFIG_SYS_PROMPT "OMAP4430 SDP # " - #endif /* __CONFIG_SDP4430_H */ diff --git a/include/configs/omap5_common.h b/include/configs/omap5_common.h index 827eaab..c7fa37e 100644 --- a/include/configs/omap5_common.h +++ b/include/configs/omap5_common.h @@ -70,10 +70,11 @@ #endif #define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ - "console=" CONSOLEDEV ",115200n8\0" \ + "loadaddr=0x80200000\0" \ + "fdtaddr=0x80F80000\0" \ "fdt_high=0xffffffff\0" \ - "fdtaddr=0x80f80000\0" \ + "rdaddr=0x81000000\0" \ + "console=" CONSOLEDEV ",115200n8\0" \ "fdtfile=undefined\0" \ "bootpart=0:2\0" \ "bootdir=/boot\0" \ diff --git a/include/configs/otc570.h b/include/configs/otc570.h index ae4054b..3f4e073 100644 --- a/include/configs/otc570.h +++ b/include/configs/otc570.h @@ -206,6 +206,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h deleted file mode 100644 index 98b2e0d..0000000 --- a/include/configs/pdnb3.h +++ /dev/null @@ -1,320 +0,0 @@ -/* - * (C) Copyright 2006-2007 - * Stefan Roese, DENX Software Engineering, sr@denx.de. - * - * Configuation settings for the PDNB3 board. - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ -#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ -#define CONFIG_PDNB3 1 /* on an PDNB3 board */ - -#define CONFIG_MACH_TYPE 1002 - -#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ -#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ - -/* - * Ethernet - */ -#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ -#define CONFIG_PHY_ADDR 16 /* NPE0 PHY address */ -#define CONFIG_HAS_ETH1 -#define CONFIG_PHY1_ADDR 18 /* NPE1 PHY address */ -#define CONFIG_MII 1 /* MII PHY management */ -#define CONFIG_SYS_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ - -/* - * Misc configuration options - */ -#define CONFIG_BOOTCOUNT_LIMIT /* support for bootcount limit */ -#define CONFIG_SYS_BOOTCOUNT_ADDR 0x60003000 /* inside qmrg sram */ - -#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (1 << 20) - -/* allow to overwrite serial and ethaddr */ -#define CONFIG_ENV_OVERWRITE - -#define CONFIG_IXP_SERIAL -#define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_IXP425_CONSOLE IXP425_UART1 /* we use UART1 for console */ - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_DATE -#define CONFIG_CMD_NET -#define CONFIG_CMD_MII -#define CONFIG_CMD_I2C -#define CONFIG_CMD_ELF -#define CONFIG_CMD_PING - -#if !defined(CONFIG_SCPU) -#define CONFIG_CMD_NAND -#endif - - -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x00400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ -#define CONFIG_SYS_LOAD_ADDR 0x00010000 /* default load address */ - -#define CONFIG_IXP425_TIMER_CLK 66666666 - -/*************************************************************** - * Platform/Board specific defines start here. - ***************************************************************/ - -/*----------------------------------------------------------------------- - * Default configuration (environment varibles...) - *----------------------------------------------------------------------*/ -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "hostname=pdnb3\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} ethaddr=${ethaddr} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate} " \ - "mtdparts=${mtdparts}\0" \ - "flash_nfs=run nfsargs addip addtty;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip addtty;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ - "bootm\0" \ - "rootpath=/opt/buildroot\0" \ - "bootfile=/tftpboot/netbox/uImage\0" \ - "kernel_addr=50080000\0" \ - "ramdisk_addr=50200000\0" \ - "load=tftp 100000 /tftpboot/netbox/u-boot.bin\0" \ - "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ - "cp.b 100000 50000000 ${filesize};" \ - "setenv filesize;saveenv\0" \ - "upd=run load update\0" \ - "ipaddr=10.0.0.233\0" \ - "serverip=10.0.0.152\0" \ - "netmask=255.255.0.0\0" \ - "ethaddr=c6:6f:13:36:f3:81\0" \ - "eth1addr=c6:6f:13:36:f3:82\0" \ - "mtdparts=IXP4XX-Flash.0:504k@0(uboot),4k@504k(env)," \ - "4k@508k(renv)\0" \ - "" -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ -#define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ - -#define CONFIG_SYS_TEXT_BASE 0x50000000 -#define CONFIG_SYS_FLASH_BASE 0x50000000 -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 512 kB for Monitor */ -#else -#define CONFIG_SYS_MONITOR_LEN (504 << 10) /* Reserve 512 kB for Monitor */ -#endif - -/* - * Expansion bus settings - */ -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_EXP_CS0 0x94d23C42 /* 8bit, max size */ -#else -#define CONFIG_SYS_EXP_CS0 0x94913C43 /* 8bit, max size */ -#endif -#define CONFIG_SYS_EXP_CS1 0x85000043 /* 8bit, 512bytes */ - -/* - * SDRAM settings - */ -#define CONFIG_SYS_SDR_CONFIG 0x18 -#define CONFIG_SYS_SDR_MODE_CONFIG 0x1 -#define CONFIG_SYS_SDRAM_REFRESH_CNT 0x81a - -/* - * FLASH and environment organization - */ -#if defined(CONFIG_SCPU) -#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ -#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ -#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ -#endif - -#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ - -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ - -#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 1000 /* Timeout for Flash Write (in ms) */ - -#define CONFIG_SYS_FLASH_WORD_SIZE unsigned char /* flash word size (width) */ -#define CONFIG_SYS_FLASH_ADDR0 0x5555 /* 1st address for flash config cycles */ -#define CONFIG_SYS_FLASH_ADDR1 0x2AAA /* 2nd address for flash config cycles */ -/* - * The following defines are added for buggy IOP480 byte interface. - * All other boards should use the standard values (CPCI405 etc.) - */ -#define CONFIG_SYS_FLASH_READ0 0x0000 /* 0 is standard */ -#define CONFIG_SYS_FLASH_READ1 0x0001 /* 1 is standard */ -#define CONFIG_SYS_FLASH_READ2 0x0002 /* 2 is standard */ - -#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -#define CONFIG_ENV_IS_IN_FLASH 1 - -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -#if defined(CONFIG_SCPU) -/* no redundant environment on SCPU */ -#define CONFIG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ -#else -#define CONFIG_ENV_SECT_SIZE 0x1000 /* size of one complete sector */ -#define CONFIG_ENV_SIZE 0x1000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) -#endif - -#if !defined(CONFIG_SCPU) -/* - * NAND-FLASH stuff - */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x51000000 /* NAND FLASH Base Address */ -#endif - -/* - * GPIO settings - */ - -/* FPGA program pin configuration */ -#define CONFIG_SYS_GPIO_PRG 12 /* FPGA program pin (cpu output)*/ -#define CONFIG_SYS_GPIO_CLK 10 /* FPGA clk pin (cpu output) */ -#define CONFIG_SYS_GPIO_DATA 14 /* FPGA data pin (cpu output) */ -#define CONFIG_SYS_GPIO_INIT 13 /* FPGA init pin (cpu input) */ -#define CONFIG_SYS_GPIO_DONE 11 /* FPGA done pin (cpu input) */ - -/* other GPIO's */ -#define CONFIG_SYS_GPIO_RESTORE_INT 0 -#define CONFIG_SYS_GPIO_RESTART_INT 1 -#define CONFIG_SYS_GPIO_SYS_RUNNING 2 -#define CONFIG_SYS_GPIO_PCI_INTA 3 -#define CONFIG_SYS_GPIO_PCI_INTB 4 -#define CONFIG_SYS_GPIO_I2C_SCL 6 -#define CONFIG_SYS_GPIO_I2C_SDA 7 -#define CONFIG_SYS_GPIO_FPGA_RESET 9 -#define CONFIG_SYS_GPIO_CLK_33M 15 - -/* - * I2C stuff - */ - -/* enable I2C and select the hardware/software driver */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SOFT_SPEED 83000 /* 83 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE -/* - * Software (bit-bang) I2C driver configuration - */ -#define PB_SCL (1 << CONFIG_SYS_GPIO_I2C_SCL) -#define PB_SDA (1 << CONFIG_SYS_GPIO_I2C_SDA) - -#define I2C_INIT GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SCL) -#define I2C_ACTIVE GPIO_OUTPUT_ENABLE(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_TRISTATE GPIO_OUTPUT_DISABLE(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_READ ((*IXP425_GPIO_GPINR & PB_SDA) != 0) -#define I2C_SDA(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SDA); \ - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SDA) -#define I2C_SCL(bit) if (bit) GPIO_OUTPUT_SET(CONFIG_SYS_GPIO_I2C_SCL); \ - else GPIO_OUTPUT_CLEAR(CONFIG_SYS_GPIO_I2C_SCL) -#define I2C_DELAY udelay(3) /* 1/4 I2C clock duration */ - -/* - * I2C RTC - */ -#if 0 /* test-only */ -#define CONFIG_RTC_DS1340 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#else -/* M41T11 Serial Access Timekeeper(R) SRAM */ -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 1900 /* play along with the linux driver */ -#endif - -/* - * Spartan3 FPGA configuration support - */ -#define CONFIG_SYS_FPGA_MAX_SIZE 700*1024 /* 700kByte for XC3S500E */ - -#define CONFIG_SYS_FPGA_PRG (1 << CONFIG_SYS_GPIO_PRG) /* FPGA program pin (cpu output)*/ -#define CONFIG_SYS_FPGA_CLK (1 << CONFIG_SYS_GPIO_CLK) /* FPGA clk pin (cpu output) */ -#define CONFIG_SYS_FPGA_DATA (1 << CONFIG_SYS_GPIO_DATA) /* FPGA data pin (cpu output) */ -#define CONFIG_SYS_FPGA_INIT (1 << CONFIG_SYS_GPIO_INIT) /* FPGA init pin (cpu input) */ -#define CONFIG_SYS_FPGA_DONE (1 << CONFIG_SYS_GPIO_DONE) /* FPGA done pin (cpu input) */ - -/* - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 32 - -/* additions for new relocation code, must be added to all boards */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_SDRAM_BASE + 0x1000 - GENERATED_GBL_DATA_SIZE) - -#endif /* __CONFIG_H */ diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 37c43f4..fc95cf0 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -243,6 +243,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index eccc027..533e249 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -270,6 +270,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 51fe0be..e0c388e 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -119,6 +119,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_DOS_PARTITION 1 #define CONFIG_SYS_USB_OHCI_CPU_INIT 1 diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index c38cf22..5a6f0fc 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -152,6 +152,7 @@ #ifdef CONFIG_CMD_USB #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_UPLL #define CONFIG_USB_OHCI_NEW #define CONFIG_SYS_USB_OHCI_CPU_INIT #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_BASE_OHCI diff --git a/include/configs/sbc35_a9g20.h b/include/configs/sbc35_a9g20.h index 1b07da4..cbcd4e1 100644 --- a/include/configs/sbc35_a9g20.h +++ b/include/configs/sbc35_a9g20.h @@ -118,6 +118,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/snapper9260.h b/include/configs/snapper9260.h index 988b680..5436bae 100644 --- a/include/configs/snapper9260.h +++ b/include/configs/snapper9260.h @@ -64,6 +64,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/stamp9g20.h b/include/configs/stamp9g20.h index 7d6f62b..248e657 100644 --- a/include/configs/stamp9g20.h +++ b/include/configs/stamp9g20.h @@ -164,6 +164,7 @@ /* USB configuration */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_USB_STORAGE #define CONFIG_DOS_PARTITION diff --git a/include/configs/ti_am335x_common.h b/include/configs/ti_am335x_common.h index d2e34ae..10fe47f 100644 --- a/include/configs/ti_am335x_common.h +++ b/include/configs/ti_am335x_common.h @@ -41,6 +41,17 @@ #define CONFIG_MII /* Required in net/eth.c */ /* + * RTC related defines. To use bootcount you must set bootlimit in the + * environment to a non-zero value. + */ +#define CONFIG_BOOTCOUNT_LIMIT +#define CONFIG_SYS_BOOTCOUNT_ADDR 0x44E3E000 + +/* Enable the HW watchdog, since we can use this with bootcount */ +#define CONFIG_HW_WATCHDOG +#define CONFIG_OMAP_WATCHDOG + +/* * SPL related defines. The Public RAM memory map the ROM defines the * area between 0x402F0400 and 0x4030B800 as a download area and * 0x4030B800 to 0x4030CE00 as a public stack area. The ROM also @@ -50,6 +61,9 @@ #define CONFIG_SPL_TEXT_BASE 0x402F0400 #define CONFIG_SPL_MAX_SIZE (0x4030B800 - CONFIG_SPL_TEXT_BASE) +/* Enable the watchdog inside of SPL */ +#define CONFIG_SPL_WATCHDOG_SUPPORT + /* * Since SPL did pll and ddr initialization for us, * we don't need to do it twice. diff --git a/include/configs/ti_armv7_common.h b/include/configs/ti_armv7_common.h index de83f7a..84269ad 100644 --- a/include/configs/ti_armv7_common.h +++ b/include/configs/ti_armv7_common.h @@ -201,7 +201,7 @@ #define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" #ifdef CONFIG_SPL_OS_BOOT -#define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + 0x100) +#define CONFIG_SYS_SPL_ARGS_ADDR 0x80F80000 /* FAT */ #define CONFIG_SPL_FAT_LOAD_KERNEL_NAME "uImage" diff --git a/include/configs/top9000.h b/include/configs/top9000.h index 578ba56..a96a9cb 100644 --- a/include/configs/top9000.h +++ b/include/configs/top9000.h @@ -173,6 +173,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT diff --git a/include/configs/tricorder.h b/include/configs/tricorder.h index d0cfd8e..d57394e 100644 --- a/include/configs/tricorder.h +++ b/include/configs/tricorder.h @@ -39,6 +39,9 @@ #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO +#define CONFIG_SILENT_CONSOLE +#define CONFIG_ZERO_BOOTDELAY_CHECK + /* Clock Defines */ #define V_OSCK 26000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK >> 1) @@ -53,12 +56,27 @@ #define CONFIG_OF_LIBFDT /* Size of malloc() pool */ -#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */ - /* Sector */ #define CONFIG_SYS_MALLOC_LEN (1024*1024) /* Hardware drivers */ +/* GPIO support */ +#define CONFIG_OMAP_GPIO + +/* LED support */ +#define CONFIG_STATUS_LED +#define CONFIG_BOARD_SPECIFIC_LED +#define CONFIG_CMD_LED /* LED command */ +#define STATUS_LED_BIT (1 << 0) +#define STATUS_LED_STATE STATUS_LED_ON +#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT1 (1 << 1) +#define STATUS_LED_STATE1 STATUS_LED_ON +#define STATUS_LED_PERIOD1 (CONFIG_SYS_HZ / 2) +#define STATUS_LED_BIT2 (1 << 2) +#define STATUS_LED_STATE2 STATUS_LED_ON +#define STATUS_LED_PERIOD2 (CONFIG_SYS_HZ / 2) + /* NS16550 Configuration */ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL @@ -84,6 +102,13 @@ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 1 #define CONFIG_DRIVER_OMAP34XX_I2C 1 +#define CONFIG_I2C_MULTI_BUS + +/* EEPROM */ +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_BUS_NUM 1 /* TWL4030 */ #define CONFIG_TWL4030_POWER @@ -92,13 +117,16 @@ /* Board NAND Info */ #define CONFIG_SYS_NO_FLASH /* no NOR flash */ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define MTDIDS_DEFAULT "nand0=nand" -#define MTDPARTS_DEFAULT "mtdparts=nand:" \ - "512k(u-boot-spl)," \ - "1920k(u-boot)," \ - "128k(u-boot-env)," \ - "4m(kernel)," \ - "-(fs)" +#define MTDIDS_DEFAULT "nand0=omap2-nand.0" +#define MTDPARTS_DEFAULT "mtdparts=omap2-nand.0:" \ + "128k(SPL)," \ + "1m(u-boot)," \ + "384k(u-boot-env1)," \ + "1152k(mtdoops)," \ + "384k(u-boot-env2)," \ + "5m(kernel)," \ + "2m(fdt)," \ + "-(ubi)" #define CONFIG_NAND_OMAP_GPMC #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ @@ -138,53 +166,104 @@ #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ #define CONFIG_MTD_PARTITIONS -/* Environment information */ -#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ +/* Environment information (this is the common part) */ -#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTDELAY 0 -#define CONFIG_EXTRA_ENV_SETTINGS \ - "loadaddr=0x82000000\0" \ +/* hang() the board on panic() */ +#define CONFIG_PANIC_HANG + +/* environment placement (for NAND), is different for FLASHCARD but does not + * harm there */ +#define CONFIG_ENV_OFFSET 0x120000 /* env start */ +#define CONFIG_ENV_OFFSET_REDUND 0x2A0000 /* redundant env start */ +#define CONFIG_ENV_SIZE (16 << 10) /* use 16KiB for env */ +#define CONFIG_ENV_RANGE (384 << 10) /* allow badblocks in env */ + +/* the loadaddr is the same as CONFIG_SYS_LOAD_ADDR, unfortunately the defiend + * value can not be used here! */ +#define CONFIG_LOADADDR 0x82000000 + +#define CONFIG_COMMON_ENV_SETTINGS \ "console=ttyO2,115200n8\0" \ "mmcdev=0\0" \ - "vram=12M\0" \ - "lcdmode=800x600\0" \ + "vram=3M\0" \ "defaultdisplay=lcd\0" \ - "kernelopts=rw rootwait\0" \ + "kernelopts=mtdoops.mtddev=3\0" \ + "mtdparts=" MTDPARTS_DEFAULT "\0" \ + "mtdids=" MTDIDS_DEFAULT "\0" \ "commonargs=" \ "setenv bootargs console=${console} " \ + "${mtdparts} " \ + "${kernelopts} " \ + "vt.global_cursor_default=0 " \ "vram=${vram} " \ - "omapfb.mode=lcd:${lcdmode} " \ - "omapdss.def_disp=${defaultdisplay}\0" \ + "omapdss.def_disp=${defaultdisplay}\0" + +#define CONFIG_BOOTCOMMAND "run autoboot" + +/* specific environment settings for different use cases + * FLASHCARD: used to run a rdimage from sdcard to program the device + * 'NORMAL': used to boot kernel from sdcard, nand, ... + * + * The main aim for the FLASHCARD skin is to have an embedded environment + * which will not be influenced by any data already on the device. + */ +#ifdef CONFIG_FLASHCARD + +#define CONFIG_ENV_IS_NOWHERE + +/* the rdaddr is 16 MiB before the loadaddr */ +#define CONFIG_ENV_RDADDR "rdaddr=0x81000000\0" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_COMMON_ENV_SETTINGS \ + CONFIG_ENV_RDADDR \ + "autoboot=" \ + "run commonargs; " \ + "setenv bootargs ${bootargs} " \ + "flashy_updateimg=/dev/mmcblk0p1:corscience_update.img " \ + "rdinit=/sbin/init; " \ + "mmc dev ${mmcdev}; mmc rescan; " \ + "fatload mmc ${mmcdev} ${loadaddr} uImage; " \ + "fatload mmc ${mmcdev} ${rdaddr} uRamdisk; " \ + "bootm ${loadaddr} ${rdaddr}\0" + +#else /* CONFIG_FLASHCARD */ + +#define CONFIG_ENV_OVERWRITE /* allow to overwrite serial and ethaddr */ + +#define CONFIG_ENV_IS_IN_NAND + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_COMMON_ENV_SETTINGS \ "mmcargs=" \ "run commonargs; " \ "setenv bootargs ${bootargs} " \ "root=/dev/mmcblk0p2 " \ - "${kernelopts}\0" \ + "rootwait " \ + "rw\0" \ "nandargs=" \ "run commonargs; " \ "setenv bootargs ${bootargs} " \ - "omapfb.mode=lcd:${lcdmode} " \ - "omapdss.def_disp=${defaultdisplay} " \ "root=ubi0:root " \ - "ubi.mtd=4 " \ + "ubi.mtd=7 " \ "rootfstype=ubifs " \ - "${kernelopts}\0" \ + "ro\0" \ "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source ${loadaddr}\0" \ "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ - "eraseenv=nand unlock 0x260000 0x20000; nand erase 0x260000 0x20000\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "bootm ${loadaddr}\0" \ - "loaduimage_ubi=mtd default; " \ - "ubi part fs; " \ + "loaduimage_ubi=ubi part ubi; " \ "ubifsmount ubi:root; " \ "ubifsload ${loadaddr} /boot/uImage\0" \ + "loaduimage_nand=nand read ${loadaddr} kernel 0x500000\0" \ "nandboot=echo Booting from nand ...; " \ "run nandargs; " \ - "run loaduimage_ubi; " \ + "run loaduimage_nand; " \ "bootm ${loadaddr}\0" \ "autoboot=mmc dev ${mmcdev}; if mmc rescan; then " \ "if run loadbootscript; then " \ @@ -197,12 +276,12 @@ "fi; " \ "else run nandboot; fi\0" - -#define CONFIG_BOOTCOMMAND "run autoboot" +#endif /* CONFIG_FLASHCARD */ /* Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_CMDLINE_EDITING /* enable cmdline history */ #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_PROMPT "OMAP3 Tricorder # " #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -214,9 +293,9 @@ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) -#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x07000000) +#define CONFIG_SYS_MEMTEST_START (OMAP34XX_SDRC_CS0 + 0x00000000) #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ - 0x01000000) /* 16MB */ + 0x07000000) /* 112 MB */ #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0 + 0x02000000) @@ -238,9 +317,6 @@ #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ -#define CONFIG_ENV_IS_IN_NAND 1 -#define CONFIG_ENV_OFFSET 0x260000 /* environment starts here */ - #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -258,6 +334,7 @@ #define CONFIG_SPL_NAND_SIMPLE #define CONFIG_SPL_BOARD_INIT +#define CONFIG_SPL_GPIO_SUPPORT #define CONFIG_SPL_LIBCOMMON_SUPPORT #define CONFIG_SPL_LIBDISK_SUPPORT #define CONFIG_SPL_I2C_SUPPORT @@ -276,7 +353,7 @@ #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ #define CONFIG_SPL_TEXT_BASE 0x40200000 /*CONFIG_SYS_SRAM_START*/ -#define CONFIG_SPL_MAX_SIZE (55 * 1024) /* 7 KB for stack */ +#define CONFIG_SPL_MAX_SIZE (57 * 1024) /* 7 KB for stack */ #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK #define CONFIG_SPL_BSS_START_ADDR 0x80000000 /*CONFIG_SYS_SDRAM_BASE*/ @@ -300,10 +377,12 @@ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 -#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x200000 +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 +#define CONFIG_SYS_NAND_U_BOOT_SIZE 0x100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 /* 1 MB */ +#define CONFIG_SYS_ALT_MEMTEST +#define CONFIG_SYS_MEMTEST_SCRATCH 0x81000000 #endif /* __CONFIG_H */ diff --git a/include/configs/udoo.h b/include/configs/udoo.h new file mode 100644 index 0000000..78df071 --- /dev/null +++ b/include/configs/udoo.h @@ -0,0 +1,206 @@ +/* + * Copyright (C) 2013 Freescale Semiconductor, Inc. + * + * Configuration settings for Udoo board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/imx-regs.h> +#include <asm/imx-common/gpio.h> +#include <asm/sizes.h> + +#define CONFIG_MX6 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define MACH_TYPE_UDOO 4800 +#define CONFIG_MACH_TYPE MACH_TYPE_UDOO + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN (2 * SZ_1M) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MXC_GPIO + +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART2_BASE + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +/* Command definition */ +#include <config_cmd_default.h> + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_BMODE +#define CONFIG_CMD_SETEXPR + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_SYS_MEMTEST_START 0x10000000 +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 500 * SZ_1M) +#define CONFIG_LOADADDR 0x12000000 +#define CONFIG_SYS_TEXT_BASE 0x17800000 + +/* MMC Configuration */ +#define CONFIG_FSL_ESDHC +#define CONFIG_FSL_USDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_MMC +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION + +#define CONFIG_DEFAULT_FDT_FILE "imx6q-udoo.dtb" + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "script=boot.scr\0" \ + "uimage=uImage\0" \ + "console=ttymxc1\0" \ + "splashpos=m,m\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "fdt_addr=0x11000000\0" \ + "boot_fdt=try\0" \ + "ip_dyn=yes\0" \ + "mmcdev=0\0" \ + "mmcpart=1\0" \ + "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \ + "update_sd_firmware_filename=u-boot.imx\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "loadbootscript=" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "loaduimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${uimage}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if run loadfdt; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${uimage}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \ + "bootm ${loadaddr} - ${fdt_addr}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootm; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootm; " \ + "fi;\0" + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev}; if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loaduimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi" + +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT "=> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +/* FLASH and environment organization */ +#define CONFIG_SYS_NO_FLASH + +#define CONFIG_ENV_SIZE (8 * 1024) + +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_SYS_MMC_ENV_DEV 0 + +#define CONFIG_OF_LIBFDT +#define CONFIG_CMD_BOOTZ + +#ifndef CONFIG_SYS_DCACHE_OFF +#define CONFIG_CMD_CACHE +#endif + +#endif /* __CONFIG_H * */ diff --git a/include/configs/vl_ma2sc.h b/include/configs/vl_ma2sc.h index 4c73134..1489080 100644 --- a/include/configs/vl_ma2sc.h +++ b/include/configs/vl_ma2sc.h @@ -116,6 +116,7 @@ /* USB */ #define CONFIG_USB_ATMEL +#define CONFIG_USB_ATMEL_CLK_SEL_PLLB #define CONFIG_USB_OHCI_NEW #define CONFIG_DOS_PARTITION #define CONFIG_SYS_USB_OHCI_CPU_INIT |