diff options
| -rw-r--r-- | CHANGELOG | 4 | ||||
| -rw-r--r-- | board/integratorap/integratorap.c | 28 | ||||
| -rw-r--r-- | board/integratorap/platform.S | 64 | ||||
| -rw-r--r-- | board/mpc8260ads/mpc8260ads.c | 4 | ||||
| -rw-r--r-- | board/omap2420h4/sys_info.c | 1 | ||||
| -rw-r--r-- | common/spartan3.c | 2 | ||||
| -rw-r--r-- | cpu/mpc8260/pci.c | 44 | ||||
| -rw-r--r-- | include/configs/MPC8260ADS.h | 11 | ||||
| -rw-r--r-- | include/configs/integratorap.h | 243 | ||||
| -rw-r--r-- | include/configs/omap2420h4.h | 7 |
10 files changed, 197 insertions, 211 deletions
@@ -28,8 +28,8 @@ Changes for U-Boot 1.1.4: Patch by Zachary Landau, 21 Feb 2005 * Update ep8260: Fix flash timeouts; improve clock resolution for faster UARTs - Patch by Jeff Angielski, 21 Feb 2005 - + Patch by Jeff Angielski, 21 Feb 2005 + * Fix au1x00_serial baud rate calculation: remove hardcoded cpu clock divisor and use register instead; round up instead of truncate diff --git a/board/integratorap/integratorap.c b/board/integratorap/integratorap.c index ff074ca..d4f61d6 100644 --- a/board/integratorap/integratorap.c +++ b/board/integratorap/integratorap.c @@ -36,7 +36,7 @@ #include <common.h> #ifdef CONFIG_PCI -# include <pci.h> +#include <pci.h> #endif void flash__init (void); @@ -46,7 +46,7 @@ void peripheral_power_enable (void); #if defined(CONFIG_SHOW_BOOT_PROGRESS) void show_boot_progress(int progress) { - printf("Boot reached stage %d\n", progress); + printf("Boot reached stage %d\n", progress); } #endif @@ -79,7 +79,7 @@ int board_init (void) extern void cm_remap(void); cm_remap(); /* remaps writeable memory to 0x00000000 */ #endif - + icache_enable (); flash__init (); @@ -483,7 +483,7 @@ int dram_init (void) DECLARE_GLOBAL_DATA_PTR; gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; #ifdef CONFIG_CM_SPD_DETECT { @@ -492,22 +492,22 @@ extern void dram_query(void); unsigned long sdram_shift; dram_query(); /* Assembler accesses to CM registers */ - /* Queries the SPD values */ + /* Queries the SPD values */ /* Obtain the SDRAM size from the CM SDRAM register */ cm_reg_sdram = *(volatile ulong *)(CM_BASE + OS_SDRAM); - /* Register SDRAM size + /* Register SDRAM size + * + * 0xXXXXXXbbb000bb 16 MB + * 0xXXXXXXbbb001bb 32 MB + * 0xXXXXXXbbb010bb 64 MB + * 0xXXXXXXbbb011bb 128 MB + * 0xXXXXXXbbb100bb 256 MB * - * 0xXXXXXXbbb000bb 16 MB - * 0xXXXXXXbbb001bb 32 MB - * 0xXXXXXXbbb010bb 64 MB - * 0xXXXXXXbbb011bb 128 MB - * 0xXXXXXXbbb100bb 256 MB - * */ - sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; - gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; + sdram_shift = ((cm_reg_sdram & 0x0000001C)/4)%4; + gd->bd->bi_dram[0].size = 0x01000000 << sdram_shift; } #endif /* CM_SPD_DETECT */ diff --git a/board/integratorap/platform.S b/board/integratorap/platform.S index fefee72..2d9b436 100644 --- a/board/integratorap/platform.S +++ b/board/integratorap/platform.S @@ -36,7 +36,7 @@ reset_cpu: reset_failed: b reset_failed - + /* set up the platform, once the cpu has been initialized */ .globl platformsetup platformsetup: @@ -48,45 +48,45 @@ platformsetup: * itself should be performed in cpu/arm<>/start.S * This function affects only the core module or board settings */ - + #ifdef CONFIG_CM_INIT /* CM has an initialization register * - bits in it are wired into test-chip pins to force * reset defaults * - may need to change its contents for U-Boot */ - + /* set the desired CM specific value */ mov r2,#CMMASK_LOWVEC /* Vectors at 0x00000000 for all */ - + #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) orr r2,r2,#CMMASK_INIT_102 #else - + #if !defined (CONFIG_CM920T) && !defined (CONFIG_CM920T_ETM) && \ !defined (CONFIG_CM940T) - + #ifdef CONFIG_CM_MULTIPLE_SSRAM /* set simple mapping */ and r2,r2,#CMMASK_MAP_SIMPLE #endif /* #ifdef CONFIG_CM_MULTIPLE_SSRAM */ - + #ifdef CONFIG_CM_TCRAM /* disable TCRAM */ and r2,r2,#CMMASK_TCRAM_DISABLE #endif /* #ifdef CONFIG_CM_TCRAM */ - + #if defined (CONFIG_CM926EJ_S) || defined (CONFIG_CM1026EJ_S) || \ defined (CONFIG_CM1136JF_S) and r2,r2,#CMMASK_LE - + #endif /* cpu with little endian initialization */ - + orr r2,r2,#CMMASK_CMxx6_COMMON - + #endif /* CMxx6 code */ - + #endif /* ARM102xxE value */ /* read CM_INIT */ @@ -96,7 +96,7 @@ platformsetup: and r3,r1,r2 cmp r3,r2 beq init_reg_OK - + /* lock for change */ mov r3, #CMVAL_LOCK and r3,r3,#CMMASK_LOCK @@ -107,16 +107,16 @@ platformsetup: str r1, [r0, #OS_INIT] mov r1, #CMVAL_UNLOCK str r1, [r0, #OS_LOCK] - + /* soft reset so new values used */ b reset_cpu - + init_reg_OK: - + #endif /* CONFIG_CM_INIT */ - + mov pc, lr - + #ifdef CONFIG_CM_SPD_DETECT /* Fast memory is available for the DRAM data * - ensure it has been transferred, then summarize the data @@ -128,13 +128,13 @@ dram_query: /* set up SDRAM info */ /* - based on example code from the CM User Guide */ mov r0, #CM_BASE - + readspdbit: ldr r1, [r0, #OS_SDRAM] /* read the SDRAM register */ and r1, r1, #0x20 /* mask SPD bit (5) */ cmp r1, #0x20 /* test if set */ bne readspdbit - + setupsdram: add r0, r0, #OS_SPD /* address the copy of the SDP data */ ldrb r1, [r0, #3] /* number of row address lines */ @@ -148,40 +148,40 @@ setupsdram: bne not16 mov r6, #0x2 /* store size and CAS latency of 2 */ b writesize - + not16: cmp r5, #0x20 /* is it 32MB? */ bne not32 mov r6, #0x6 b writesize - + not32: cmp r5, #0x40 /* is it 64MB? */ bne not64 mov r6, #0xa b writesize - + not64: cmp r5, #0x80 /* is it 128MB? */ bne not128 mov r6, #0xe b writesize - + not128: /* if it is none of these sizes then it is either 256MB, or * there is no SDRAM fitted so default to 256MB */ mov r6, #0x12 - + writesize: mov r1, r1, ASL#8 /* row addr lines from SDRAM reg */ orr r2, r1, r2, ASL#12 /* OR in column address lines */ orr r3, r2, r3, ASL#16 /* OR in number of banks */ orr r6, r6, r3 /* OR in size and CAS latency */ str r6, [r0, #OS_SDRAM] /* store SDRAM parameters */ - + #endif /* #ifdef CONFIG_CM_SPD_DETECT */ - + ldmfd r13!,{r4-r6,pc} /* back to caller */ #ifdef CONFIG_CM_REMAP @@ -191,23 +191,23 @@ writesize: .globl cm_remap cm_remap: stmfd r13!,{r4-r10,lr} - + mov r0, #CM_BASE ldr r1, [r0, #OS_CTRL] orr r1, r1, #CMMASK_REMAP /* set remap and led bits */ str r1, [r0, #OS_CTRL] - + /* Now 0x00000000 is writeable, replace the vectors */ ldr r0, =_start /* r0 <- start of vectors */ ldr r2, =_armboot_start /* r2 <- past vectors */ sub r1,r1,r1 /* destination 0x00000000 */ - + copy_vec: ldmia r0!, {r3-r10} /* copy from source address [r0] */ stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end address [r2] */ ble copy_vec - + ldmfd r13!,{r4-r10,pc} /* back to caller */ - + #endif /* #ifdef CONFIG_CM_REMAP */ diff --git a/board/mpc8260ads/mpc8260ads.c b/board/mpc8260ads/mpc8260ads.c index 2125963..a1d0a08 100644 --- a/board/mpc8260ads/mpc8260ads.c +++ b/board/mpc8260ads/mpc8260ads.c @@ -13,7 +13,7 @@ * Yuli Barcohen <yuli@arabellasw.com> * Added support for SDRAM DIMMs SPD EEPROM, MII, Ethernet PHY init. * - * Copyright (c) 2005 MontaVista Software, Inc. + * Copyright (c) 2005 MontaVista Software, Inc. * Vitaly Bordug <vbordug@ru.mvista.com> * Added support for PCI. * @@ -267,7 +267,7 @@ int board_early_init_f (void) #ifdef CONFIG_PCI volatile pci_ic_t* pci_ic = (pci_ic_t *) CFG_PCI_INT; - + /* mask alll the PCI interrupts */ pci_ic->pci_int_mask |= 0xfff00000; #endif diff --git a/board/omap2420h4/sys_info.c b/board/omap2420h4/sys_info.c index 9864d3e..a9f7241 100644 --- a/board/omap2420h4/sys_info.c +++ b/board/omap2420h4/sys_info.c @@ -385,4 +385,3 @@ u32 get_device_type(void) mode = __raw_readl(CONTROL_STATUS) & (BIT10|BIT9|BIT8); return(mode >>= 8); } - diff --git a/common/spartan3.c b/common/spartan3.c index f9302e1..c0f2b05 100644 --- a/common/spartan3.c +++ b/common/spartan3.c @@ -26,7 +26,7 @@ * Configuration support for Xilinx Spartan3 devices. Based * on spartan2.c (Rich Ireland, rireland@enterasys.com). */ - + #include <common.h> /* core U-Boot definitions */ #include <spartan3.h> /* Spartan-II device family */ diff --git a/cpu/mpc8260/pci.c b/cpu/mpc8260/pci.c index cb0c79b..44576de 100644 --- a/cpu/mpc8260/pci.c +++ b/cpu/mpc8260/pci.c @@ -2,7 +2,7 @@ * (C) Copyright 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * - * Copyright (c) 2005 MontaVista Software, Inc. + * Copyright (c) 2005 MontaVista Software, Inc. * Vitaly Bordug <vbordug@ru.mvista.com> * Added support for PCI bridge on MPC8272ADS * @@ -253,25 +253,25 @@ void pci_mpc8250_init (struct pci_controller *hose) (immap->im_siu_conf.sc_siumcr & ~SIUMCR_LBPC11) | SIUMCR_LBPC01; #elif defined CONFIG_MPC8272 - immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & - ~SIUMCR_BBD & - ~SIUMCR_ESE & - ~SIUMCR_PBSE & - ~SIUMCR_CDIS & - ~SIUMCR_DPPC11 & - ~SIUMCR_L2CPC11 & - ~SIUMCR_LBPC11 & - ~SIUMCR_APPC11 & - ~SIUMCR_CS10PC11 & - ~SIUMCR_BCTLC11 & - ~SIUMCR_MMR11) - | SIUMCR_DPPC11 - | SIUMCR_L2CPC01 - | SIUMCR_LBPC00 - | SIUMCR_APPC10 - | SIUMCR_CS10PC00 - | SIUMCR_BCTLC00 - | SIUMCR_MMR11; + immap->im_siu_conf.sc_siumcr = (immap->im_siu_conf.sc_siumcr & + ~SIUMCR_BBD & + ~SIUMCR_ESE & + ~SIUMCR_PBSE & + ~SIUMCR_CDIS & + ~SIUMCR_DPPC11 & + ~SIUMCR_L2CPC11 & + ~SIUMCR_LBPC11 & + ~SIUMCR_APPC11 & + ~SIUMCR_CS10PC11 & + ~SIUMCR_BCTLC11 & + ~SIUMCR_MMR11) + | SIUMCR_DPPC11 + | SIUMCR_L2CPC01 + | SIUMCR_LBPC00 + | SIUMCR_APPC10 + | SIUMCR_CS10PC00 + | SIUMCR_BCTLC00 + | SIUMCR_MMR11; #else /* @@ -399,7 +399,7 @@ void pci_mpc8250_init (struct pci_controller *hose) hose->last_busno = 0xff; /* System memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 pci_set_region (hose->regions + 0, PCI_SLV_MEM_BUS, PCI_SLV_MEM_LOCAL, @@ -412,7 +412,7 @@ void pci_mpc8250_init (struct pci_controller *hose) #endif /* PCI memory space */ -#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 +#if defined CONFIG_MPC8266ADS || defined CONFIG_MPC8272 pci_set_region (hose->regions + 1, PCI_MSTR_MEMIO_BUS, PCI_MSTR_MEMIO_LOCAL, diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 61a1c27..d8c609b 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -13,7 +13,7 @@ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. * Ported to MPC8272ADS board. * - * Copyright (c) 2005 MontaVista Software, Inc. + * Copyright (c) 2005 MontaVista Software, Inc. * Vitaly Bordug <vbordug@ru.mvista.com> * Added support for PCI bridge on MPC8272ADS * @@ -55,7 +55,6 @@ # define CFG_LOWBOOT 1 #endif - /* ADS flavours */ #define CFG_8260ADS 1 /* MPC8260ADS */ #define CFG_8266ADS 2 /* MPC8266ADS */ @@ -185,7 +184,6 @@ #define CONFIG_PCI_SCAN_SHOW #endif - #ifndef CONFIG_SDRAM_PBI #define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif @@ -334,7 +332,6 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - #ifdef CFG_LOWBOOT /* PQ2FADS flash HRCW = 0x0EB4B645 */ #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ @@ -386,13 +383,11 @@ # define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ - #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ #if (CONFIG_COMMANDS & CFG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - #define CFG_HID0_INIT 0 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) @@ -461,8 +456,6 @@ * these windows. */ - - /* * Master window that allows the CPU to access PCI Memory (prefetch). * This window will be setup with the second set of Outbound ATU registers @@ -504,7 +497,7 @@ #define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ #define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ /* PCIBR1 - prefetch and non-prefetch regions joined together */ -#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL #define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ diff --git a/include/configs/integratorap.h b/include/configs/integratorap.h index 25f4682..ad92f32 100644 --- a/include/configs/integratorap.h +++ b/include/configs/integratorap.h @@ -38,15 +38,15 @@ #define CFG_MEMTEST_END 0x10000000 #define CFG_HZ 1000 #define CFG_HZ_CLOCK 24000000 /* Timer 1 is clocked at 24Mhz */ -#define CFG_TIMERBASE 0x13000100 /* Timer1 */ +#define CFG_TIMERBASE 0x13000100 /* Timer1 */ #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ #define CONFIG_SETUP_MEMORY_TAGS 1 #define CONFIG_MISC_INIT_R 1 /* call misc_init_r during start up */ #undef CONFIG_INIT_CRITICAL -#define CONFIG_CM_INIT 1 -#define CONFIG_CM_REMAP 1 +#define CONFIG_CM_INIT 1 +#define CONFIG_CM_REMAP 1 #undef CONFIG_CM_SPD_DETECT /* @@ -60,36 +60,36 @@ */ #define CFG_PL010_SERIAL #define CONFIG_CONS_INDEX 0 -#define CONFIG_BAUDRATE 38400 +#define CONFIG_BAUDRATE 38400 #define CONFIG_PL01x_PORTS { (void *) (CFG_SERIAL0), (void *) (CFG_SERIAL1) } -#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } #define CFG_SERIAL0 0x16000000 #define CFG_SERIAL1 0x17000000 /*#define CONFIG_COMMANDS (CFG_CMD_DHCP | CFG_CMD_IMI | CFG_CMD_NET | CFG_CMD_PING | CFG_CMD_BDI | CFG_CMD_PCI) */ /*#define CONFIG_NET_MULTI */ -/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ +/*#define CONFIG_BOOTP_MASK CONFIG_BOOTP_DEFAULT */ -#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) +#define CONFIG_COMMANDS (CFG_CMD_IMI | CFG_CMD_BDI | CFG_CMD_MEMORY) /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ #include <cmd_confdefs.h> -#define CONFIG_BOOTDELAY 2 -#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" -#define CONFIG_BOOTCOMMAND "" +#define CONFIG_BOOTDELAY 2 +#define CONFIG_BOOTARGS "root=/dev/mtdblock0 mem=32M console=ttyAM0 console=tty" +#define CONFIG_BOOTCOMMAND "" /* * Miscellaneous configurable options */ -#define CFG_LONGHELP /* undef to save memory */ +#define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "Integrator-AP # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ /* Print Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ #define CFG_LOAD_ADDR 0x7fc0 /* default load address */ @@ -108,11 +108,11 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ #define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ -#define CFG_FLASH_BASE 0x24000000 +#define CFG_FLASH_BASE 0x24000000 /*----------------------------------------------------------------------- * FLASH and environment organization @@ -123,8 +123,8 @@ /* timeout values are in ticks */ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ -#define CFG_MAX_FLASH_SECT 128 -#define CFG_ENV_SIZE 32768 +#define CFG_MAX_FLASH_SECT 128 +#define CFG_ENV_SIZE 32768 #define PHYS_FLASH_1 (CFG_FLASH_BASE) @@ -134,35 +134,35 @@ /*#define CONFIG_PCI /--* include pci support */ #undef CONFIG_PCI_PNP -#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ +#define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */ #define DEBUG #define CONFIG_EEPRO100 -#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ +#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ #define INTEGRATOR_BOOT_ROM_BASE 0x20000000 -#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 +#define INTEGRATOR_HDR0_SDRAM_BASE 0x80000000 /* PCI Base area */ #define INTEGRATOR_PCI_BASE 0x40000000 #define INTEGRATOR_PCI_SIZE 0x3FFFFFFF /* memory map as seen by the CPU on the local bus */ -#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ +#define CPU_PCI_IO_ADRS 0x60000000 /* PCI I/O space base */ #define CPU_PCI_IO_SIZE 0x10000 #define CPU_PCI_CNFG_ADRS 0x61000000 /* PCI config space */ #define CPU_PCI_CNFG_SIZE 0x1000000 -#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ +#define PCI_MEM_BASE 0x40000000 /* 512M to xxx */ /* unused 256M from A0000000-AFFFFFFF might be used for I2O ??? */ -#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ +#define INTEGRATOR_PCI_IO_BASE 0x60000000 /* 16M to xxx */ /* unused (128-16)M from B1000000-B7FFFFFF */ -#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ +#define PCI_CONFIG_BASE 0x61000000 /* 16M to xxx */ /* unused ((128-16)M - 64K) from XXX */ -#define PCI_V3_BASE 0x62000000 +#define PCI_V3_BASE 0x62000000 /* V3 PCI bridge controller */ #define V3_BASE 0x62000000 /* V360EPC registers */ @@ -171,97 +171,97 @@ #define PCI_ENET0_MEMADDR (PCI_MEM_BASE) -#define V3_PCI_VENDOR 0x00000000 -#define V3_PCI_DEVICE 0x00000002 -#define V3_PCI_CMD 0x00000004 -#define V3_PCI_STAT 0x00000006 -#define V3_PCI_CC_REV 0x00000008 -#define V3_PCI_HDR_CF 0x0000000C -#define V3_PCI_IO_BASE 0x00000010 -#define V3_PCI_BASE0 0x00000014 -#define V3_PCI_BASE1 0x00000018 -#define V3_PCI_SUB_VENDOR 0x0000002C -#define V3_PCI_SUB_ID 0x0000002E -#define V3_PCI_ROM 0x00000030 -#define V3_PCI_BPARAM 0x0000003C -#define V3_PCI_MAP0 0x00000040 -#define V3_PCI_MAP1 0x00000044 -#define V3_PCI_INT_STAT 0x00000048 -#define V3_PCI_INT_CFG 0x0000004C -#define V3_LB_BASE0 0x00000054 -#define V3_LB_BASE1 0x00000058 -#define V3_LB_MAP0 0x0000005E -#define V3_LB_MAP1 0x00000062 -#define V3_LB_BASE2 0x00000064 -#define V3_LB_MAP2 0x00000066 -#define V3_LB_SIZE 0x00000068 -#define V3_LB_IO_BASE 0x0000006E -#define V3_FIFO_CFG 0x00000070 -#define V3_FIFO_PRIORITY 0x00000072 -#define V3_FIFO_STAT 0x00000074 -#define V3_LB_ISTAT 0x00000076 -#define V3_LB_IMASK 0x00000077 -#define V3_SYSTEM 0x00000078 -#define V3_LB_CFG 0x0000007A -#define V3_PCI_CFG 0x0000007C -#define V3_DMA_PCI_ADR0 0x00000080 -#define V3_DMA_PCI_ADR1 0x00000090 -#define V3_DMA_LOCAL_ADR0 0x00000084 -#define V3_DMA_LOCAL_ADR1 0x00000094 -#define V3_DMA_LENGTH0 0x00000088 -#define V3_DMA_LENGTH1 0x00000098 -#define V3_DMA_CSR0 0x0000008B -#define V3_DMA_CSR1 0x0000009B -#define V3_DMA_CTLB_ADR0 0x0000008C -#define V3_DMA_CTLB_ADR1 0x0000009C -#define V3_DMA_DELAY 0x000000E0 -#define V3_MAIL_DATA 0x000000C0 -#define V3_PCI_MAIL_IEWR 0x000000D0 -#define V3_PCI_MAIL_IERD 0x000000D2 -#define V3_LB_MAIL_IEWR 0x000000D4 -#define V3_LB_MAIL_IERD 0x000000D6 -#define V3_MAIL_WR_STAT 0x000000D8 -#define V3_MAIL_RD_STAT 0x000000DA -#define V3_QBA_MAP 0x000000DC +#define V3_PCI_VENDOR 0x00000000 +#define V3_PCI_DEVICE 0x00000002 +#define V3_PCI_CMD 0x00000004 +#define V3_PCI_STAT 0x00000006 +#define V3_PCI_CC_REV 0x00000008 +#define V3_PCI_HDR_CF 0x0000000C +#define V3_PCI_IO_BASE 0x00000010 +#define V3_PCI_BASE0 0x00000014 +#define V3_PCI_BASE1 0x00000018 +#define V3_PCI_SUB_VENDOR 0x0000002C +#define V3_PCI_SUB_ID 0x0000002E +#define V3_PCI_ROM 0x00000030 +#define V3_PCI_BPARAM 0x0000003C +#define V3_PCI_MAP0 0x00000040 +#define V3_PCI_MAP1 0x00000044 +#define V3_PCI_INT_STAT 0x00000048 +#define V3_PCI_INT_CFG 0x0000004C +#define V3_LB_BASE0 0x00000054 +#define V3_LB_BASE1 0x00000058 +#define V3_LB_MAP0 0x0000005E +#define V3_LB_MAP1 0x00000062 +#define V3_LB_BASE2 0x00000064 +#define V3_LB_MAP2 0x00000066 +#define V3_LB_SIZE 0x00000068 +#define V3_LB_IO_BASE 0x0000006E +#define V3_FIFO_CFG 0x00000070 +#define V3_FIFO_PRIORITY 0x00000072 +#define V3_FIFO_STAT 0x00000074 +#define V3_LB_ISTAT 0x00000076 +#define V3_LB_IMASK 0x00000077 +#define V3_SYSTEM 0x00000078 +#define V3_LB_CFG 0x0000007A +#define V3_PCI_CFG 0x0000007C +#define V3_DMA_PCI_ADR0 0x00000080 +#define V3_DMA_PCI_ADR1 0x00000090 +#define V3_DMA_LOCAL_ADR0 0x00000084 +#define V3_DMA_LOCAL_ADR1 0x00000094 +#define V3_DMA_LENGTH0 0x00000088 +#define V3_DMA_LENGTH1 0x00000098 +#define V3_DMA_CSR0 0x0000008B +#define V3_DMA_CSR1 0x0000009B +#define V3_DMA_CTLB_ADR0 0x0000008C +#define V3_DMA_CTLB_ADR1 0x0000009C +#define V3_DMA_DELAY 0x000000E0 +#define V3_MAIL_DATA 0x000000C0 +#define V3_PCI_MAIL_IEWR 0x000000D0 +#define V3_PCI_MAIL_IERD 0x000000D2 +#define V3_LB_MAIL_IEWR 0x000000D4 +#define V3_LB_MAIL_IERD 0x000000D6 +#define V3_MAIL_WR_STAT 0x000000D8 +#define V3_MAIL_RD_STAT 0x000000DA +#define V3_QBA_MAP 0x000000DC /* SYSTEM register bits */ -#define V3_SYSTEM_M_RST_OUT (1 << 15) -#define V3_SYSTEM_M_LOCK (1 << 14) +#define V3_SYSTEM_M_RST_OUT (1 << 15) +#define V3_SYSTEM_M_LOCK (1 << 14) /* PCI_CFG bits */ -#define V3_PCI_CFG_M_RETRY_EN (1 << 10) -#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) -#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) +#define V3_PCI_CFG_M_RETRY_EN (1 << 10) +#define V3_PCI_CFG_M_AD_LOW1 (1 << 9) +#define V3_PCI_CFG_M_AD_LOW0 (1 << 8) /* PCI MAP register bits (PCI -> Local bus) */ -#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 -#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) -#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) -#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) -#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 -#define V3_PCI_MAP_M_REG_EN (1 << 1) -#define V3_PCI_MAP_M_ENABLE (1 << 0) +#define V3_PCI_MAP_M_MAP_ADR 0xFFF00000 +#define V3_PCI_MAP_M_RD_POST_INH (1 << 15) +#define V3_PCI_MAP_M_ROM_SIZE (1 << 11 | 1 << 10) +#define V3_PCI_MAP_M_SWAP (1 << 9 | 1 << 8) +#define V3_PCI_MAP_M_ADR_SIZE 0x000000F0 +#define V3_PCI_MAP_M_REG_EN (1 << 1) +#define V3_PCI_MAP_M_ENABLE (1 << 0) /* 9 => 512M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 +#define V3_PCI_MAP_M_ADR_SIZE_512M 0x00000090 /* A => 1024M window size */ -#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 +#define V3_PCI_MAP_M_ADR_SIZE_1024M 0x000000A0 /* LB_BASE register bits (Local bus -> PCI) */ -#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 -#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) -#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 -#define V3_LB_BASE_M_PREFETCH (1 << 3) -#define V3_LB_BASE_M_ENABLE (1 << 0) +#define V3_LB_BASE_M_MAP_ADR 0xFFF00000 +#define V3_LB_BASE_M_SWAP (1 << 8 | 1 << 9) +#define V3_LB_BASE_M_ADR_SIZE 0x000000F0 +#define V3_LB_BASE_M_PREFETCH (1 << 3) +#define V3_LB_BASE_M_ENABLE (1 << 0) /* PCI COMMAND REGISTER bits */ -#define V3_COMMAND_M_FBB_EN (1 << 9) -#define V3_COMMAND_M_SERR_EN (1 << 8) -#define V3_COMMAND_M_PAR_EN (1 << 6) -#define V3_COMMAND_M_MASTER_EN (1 << 2) -#define V3_COMMAND_M_MEM_EN (1 << 1) -#define V3_COMMAND_M_IO_EN (1 << 0) +#define V3_COMMAND_M_FBB_EN (1 << 9) +#define V3_COMMAND_M_SERR_EN (1 << 8) +#define V3_COMMAND_M_PAR_EN (1 << 6) +#define V3_COMMAND_M_MASTER_EN (1 << 2) +#define V3_COMMAND_M_MEM_EN (1 << 1) +#define V3_COMMAND_M_IO_EN (1 << 0) #define INTEGRATOR_SC_BASE 0x11000000 #define INTEGRATOR_SC_PCIENABLE_OFFSET 0x18 @@ -280,38 +280,37 @@ /* CM registers common to all integrator/CP CMs */ #define OS_CTRL 0x0000000C -#define CMMASK_REMAP 0x00000005 /* Set remap & led */ +#define CMMASK_REMAP 0x00000005 /* Set remap & led */ #define CMMASK_RESET 0x00000008 #define OS_LOCK 0x00000014 -#define CMVAL_LOCK 0x0000A000 /* Locking value */ -#define CMMASK_LOCK 0x0000005F /* Locking value */ +#define CMVAL_LOCK 0x0000A000 /* Locking value */ +#define CMMASK_LOCK 0x0000005F /* Locking value */ #define CMVAL_UNLOCK 0x00000000 /* Any value != CM_LOCKVAL */ #define OS_SDRAM 0x00000020 #define OS_INIT 0x00000024 #define CMMASK_MAP_SIMPLE 0xFFFDFFFF /* simple mapping */ #define CMMASK_TCRAM_DISABLE 0xFFFEFFFF /* TCRAM disabled */ -#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ +#define CMMASK_LOWVEC 0x00000004 /* vectors @ 0x00000000 */ #ifdef CONFIG_CM_SPD_DETECT #define OS_SPD 0x00000100 /* The SDRAM SPD data is copied here */ #endif #if defined (CONFIG_CM10200E) || defined (CONFIG_CM10220E) -#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual - * - PLL test clock bypassed - * - bus clock ratio 2 - * - little endian - * - vectors at zero - */ +#define CMMASK_INIT_102 0x00000300 /* see CM102xx ref manual + * - PLL test clock bypassed + * - bus clock ratio 2 + * - little endian + * - vectors at zero + */ #endif /* CM1022xx */ -#define CMMASK_LE 0x00000008 /* little endian */ +#define CMMASK_LE 0x00000008 /* little endian */ #define CMMASK_CMxx6_COMMON 0x00000100 /* Common value for CMxx6 - * - divisor/ratio b00000001 - * bx - * - HCLKDIV b000 - * bxx - * - PLL BYPASS b00 - */ -#endif /* __CONFIG_H */ - + * - divisor/ratio b00000001 + * bx + * - HCLKDIV b000 + * bxx + * - PLL BYPASS b00 + */ +#endif /* __CONFIG_H */ diff --git a/include/configs/omap2420h4.h b/include/configs/omap2420h4.h index 5674e20..12252ac 100644 --- a/include/configs/omap2420h4.h +++ b/include/configs/omap2420h4.h @@ -40,7 +40,7 @@ /* Clock config to target*/ #define PRCM_CONFIG_II 1 -//#define PRCM_CONFIG_III 1 +/* #define PRCM_CONFIG_III 1 */ #include <asm/arch/omap2420.h> /* get chip and board defs */ @@ -157,7 +157,6 @@ #define NAND_WP_OFF() do {*(volatile u32 *)(0x6800A050) |= 0x00000010;} while(0) #define NAND_WP_ON() do {*(volatile u32 *)(0x6800A050) &= ~0x00000010;} while(0) - #define NAND_CTL_CLRALE(nandptr) #define NAND_CTL_SETALE(nandptr) #define NAND_CTL_CLRCLE(nandptr) @@ -165,7 +164,6 @@ #define NAND_DISABLE_CE(nand) #define NAND_ENABLE_CE(nand) - #define CONFIG_BOOTDELAY 3 #ifdef NFS_BOOT_DEFAULTS @@ -261,9 +259,6 @@ #define CFG_ENV_OFFSET ( CFG_MONITOR_BASE + CFG_MONITOR_LEN ) /* Environment after Monitor */ #endif - - - /*----------------------------------------------------------------------- * CFI FLASH driver setup */ |