diff options
| -rw-r--r-- | arch/arm/include/asm/arch-omap3/dma.h | 77 | ||||
| -rw-r--r-- | doc/README.omap3 | 18 | ||||
| -rw-r--r-- | drivers/dma/Makefile | 1 | ||||
| -rw-r--r-- | drivers/dma/omap3_dma.c | 180 |
4 files changed, 276 insertions, 0 deletions
diff --git a/arch/arm/include/asm/arch-omap3/dma.h b/arch/arm/include/asm/arch-omap3/dma.h new file mode 100644 index 0000000..ba5e057 --- /dev/null +++ b/arch/arm/include/asm/arch-omap3/dma.h @@ -0,0 +1,77 @@ +#ifndef __SDMA_H +#define __SDMA_H + +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* Functions */ +void omap3_dma_init(void); +int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, + uint32_t sze); +int omap3_dma_start_transfer(uint32_t chan); +int omap3_dma_wait_for_transfer(uint32_t chan); +int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); +int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); + +/* Register settings */ +#define CSDP_DATA_TYPE_8BIT 0x0 +#define CSDP_DATA_TYPE_16BIT 0x1 +#define CSDP_DATA_TYPE_32BIT 0x2 +#define CSDP_SRC_BURST_SINGLE (0x0 << 7) +#define CSDP_SRC_BURST_EN_16BYTES (0x1 << 7) +#define CSDP_SRC_BURST_EN_32BYTES (0x2 << 7) +#define CSDP_SRC_BURST_EN_64BYTES (0x3 << 7) +#define CSDP_DST_BURST_SINGLE (0x0 << 14) +#define CSDP_DST_BURST_EN_16BYTES (0x1 << 14) +#define CSDP_DST_BURST_EN_32BYTES (0x2 << 14) +#define CSDP_DST_BURST_EN_64BYTES (0x3 << 14) +#define CSDP_DST_ENDIAN_LOCK_ADAPT (0x0 << 18) +#define CSDP_DST_ENDIAN_LOCK_LOCK (0x1 << 18) +#define CSDP_DST_ENDIAN_LITTLE (0x0 << 19) +#define CSDP_DST_ENDIAN_BIG (0x1 << 19) +#define CSDP_SRC_ENDIAN_LOCK_ADAPT (0x0 << 20) +#define CSDP_SRC_ENDIAN_LOCK_LOCK (0x1 << 20) +#define CSDP_SRC_ENDIAN_LITTLE (0x0 << 21) +#define CSDP_SRC_ENDIAN_BIG (0x1 << 21) + +#define CCR_READ_PRIORITY_LOW (0x0 << 6) +#define CCR_READ_PRIORITY_HIGH (0x1 << 6) +#define CCR_ENABLE_DISABLED (0x0 << 7) +#define CCR_ENABLE_ENABLE (0x1 << 7) +#define CCR_SRC_AMODE_CONSTANT (0x0 << 12) +#define CCR_SRC_AMODE_POST_INC (0x1 << 12) +#define CCR_SRC_AMODE_SINGLE_IDX (0x2 << 12) +#define CCR_SRC_AMODE_DOUBLE_IDX (0x3 << 12) +#define CCR_DST_AMODE_CONSTANT (0x0 << 14) +#define CCR_DST_AMODE_POST_INC (0x1 << 14) +#define CCR_DST_AMODE_SINGLE_IDX (0x2 << 14) +#define CCR_DST_AMODE_SOUBLE_IDX (0x3 << 14) + +#define CCR_RD_ACTIVE_MASK (1 << 9) +#define CCR_WR_ACTIVE_MASK (1 << 10) + +#define CSR_TRANS_ERR (1 << 8) +#define CSR_SUPERVISOR_ERR (1 << 10) +#define CSR_MISALIGNED_ADRS_ERR (1 << 11) + +/* others */ +#define CHAN_NR_MIN 0 +#define CHAN_NR_MAX 31 + +#endif /* __SDMA_H */ diff --git a/doc/README.omap3 b/doc/README.omap3 index 1768cdd..2a3f46b 100644 --- a/doc/README.omap3 +++ b/doc/README.omap3 @@ -95,6 +95,7 @@ Interfaces ========== gpio +---- To set a bit : @@ -122,6 +123,23 @@ To read a bit : else printf("GPIO N is clear\n"); +dma +--- +void omap3_dma_init(void) + Init the DMA module +int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config); + Read config of the channel +int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config); + Write config to the channel +int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, + uint32_t sze) + Config source, destination and size of a transfer +int omap3_dma_wait_for_transfer(uint32_t chan) + Wait for a transfer to end - this hast to be called before a channel + or the data the channel transferd are used. +int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) + Read silicon Revision of the DMA module + Acknowledgements ================ diff --git a/drivers/dma/Makefile b/drivers/dma/Makefile index 9d945a0..3d9c9f1 100644 --- a/drivers/dma/Makefile +++ b/drivers/dma/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libdma.o COBJS-$(CONFIG_FSLDMAFEC) += MCD_tasksInit.o MCD_dmaApi.o MCD_tasks.o COBJS-$(CONFIG_FSL_DMA) += fsl_dma.o +COBJS-$(CONFIG_OMAP3_DMA) += omap3_dma.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/dma/omap3_dma.c b/drivers/dma/omap3_dma.c new file mode 100644 index 0000000..b98eca1 --- /dev/null +++ b/drivers/dma/omap3_dma.c @@ -0,0 +1,180 @@ +/* Copyright (C) 2011 + * Corscience GmbH & Co. KG - Simon Schwarz <schwarz@corscience.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* This is a basic implementation of the SDMA/DMA4 controller of OMAP3 + * Tested on Silicon Revision major:0x4 minor:0x0 + */ + +#include <common.h> +#include <asm/arch/cpu.h> +#include <asm/arch/omap3.h> +#include <asm/arch/dma.h> +#include <asm/io.h> +#include <asm/errno.h> + +static struct dma4 *dma4_cfg = (struct dma4 *)OMAP34XX_DMA4_BASE; +uint32_t dma_active; /* if a transfer is started the respective + bit is set for the logical channel */ + +/* Check if we have the given channel + * PARAMETERS: + * chan: Channel number + * + * RETURN of non-zero means error */ +static inline int check_channel(uint32_t chan) +{ + if (chan < CHAN_NR_MIN || chan > CHAN_NR_MAX) + return -EINVAL; + return 0; +} + +static inline void reset_irq(uint32_t chan) +{ + /* reset IRQ reason */ + writel(0x1DFE, &dma4_cfg->chan[chan].csr); + /* reset IRQ */ + writel((1 << chan), &dma4_cfg->irqstatus_l[0]); + dma_active &= ~(1 << chan); +} + +/* Set Source, Destination and Size of DMA transfer for the + * specified channel. + * PARAMETERS: + * chan: channel to use + * src: source of the transfer + * dst: destination of the transfer + * sze: Size of the transfer + * + * RETURN of non-zero means error */ +int omap3_dma_conf_transfer(uint32_t chan, uint32_t *src, uint32_t *dst, + uint32_t sze) +{ + if (check_channel(chan)) + return -EINVAL; + /* CDSA0 */ + writel((uint32_t)src, &dma4_cfg->chan[chan].cssa); + writel((uint32_t)dst, &dma4_cfg->chan[chan].cdsa); + writel(sze, &dma4_cfg->chan[chan].cen); +return 0; +} + +/* Start the DMA transfer */ +int omap3_dma_start_transfer(uint32_t chan) +{ + uint32_t val; + + if (check_channel(chan)) + return -EINVAL; + + val = readl(&dma4_cfg->chan[chan].ccr); + /* Test for channel already in use */ + if (val & CCR_ENABLE_ENABLE) + return -EBUSY; + + writel((val | CCR_ENABLE_ENABLE), &dma4_cfg->chan[chan].ccr); + dma_active |= (1 << chan); + debug("started transfer...\n"); + return 0; +} + +/* Busy-waiting for a DMA transfer + * This has to be called before another transfer is started + * PARAMETER + * chan: Channel to wait for + * + * RETURN of non-zero means error*/ +int omap3_dma_wait_for_transfer(uint32_t chan) +{ + uint32_t val; + + if (!(dma_active & (1 << chan))) { + val = readl(&dma4_cfg->irqstatus_l[0]); + if (!(val & chan)) { + debug("dma: The channel you are trying to wait for " + "was never activated - ERROR\n"); + return -1; /* channel was never active */ + } + } + + /* all irqs on line 0 */ + while (!(readl(&dma4_cfg->irqstatus_l[0]) & (1 << chan))) + asm("nop"); + + val = readl(&dma4_cfg->chan[chan].csr); + if ((val & CSR_TRANS_ERR) | (val & CSR_SUPERVISOR_ERR) | + (val & CSR_MISALIGNED_ADRS_ERR)) { + debug("err code: %X\n", val); + debug("dma: transfer error detected\n"); + reset_irq(chan); + return -1; + } + reset_irq(chan); + return 0; +} + +/* Get the revision of the DMA module + * PARAMETER + * minor: Address of minor revision to write + * major: Address of major revision to write + * + * RETURN of non-zero means error + */ +int omap3_dma_get_revision(uint32_t *minor, uint32_t *major) +{ + uint32_t val; + + /* debug information */ + val = readl(&dma4_cfg->revision); + *major = (val & 0x000000F0) >> 4; + *minor = (val & 0x0000000F); + debug("DMA Silicon revision (maj/min): 0x%X/0x%X\n", *major, *minor); + return 0; +} + +/* Initial config of omap dma + */ +void omap3_dma_init(void) +{ + dma_active = 0; + /* All interrupts on channel 0 */ + writel(0xFFFFFFFF, &dma4_cfg->irqenable_l[0]); +} + +/* set channel config to config + * + * RETURN of non-zero means error */ +int omap3_dma_conf_chan(uint32_t chan, struct dma4_chan *config) +{ + if (check_channel(chan)) + return -EINVAL; + + dma4_cfg->chan[chan] = *config; + return 0; +} + +/* get channel config to config + * + * RETURN of non-zero means error */ +int omap3_dma_get_conf_chan(uint32_t chan, struct dma4_chan *config) +{ + if (check_channel(chan)) + return -EINVAL; + *config = dma4_cfg->chan[chan]; + return 0; +} |