diff options
518 files changed, 15828 insertions, 8339 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 0c6ce2b..2cf29dd 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -486,6 +486,7 @@ Stephen Williams <steve@icarus.com> Ilya Yanok <yanok@emcraft.com> + mpc8308_p1m MPC8308 MPC8308RDB MPC8308 Roy Zang <tie-fei.zang@freescale.com> @@ -41,39 +41,39 @@ ERR_LIST="" TOTAL_CNT=0 RC=0 +# Helper funcs for parsing boards.cfg +boards_by_field() +{ + awk \ + -v field="$1" \ + -v select="$2" \ + '($1 !~ /^#/ && $field == select) { print $1 }' \ + boards.cfg +} +boards_by_arch() { boards_by_field 2 "$@" ; } +boards_by_cpu() { boards_by_field 3 "$@" ; } + ######################################################################### ## MPC5xx Systems ######################################################################### -LIST_5xx=" \ - cmi_mpc5xx \ -" +LIST_5xx="$(boards_by_cpu mpc5xx)" ######################################################################### ## MPC5xxx Systems ######################################################################### -LIST_5xxx=" \ - BC3450 \ - cm5200 \ - cpci5200 \ +LIST_5xxx="$(boards_by_cpu mpc5xxx) digsy_mtc \ EVAL5200 \ fo300 \ galaxy5200 \ icecube_5200 \ - inka4x0 \ - ipek01 \ lite5200b \ mcc200 \ - mecp5200 \ - motionpro \ - munices \ MVBC_P \ MVSMR \ - o2dnt \ pcm030 \ - pf5200 \ PM520 \ TB5200 \ Total5200 \ @@ -81,62 +81,39 @@ LIST_5xxx=" \ TQM5200 \ TQM5200_B \ TQM5200S \ - v38b \ " ######################################################################### ## MPC512x Systems ######################################################################### -LIST_512x=" \ - aria \ - mecp5123 \ +LIST_512x="$(boards_by_cpu mpc512x) mpc5121ads \ - pdm360ng \ " ######################################################################### ## MPC8xx Systems ######################################################################### -LIST_8xx=" \ + +LIST_8xx="$(boards_by_cpu mpc8xx) Adder87x \ AdderII \ ADS860 \ - AMX860 \ - c2mon \ - CCM \ - cogent_mpc8xx \ - ELPT860 \ - EP88x \ - ESTEEM192E \ - ETX094 \ FADS823 \ FADS850SAR \ FADS860T \ - FLAGADM \ FPS850L \ GEN860T \ GEN860T_SC \ - GENIETV \ - hermes \ - IAD210 \ ICU862_100MHz \ - IP860 \ IVML24 \ IVML24_128 \ IVML24_256 \ IVMS8 \ IVMS8_128 \ IVMS8_256 \ - KUP4K \ - KUP4X \ - LANTEC \ - lwmon \ - kmsupx4 \ MBX \ MBX860T \ - mgsuvd \ - MHPC \ MPC86xADS \ MPC885ADS \ NETPHONE \ @@ -145,33 +122,16 @@ LIST_8xx=" \ NETTA_ISDN \ NETVIA \ NETVIA_V2 \ - NX823 \ - pcu_e \ - QS823 \ - QS850 \ - QS860T \ - quantum \ - R360MPI \ - RBC823 \ - rmu \ - RPXClassic \ - RPXlite \ RPXlite_DW \ - RRvision \ - SM850 \ - spc1920 \ SPD823TS \ - svm_sc8xx \ SXNI855T \ TK885D \ - TOP860 \ TQM823L \ TQM823L_LCD \ TQM850L \ TQM855L \ TQM860L \ TQM885D \ - uc100 \ v37 \ " @@ -179,195 +139,98 @@ LIST_8xx=" \ ## PPC4xx Systems ######################################################################### -LIST_4xx=" \ - acadia \ +LIST_4xx="$(boards_by_cpu ppc4xx) acadia_nand \ - ADCIOP \ - alpr \ - AP1000 \ - APC405 \ - AR405 \ arches \ - ASH405 \ - bamboo \ bamboo_nand \ - bubinga \ - CANBT \ canyonlands \ canyonlands_nand \ - CMS700 \ - CPCI2DP \ CPCI405 \ CPCI4052 \ CPCI405AB \ CPCI405DT \ - CPCIISER4 \ - CRAYL1 \ - csb272 \ - csb472 \ - DASA_SIM \ devconcenter \ - dlvision \ - DP405 \ - DU405 \ - DU440 \ - ebony \ - ERIC \ fx12mm \ - G2000 \ - gdppc440etx \ glacier \ haleakala \ haleakala_nand \ hcu4 \ hcu5 \ - HH405 \ - HUB405 \ - icon \ intip \ - JSE \ - KAREF \ - katmai \ kilauea \ kilauea_nand \ - korat \ - luan \ - lwmon5 \ - makalu \ mcu25 \ - METROBOX \ - MIP405 \ MIP405T \ - ML2 \ ml507 \ ml507_flash \ - neo \ - ocotea \ OCRTC \ ORSG \ - p3p440 \ - PCI405 \ - pcs440ep \ - PIP405 \ - PLU405 \ - PMC405 \ - PMC405DE \ - PMC440 \ PPChameleonEVB \ - quad100hd \ rainier \ - redwood \ - sbc405 \ - sc3 \ sequoia \ sequoia_nand \ - t3corp \ - taihu \ - taishan \ v5fx30teval \ v5fx30teval_flash \ - VOH405 \ - VOM405 \ W7OLMC \ W7OLMG \ walnut \ - WUH405 \ xilinx-ppc440-generic \ xilinx-ppc440-generic_flash \ - XPEDITE1000 \ yellowstone \ yosemite \ - yucca \ - zeus \ " ######################################################################### ## MPC8220 Systems ######################################################################### -LIST_8220=" \ - Alaska8220 \ - Yukon8220 \ -" +LIST_8220="$(boards_by_cpu mpc8220)" ######################################################################### ## MPC824x Systems ######################################################################### -LIST_824x=" \ - A3000 \ - barco \ - BMW \ +LIST_824x="$(boards_by_cpu mpc824x) CPC45 \ - CU824 \ - debris \ eXalion \ - HIDDEN_DRAGON \ IDS8247 \ linkstation_HGLAN \ - MOUSSE \ - MUSENKI \ - MVBLUE \ - OXC \ - PN62 \ Sandpoint8240 \ Sandpoint8245 \ - sbc8240 \ - utx8245 \ " ######################################################################### ## MPC8260 Systems (includes 8250, 8255 etc.) ######################################################################### -LIST_8260=" \ - atc \ +LIST_8260="$(boards_by_cpu mpc8260) cogent_mpc8260 \ CPU86 \ CPU87 \ ep8248 \ - ep8260 \ - ep82xxm \ - gw8260 \ - hymod \ - IPHASE4539 \ ISPAN \ - mgcoge \ MPC8260ADS \ - MPC8266ADS \ MPC8272ADS \ PM826 \ PM828 \ - ppmc8260 \ Rattler8248 \ - RPXsuper \ - rsdproto \ - sacsng \ - sbc8260 \ - SCM \ TQM8260_AC \ TQM8260_AD \ TQM8260_AE \ - TQM8272 \ - ZPC1900 \ " ######################################################################### ## MPC83xx Systems (includes 8349, etc.) ######################################################################### -LIST_83xx=" \ +LIST_83xx="$(boards_by_cpu mpc83xx) caddy2 \ - kmeter1 \ - MPC8308RDB \ MPC8313ERDB_33 \ MPC8313ERDB_NAND_66 \ MPC8315ERDB \ MPC8315ERDB_NAND \ - MPC8323ERDB \ MPC832XEMDS \ MPC832XEMDS_ATM \ - MPC8349EMDS \ MPC8349ITX \ MPC8349ITXGP \ MPC8360EMDS \ @@ -375,12 +238,8 @@ LIST_83xx=" \ MPC8360ERDK_33 \ MPC8360ERDK_66 \ MPC837XEMDS \ - MPC837XERDB \ - MVBLM7 \ sbc8349 \ SIMPC8313_LP \ - TQM834x \ - ve8313 \ vme8349 \ " @@ -389,27 +248,21 @@ LIST_83xx=" \ ## MPC85xx Systems (includes 8540, 8560 etc.) ######################################################################### -LIST_85xx=" \ - ATUM8548 \ +LIST_85xx="$(boards_by_cpu mpc85xx) MPC8536DS \ MPC8536DS_NAND \ MPC8536DS_SDCARD \ MPC8536DS_SPIFLASH \ MPC8536DS_36BIT \ - MPC8540ADS \ MPC8540EVAL \ MPC8541CDS \ - MPC8544DS \ MPC8548CDS \ MPC8555CDS \ - MPC8560ADS \ - MPC8568MDS \ MPC8569MDS \ MPC8569MDS_ATM \ MPC8569MDS_NAND \ MPC8572DS \ MPC8572DS_36BIT \ - P1022DS \ P2020DS \ P2020DS_36BIT \ P1011RDB \ @@ -428,9 +281,6 @@ LIST_85xx=" \ P2020RDB_NAND \ P2020RDB_SDCARD \ P2020RDB_SPIFLASH \ - P4080DS \ - PM854 \ - PM856 \ sbc8540 \ sbc8548 \ sbc8548_PCI_33 \ @@ -438,8 +288,6 @@ LIST_85xx=" \ sbc8548_PCI_33_PCIE \ sbc8548_PCI_66_PCIE \ sbc8560 \ - socrates \ - stxgp3 \ stxssa \ TQM8540 \ TQM8541 \ @@ -448,20 +296,15 @@ LIST_85xx=" \ TQM8548_BE \ TQM8555 \ TQM8560 \ - XPEDITE5200 \ - XPEDITE5370 \ " ######################################################################### ## MPC86xx Systems ######################################################################### -LIST_86xx=" \ - MPC8610HPCD \ +LIST_86xx="$(boards_by_cpu mpc86xx) MPC8641HPCN_36BIT \ MPC8641HPCN \ - sbc8641d \ - XPEDITE5170 \ " ######################################################################### @@ -524,13 +367,7 @@ LIST_ppc=" \ ## StrongARM Systems ######################################################################### -LIST_SA=" \ - assabet \ - dnp1110 \ - gcplus \ - lart \ - shannon \ -" +LIST_SA="$(boards_by_cpu sa1100)" ######################################################################### ## ARM7 Systems @@ -706,35 +543,14 @@ LIST_at91=" \ ## Xscale Systems ######################################################################### -LIST_pxa=" \ - cerf250 \ - colibri_pxa270 \ - cradle \ - csb226 \ - delta \ - innokom \ - lubbock \ - pleb2 \ +LIST_pxa="$(boards_by_cpu pxa) polaris \ - pxa255_idp \ trizepsiv \ vpac270_nor \ vpac270_onenand \ - wepep250 \ - xaeniax \ - xm250 \ - xsengine \ - zipitz2 \ - zylonite \ " -LIST_ixp=" \ - actux1 \ - actux2 \ - actux3 \ - actux4 \ - ixdp425 \ - ixdpg425 \ +LIST_ixp="$(boards_by_cpu ixp) pdnb3 \ scpu \ " @@ -818,21 +634,15 @@ LIST_mips_el=" \ ## i386 Systems ######################################################################### -LIST_I486=" \ +LIST_x86="$(boards_by_arch i386) sc520_eNET \ " -LIST_x86=" \ - ${LIST_I486} \ -" - ######################################################################### ## Nios-II Systems ######################################################################### -LIST_nios2=" \ - PCI5441 \ - PK1C20 \ +LIST_nios2="$(boards_by_arch nios2) nios2-generic \ " @@ -840,86 +650,39 @@ LIST_nios2=" \ ## MicroBlaze Systems ######################################################################### -LIST_microblaze=" \ - microblaze-generic \ -" +LIST_microblaze="$(boards_by_arch microblaze)" ######################################################################### ## ColdFire Systems ######################################################################### -LIST_coldfire=" \ +LIST_coldfire="$(boards_by_arch m68k) astro_mcf5373l \ cobra5272 \ EB+MCF-EV123 \ EB+MCF-EV123_internal \ - idmr \ - M5208EVBE \ M52277EVB \ M5235EVB \ - M5249EVB \ - M5253DEMO \ - M5253EVBE \ - M5271EVB \ - M5272C3 \ - M5275EVB \ - M5282EVB \ - M53017EVB \ M5329AFEE \ M5373EVB \ M54451EVB \ M54455EVB \ M5475AFE \ M5485AFE \ - TASREG \ " ######################################################################### ## AVR32 Systems ######################################################################### -LIST_avr32=" \ - atstk1002 \ - atstk1003 \ - atstk1004 \ - atstk1006 \ - atngw100 \ - favr-32-ezkit \ - hammerhead \ - mimc200 \ -" +LIST_avr32="$(boards_by_arch avr32)" ######################################################################### ## Blackfin Systems ######################################################################### -LIST_blackfin=" \ - bf518f-ezbrd \ - bf526-ezbrd \ - bf527-ad7160-eval \ - bf527-ezkit \ - bf527-ezkit-v2 \ - bf533-ezkit \ - bf533-stamp \ - bf537-minotaur \ - bf537-pnav \ - bf537-srv1 \ - bf537-stamp \ - bf538f-ezkit \ - bf548-ezkit \ - bf561-acvilon \ - bf561-ezkit \ - blackstamp \ - cm-bf527 \ - cm-bf533 \ - cm-bf537e \ - cm-bf537u \ - cm-bf548 \ - cm-bf561 \ - ibf-dsp561 \ - ip04 \ - tcm-bf518 \ - tcm-bf537 \ +LIST_blackfin="$(boards_by_arch blackfin) + bf527-ezkit-v2 " ######################################################################### @@ -956,12 +719,7 @@ LIST_sh=" \ ## SPARC Systems ######################################################################### -LIST_sparc="gr_xc3s_1500 gr_cpci_ax2000 gr_ep2s60 grsim grsim_leon2" - -#----------------------------------------------------------------------- - -#----- for now, just run PowerPC by default ----- -[ $# = 0 ] && set $LIST_powerpc +LIST_sparc="$(boards_by_arch sparc)" #----------------------------------------------------------------------- @@ -969,7 +727,7 @@ build_target() { target=$1 ${MAKE} distclean >/dev/null - ${MAKE} ${target}_config + ${MAKE} -s ${target}_config ${MAKE} ${JOBS} all 2>&1 >${LOG_DIR}/$target.MAKELOG \ | tee ${LOG_DIR}/$target.ERR @@ -991,6 +749,22 @@ build_target() { ${CROSS_COMPILE}size ${BUILD_DIR}/u-boot \ | tee -a ${LOG_DIR}/$target.MAKELOG } +build_targets() { + for t in "$@" ; do + # If a LIST_xxx var exists, use it. But avoid variable + # expansion in the eval when a board name contains certain + # characters that the shell interprets. + case ${t} in + *[-+=]*) list= ;; + *) list=$(eval echo '${LIST_'$t'}') ;; + esac + if [ -n "${list}" ] ; then + build_targets ${list} + else + build_target ${t} + fi + done +} #----------------------------------------------------------------------- @@ -1007,27 +781,8 @@ print_stats() { } #----------------------------------------------------------------------- -for arg in $@ -do - case "$arg" in - arm|SA|ARM7|ARM9|ARM10|ARM11|ARMV7|at91|ixp|pxa \ - |avr32 \ - |blackfin \ - |coldfire \ - |microblaze \ - |mips|mips_el \ - |nios2 \ - |ppc|powerpc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ - |sh|sh2|sh3|sh4 \ - |sparc \ - |x86|I486 \ - ) - for target in `eval echo '$LIST_'${arg}` - do - build_target ${target} - done - ;; - *) build_target ${arg} - ;; - esac -done + +#----- for now, just run PowerPC by default ----- +[ $# = 0 ] && set -- powerpc + +build_targets "$@" @@ -404,14 +404,8 @@ $(TIMESTAMP_FILE): @LC_ALL=C date +'#define U_BOOT_DATE "%b %d %C%y"' > $@ @LC_ALL=C date +'#define U_BOOT_TIME "%T"' >> $@ -gdbtools: - $(MAKE) -C tools/gdb all || exit 1 - updater: - $(MAKE) -C tools/updater all || exit 1 - -env: - $(MAKE) -C tools/env all MTD_VERSION=${MTD_VERSION} || exit 1 + $(MAKE) -C tools/updater all # Explicitly make _depend in subdirs containing multiple targets to prevent # parallel sub-makes creating .depend files simultaneously. @@ -466,17 +460,22 @@ $(obj)include/autoconf.mk: $(obj)include/config.h else # !config.mk all $(obj)u-boot.hex $(obj)u-boot.srec $(obj)u-boot.bin \ $(obj)u-boot.img $(obj)u-boot.dis $(obj)u-boot \ -$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) gdbtools \ -updater env depend dep tags ctags etags cscope $(obj)System.map: +$(filter-out tools,$(SUBDIRS)) $(TIMESTAMP_FILE) $(VERSION_FILE) \ +updater depend dep tags ctags etags cscope $(obj)System.map: @echo "System not configured - see README" >&2 @ exit 1 tools: - $(MAKE) -C tools -tools-all: - $(MAKE) -C tools HOST_TOOLS_ALL=y + $(MAKE) -C $@ all endif # config.mk +easylogo env gdb: + $(MAKE) -C tools/$@ all MTD_VERSION=${MTD_VERSION} +gdbtools: gdb + +tools-all: easylogo env gdb + $(MAKE) -C tools HOST_TOOLS_ALL=y + .PHONY : CHANGELOG CHANGELOG: git log --no-merges U-Boot-1_1_5.. | \ @@ -494,8 +493,9 @@ unconfig: %_config:: unconfig @$(MKCONFIG) -A $(@:_config=) -##%: %_config -## $(MAKE) +sinclude .boards.depend +.boards.depend: boards.cfg + awk '(NF && $$1 !~ /^#/) { print $$1 ": " $$1 "_config; $$(MAKE)" }' $< > $@ # # Functions to generate common board directory names @@ -2475,7 +2475,7 @@ clean: | xargs rm -f clobber: clean - @find $(OBJTREE) -type f \( -name .depend \ + @find $(OBJTREE) -type f \( -name '*.depend' \ -o -name '*.srec' -o -name '*.bin' -o -name u-boot.img \) \ -print0 \ | xargs -0 rm -f @@ -536,25 +536,6 @@ The following options need to be configured: must be defined, to setup the maximum idle timeout for the SMC. -- Interrupt driven serial port input: - CONFIG_SERIAL_SOFTWARE_FIFO - - PPC405GP only. - Use an interrupt handler for receiving data on the - serial port. It also enables using hardware handshake - (RTS/CTS) and UART's built-in FIFO. Set the number of - bytes the interrupt driven input buffer should have. - - Leave undefined to disable this feature, including - disable the buffer and hardware handshake. - -- Console UART Number: - CONFIG_UART1_CONSOLE - - AMCC PPC4xx only. - If defined internal UART1 (and not UART0) is used - as default U-Boot console. - - Boot Delay: CONFIG_BOOTDELAY - in seconds Delay before automatically booting the default image; set to -1 to disable autoboot. @@ -2368,6 +2349,14 @@ Configuration Settings: on high Ethernet traffic. Defaults to 4 if not defined. +- CONFIG_ENV_MAX_ENTRIES + + Maximum number of entries in the hash table that is used + internally to store the environment settings. The default + setting is supposed to be generous and should work in most + cases. This setting can be used to tune behaviour; see + lib/hashtable.c for details. + The following definitions that deal with the placement and management of environment data (variable area); in general, we support the following configurations: diff --git a/arch/arm/config.mk b/arch/arm/config.mk index e10dafc..6923f6d 100644 --- a/arch/arm/config.mk +++ b/arch/arm/config.mk @@ -33,6 +33,14 @@ STANDALONE_LOAD_ADDR = 0xc100000 endif endif +ifndef CONFIG_SYS_ARM_WITHOUT_RELOC +# needed for relocation +PLATFORM_RELFLAGS += -fPIC +endif + +ifdef CONFIG_SYS_ARM_WITHOUT_RELOC +PLATFORM_CPPFLAGS += -DCONFIG_SYS_ARM_WITHOUT_RELOC +endif PLATFORM_CPPFLAGS += -DCONFIG_ARM -D__ARM__ # Explicitly specifiy 32-bit ARM ISA since toolchain default can be -mthumb: diff --git a/arch/arm/cpu/arm1136/start.S b/arch/arm/cpu/arm1136/start.S index 41eb82d..8b63192 100644 --- a/arch/arm/cpu/arm1136/start.S +++ b/arch/arm/cpu/arm1136/start.S @@ -85,12 +85,15 @@ _end_vect: ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -103,6 +106,32 @@ _bss_start: _bss_end: .word _end +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end +#endif + #ifdef CONFIG_USE_IRQ /* IRQ stack memory (calculated at run-time) */ .globl IRQ_STACK_START @@ -115,6 +144,164 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de +#endif + +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +#ifdef CONFIG_OMAP2420H4 + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start /* r0 <- current position of code */ + add r0, r0, #4 /* skip reset vector */ + mov r2, #64 /* r2 <- size to copy */ + add r2, r0, r2 /* r2 <- source end address */ + mov r1, #SRAM_OFFSET0 /* build vect addr */ + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3-r10} /* copy from source address [r0] */ + stmia r1!, {r3-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end address [r2] */ + bne next /* loop until equal */ + bl cpy_clk_code /* put dpll adjust code behind vectors */ +#endif + /* the mask ROM code should have PLL and others stable */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + +#ifdef CONFIG_NAND_SPL + bl nand_boot +#else +#ifdef CONFIG_ONENAND_IPL + bl start_oneboot +#else + bl board_init_f +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif /* #ifndef CONFIG_PRELOADER */ + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot + +_nand_boot: .word nand_boot +#else +jump_2_ram: + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code */ @@ -211,6 +398,8 @@ _start_armboot: .word start_armboot #endif /* CONFIG_ONENAND_IPL */ #endif /* CONFIG_NAND_SPL */ +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ + /* ************************************************************************* * @@ -295,9 +484,13 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort stack +#else ldr r2, _armboot_start sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#endif ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -328,9 +521,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter in banked mode) +#else ldr r13, _armboot_start @ setup our mode stack (enter in banked mode) sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move to reserved a couple spots for abort stack +#endif str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr @@ -346,9 +543,13 @@ cpu_init_crit: .macro get_bad_stack_swi sub r13, r13, #4 @ space on current stack for scratch reg. str r0, [r13] @ save R0's value. +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + ldr r0, IRQ_STACK_START_IN @ get data regions start +#else ldr r0, _armboot_start @ get data regions start sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ move past gbl and a couple spots for abort stack +#endif str lr, [r0] @ save caller lr in position 0 of saved stack mrs r0, spsr @ get the spsr str lr, [r0, #4] @ save spsr in position 1 of saved stack @@ -439,6 +640,11 @@ fiq: .align 5 .global arm1136_cache_flush arm1136_cache_flush: +#if !defined(CONFIG_SYS_NO_ICACHE) mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache +#endif +#if !defined(CONFIG_SYS_NO_DCACHE) + mcr p15, 0, r1, c7, c14, 0 @ invalidate D cache +#endif mov pc, lr @ back to caller #endif /* CONFIG_PRELOADER */ diff --git a/arch/arm/cpu/arm1136/u-boot.lds b/arch/arm/cpu/arm1136/u-boot.lds index e7eefc9..1db4b49 100644 --- a/arch/arm/cpu/arm1136/u-boot.lds +++ b/arch/arm/cpu/arm1136/u-boot.lds @@ -47,11 +47,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm1176/start.S b/arch/arm/cpu/arm1176/start.S index f98a7aa..e5e7913 100644 --- a/arch/arm/cpu/arm1176/start.S +++ b/arch/arm/cpu/arm1176/start.S @@ -95,6 +95,7 @@ _end_vect: ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE @@ -106,9 +107,11 @@ _TEXT_BASE: _TEXT_PHY_BASE: .word CONFIG_SYS_PHY_UBOOT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -121,6 +124,275 @@ _bss_start: _bss_end: .word _end +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x3f + orr r0, r0, #0xd3 + msr cpsr, r0 + +/* + ************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + ************************************************************************* + */ + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +cpu_init_crit: + /* + * When booting from NAND - it has definitely been a reset, so, no need + * to flush caches and disable the MMU + */ +#ifndef CONFIG_NAND_SPL + /* + * flush v4 I/D caches + */ + mov r0, #0 + mcr p15, 0, r0, c7, c7, 0 /* flush v3/v4 cache */ + mcr p15, 0, r0, c8, c7, 0 /* flush v4 TLB */ + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002300 @ clear bits 13, 9:8 (--V- --RS) + bic r0, r0, #0x00000087 @ clear bits 7, 2:0 (B--- -CAM) + orr r0, r0, #0x00000002 @ set bit 2 (A) Align + orr r0, r0, #0x00001000 @ set bit 12 (I) I-Cache + + /* Prepare to disable the MMU */ + adr r2, mmu_disable_phys + sub r2, r2, #(CONFIG_SYS_PHY_UBOOT_BASE - TEXT_BASE) + b mmu_disable + + .align 5 + /* Run in a single cache-line */ +mmu_disable: + mcr p15, 0, r0, c1, c0, 0 + nop + nop + mov pc, r2 +mmu_disable_phys: + +#ifdef CONFIG_DISABLE_TCM + /* + * Disable the TCMs + */ + mrc p15, 0, r0, c0, c0, 2 /* Return TCM details */ + cmp r0, #0 + beq skip_tcmdisable + mov r1, #0 + mov r2, #1 + tst r0, r2 + mcrne p15, 0, r1, c9, c1, 1 /* Disable Instruction TCM if present*/ + tst r0, r2, LSL #16 + mcrne p15, 0, r1, c9, c1, 0 /* Disable Data TCM if present*/ +skip_tcmdisable: +#endif +#endif + +#ifdef CONFIG_PERIPORT_REMAP + /* Peri port setup */ + ldr r0, =CONFIG_PERIPORT_BASE + orr r0, r0, #CONFIG_PERIPORT_SIZE + mcr p15,0,r0,c15,c2,4 +#endif + + /* + * Go setup Memory and board specific bits prior to relocation. + */ + bl lowlevel_init /* go setup pll,mux,memory */ + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +#ifdef CONFIG_ENABLE_MMU +enable_mmu: + /* enable domain access */ + ldr r5, =0x0000ffff + mcr p15, 0, r5, c3, c0, 0 /* load domain access register */ + + /* Set the TTB register */ + ldr r0, _mmu_table_base + ldr r1, =CONFIG_SYS_PHY_UBOOT_BASE + ldr r2, =0xfff00000 + bic r0, r0, r2 + orr r1, r0, r1 + mcr p15, 0, r1, c2, c0, 0 + + /* Enable the MMU */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #1 /* Set CR_M to enable MMU */ + + /* Prepare to enable the MMU */ + adr r1, skip_hw_init + and r1, r1, #0x3fc + ldr r2, _TEXT_BASE + ldr r3, =0xfff00000 + and r2, r2, r3 + orr r2, r2, r1 + b mmu_enable + + .align 5 + /* Run in a single cache-line */ +mmu_enable: + + mcr p15, 0, r0, c1, c0, 0 + nop + nop + mov pc, r2 +skip_hw_init: +#endif + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot + +_nand_boot: .word nand_boot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ + /* * the actual reset code */ @@ -299,6 +571,8 @@ _start_armboot: /* .word nand_boot*/ #endif +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ + #ifdef CONFIG_ENABLE_MMU _mmu_table_base: .word mmu_table @@ -385,10 +659,14 @@ phy_last_jump: /* Save user registers (now in svc mode) r0-r12 */ stmia sp, {r0 - r12} +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) /* set base 2 words into abort stack */ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) +#else + ldr r2, IRQ_STACK_START_IN +#endif /* get values for "aborted" pc and cpsr (into parm regs) */ ldmia r2, {r2 - r3} /* grab pointer to old stack */ @@ -403,12 +681,16 @@ phy_last_jump: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) /* setup our mode stack (enter in banked mode) */ ldr r13, _armboot_start /* move past malloc pool */ sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) /* move to reserved a couple spots for abort stack */ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif /* save caller lr in position 0 of saved stack */ str lr, [r13] @@ -433,12 +715,16 @@ phy_last_jump: sub r13, r13, #4 /* save R0's value. */ str r0, [r13] +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) /* get data regions start */ ldr r0, _armboot_start /* move past malloc pool */ sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) /* move past gbl and a couple spots for abort stack */ sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif /* save caller lr in position 0 of saved stack */ str lr, [r0] /* get the spsr */ diff --git a/arch/arm/cpu/arm1176/u-boot.lds b/arch/arm/cpu/arm1176/u-boot.lds index 8969587..fa640ee 100644 --- a/arch/arm/cpu/arm1176/u-boot.lds +++ b/arch/arm/cpu/arm1176/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm720t/start.S b/arch/arm/cpu/arm720t/start.S index d6f2c16..0f5f6c4 100644 --- a/arch/arm/cpu/arm720t/start.S +++ b/arch/arm/cpu/arm720t/start.S @@ -75,12 +75,15 @@ _fiq: .word fiq ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -105,6 +108,163 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifdef CONFIG_LPC2292 + bl lowlevel_init +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code @@ -188,6 +348,8 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ + /* ************************************************************************* * @@ -444,9 +606,13 @@ lock_loop: stmia sp, {r0 - r12} @ Calling r0-r12 add r8, sp, #S_PC +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -477,9 +643,13 @@ lock_loop: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/arm720t/u-boot.lds b/arch/arm/cpu/arm720t/u-boot.lds index c975fc3..4a0bc70 100644 --- a/arch/arm/cpu/arm720t/u-boot.lds +++ b/arch/arm/cpu/arm720t/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm920t/start.S b/arch/arm/cpu/arm920t/start.S index e532f55..a079bb2 100644 --- a/arch/arm/cpu/arm920t/start.S +++ b/arch/arm/cpu/arm920t/start.S @@ -70,12 +70,15 @@ _fiq: .word fiq ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -100,6 +103,35 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end /* * the actual start code @@ -176,6 +208,189 @@ copyex: bl cpu_init_crit #endif +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot + +_nand_boot: .word nand_boot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ +/* + * the actual start code + */ + +start_code: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr, r0 + + bl coloured_LED_init + bl red_LED_on + +#if defined(CONFIG_AT91RM9200DK) || defined(CONFIG_AT91RM9200EK) + /* + * relocate exception table + */ + ldr r0, =_start + ldr r1, =0x0 + mov r2, #16 +copyex: + subs r2, r2, #1 + ldr r3, [r0], #4 + str r3, [r1], #4 + bne copyex +#endif + +#ifdef CONFIG_S3C24X0 + /* turn off the watchdog */ + +# if defined(CONFIG_S3C2400) +# define pWTCON 0x15300000 +# define INTMSK 0x14400008 /* Interupt-Controller base addresses */ +# define CLKDIVN 0x14800014 /* clock divisor register */ +#else +# define pWTCON 0x53000000 +# define INTMSK 0x4A000008 /* Interupt-Controller base addresses */ +# define INTSUBMSK 0x4A00001C +# define CLKDIVN 0x4C000014 /* clock divisor register */ +# endif + + ldr r0, =pWTCON + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =INTMSK + str r1, [r0] +# if defined(CONFIG_S3C2410) + ldr r1, =0x3ff + ldr r0, =INTSUBMSK + str r1, [r0] +# endif + + /* FCLK:HCLK:PCLK = 1:2:4 */ + /* default FCLK is 120 MHz ! */ + ldr r0, =CLKDIVN + mov r1, #3 + str r1, [r0] +#endif /* CONFIG_S3C24X0 */ + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -219,7 +434,7 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot _start_armboot: .word start_armboot - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -309,11 +524,15 @@ cpu_init_crit: .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE) sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) /* set base 2 words into abort stack */ sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -345,11 +564,15 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE) sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) /* reserve a couple spots in abort stack */ sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/arm920t/u-boot.lds b/arch/arm/cpu/arm920t/u-boot.lds index a7decfc..6985434 100644 --- a/arch/arm/cpu/arm920t/u-boot.lds +++ b/arch/arm/cpu/arm920t/u-boot.lds @@ -47,11 +47,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm925t/start.S b/arch/arm/cpu/arm925t/start.S index 346615e..c0a856d 100644 --- a/arch/arm/cpu/arm925t/start.S +++ b/arch/arm/cpu/arm925t/start.S @@ -81,12 +81,15 @@ _fiq: .word fiq ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -111,7 +114,198 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * Set up 925T mode + */ + mov r1, #0x81 /* Set ARM925T configuration. */ + mcr p15, 0, r1, c15, c1, 0 /* Write ARM925T configuration register. */ + + /* + * turn off the watchdog, unlock/diable sequence + */ + mov r1, #0xF5 + ldr r0, =WDTIM_MODE + strh r1, [r0] + mov r1, #0xA0 + strh r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTMR - default + */ + mov r1, #0xffffffff + ldr r0, =REG_IHL1_MIR + str r1, [r0] + ldr r0, =REG_IHL2_MIR + str r1, [r0] + + /* + * wait for dpll to lock + */ + ldr r0, =CK_DPLL1 + mov r1, #0x10 + strh r1, [r0] +poll1: + ldrh r1, [r0] + ands r1, r1, #0x01 + beq poll1 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot + +_nand_boot: .word nand_boot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code */ @@ -211,7 +405,7 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot _start_armboot: .word start_armboot - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -295,9 +489,13 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current user stack stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r3} @ get values for "aborted" pc and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -328,9 +526,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN +#endif str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/arch/arm/cpu/arm925t/u-boot.lds b/arch/arm/cpu/arm925t/u-boot.lds index e21d6dc..1c4e9bc 100644 --- a/arch/arm/cpu/arm925t/u-boot.lds +++ b/arch/arm/cpu/arm925t/u-boot.lds @@ -42,11 +42,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm926ejs/orion5x/dram.c b/arch/arm/cpu/arm926ejs/orion5x/dram.c index c719798..c5c8ab7 100644 --- a/arch/arm/cpu/arm926ejs/orion5x/dram.c +++ b/arch/arm/cpu/arm926ejs/orion5x/dram.c @@ -49,7 +49,7 @@ u32 orion5x_sdram_bar(enum memory_bank bank) result = winregs[bank].base; return result; } - +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { int i; @@ -62,3 +62,25 @@ int dram_init(void) } return 0; } +#else +int dram_init (void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (volatile long *) orion5x_sdram_bar(0), + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize (void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = orion5x_sdram_bar(i); + gd->bd->bi_dram[i].size = get_ram_size( + (volatile long *) (gd->bd->bi_dram[i].start), + CONFIG_MAX_RAM_BANK_SIZE); + } +} +#endif diff --git a/arch/arm/cpu/arm926ejs/start.S b/arch/arm/cpu/arm926ejs/start.S index cf40ce1..16ee972 100644 --- a/arch/arm/cpu/arm926ejs/start.S +++ b/arch/arm/cpu/arm926ejs/start.S @@ -114,12 +114,15 @@ _fiq: ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -144,6 +147,35 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end /* * the actual reset code @@ -166,6 +198,135 @@ reset: bl cpu_init_crit #endif +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot + +_nand_boot: .word nand_boot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + #ifndef CONFIG_SKIP_RELOCATE_UBOOT relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ @@ -221,7 +382,7 @@ _start_armboot: #else .word start_armboot #endif /* CONFIG_NAND_SPL */ - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -307,10 +468,13 @@ cpu_init_crit: @ carve out a frame on current user stack sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 - +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -342,9 +506,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/arch/arm/cpu/arm926ejs/u-boot.lds b/arch/arm/cpu/arm926ejs/u-boot.lds index ecbc58c..02eb8ca 100644 --- a/arch/arm/cpu/arm926ejs/u-boot.lds +++ b/arch/arm/cpu/arm926ejs/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm946es/start.S b/arch/arm/cpu/arm946es/start.S index 8844d44..18ed0b2 100644 --- a/arch/arm/cpu/arm946es/start.S +++ b/arch/arm/cpu/arm946es/start.S @@ -85,12 +85,15 @@ _fiq: ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -115,7 +118,162 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_NAND_SPL + ldr pc, _nand_boot +_nand_boot: .word nand_boot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code */ @@ -179,7 +337,7 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -266,9 +424,13 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -300,9 +462,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/arch/arm/cpu/arm946es/u-boot.lds b/arch/arm/cpu/arm946es/u-boot.lds index fef21c7..6535963 100644 --- a/arch/arm/cpu/arm946es/u-boot.lds +++ b/arch/arm/cpu/arm946es/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/arm_intcm/start.S b/arch/arm/cpu/arm_intcm/start.S index 328bae0..b39fdc6 100644 --- a/arch/arm/cpu/arm_intcm/start.S +++ b/arch/arm/cpu/arm_intcm/start.S @@ -83,12 +83,15 @@ _fiq: ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE /* address of _start in the linked image */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -113,6 +116,159 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code @@ -178,6 +334,8 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ + /* ************************************************************************* * @@ -242,9 +400,13 @@ cpu_init_crit: sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Save user registers (now in svc mode) r0-r12 +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif @ get values for "aborted" pc and cpsr (into parm regs) ldmia r2, {r2 - r3} add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -276,9 +438,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr in position 0 of saved stack mrs lr, spsr @ get the spsr diff --git a/arch/arm/cpu/arm_intcm/u-boot.lds b/arch/arm/cpu/arm_intcm/u-boot.lds index 4ed7d89..242c7ec 100644 --- a/arch/arm/cpu/arm_intcm/u-boot.lds +++ b/arch/arm/cpu/arm_intcm/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/armv7/mx51/u-boot.lds b/arch/arm/cpu/armv7/mx51/u-boot.lds index d66434c..55d6599 100644 --- a/arch/arm/cpu/armv7/mx51/u-boot.lds +++ b/arch/arm/cpu/armv7/mx51/u-boot.lds @@ -44,10 +44,22 @@ SECTIONS .rodata : { *(.rodata) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; diff --git a/arch/arm/cpu/armv7/omap3/cache.S b/arch/arm/cpu/armv7/omap3/cache.S index fdc1666..cda87ba 100644 --- a/arch/arm/cpu/armv7/omap3/cache.S +++ b/arch/arm/cpu/armv7/omap3/cache.S @@ -181,3 +181,83 @@ setup_auxcr: orrlt r0, r0, #1 << 27 .word 0xE1600070 @ SMC bx lr + +.align 5 +.global v7_flush_dcache_all +.global v7_flush_cache_all + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r7, r9-r11 (r6 only in Thumb mode) + * + * - mm - mm_struct describing address space + */ +v7_flush_dcache_all: +# dmb @ ensure ordering with previous memory accesses + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished @ if loc is 0, then no need to clean + mov r10, #0 @ start clean at cache level 0 +loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache level + mov r1, r0, lsr r2 @ extract cache type bits from clidr + and r1, r1, #7 @ mask of the bits for current cache only + cmp r1, #2 @ see what cache we have at this level + blt skip @ skip if no cache, or just i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the way size + clz r5, r4 @ find bit position of way size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the index size +loop2: + mov r9, r4 @ create working copy of max way size +loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c14, 2 @ clean & invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge loop3 + subs r7, r7, #1 @ decrement the index + bge loop2 +skip: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt loop1 +finished: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level in cssr +# dsb + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mov pc, lr + +/* + * v7_flush_cache_all() + * + * Flush the entire cache system. + * The data cache flush is now achieved using atomic clean / invalidates + * working outwards from L1 cache. This is done using Set/Way based cache + * maintainance instructions. + * The instruction cache can still be invalidated back to the point of + * unification in a single instruction. + * + */ +v7_flush_cache_all: + stmfd sp!, {r0-r7, r9-r11, lr} + bl v7_flush_dcache_all + mov r0, #0 + mcr p15, 0, r0, c7, c5, 0 @ I+BTB cache invalidate + ldmfd sp!, {r0-r7, r9-r11, lr} + mov pc, lr diff --git a/arch/arm/cpu/armv7/omap3/emif4.c b/arch/arm/cpu/armv7/omap3/emif4.c index fae5b11..da2cd90 100644 --- a/arch/arm/cpu/armv7/omap3/emif4.c +++ b/arch/arm/cpu/armv7/omap3/emif4.c @@ -136,6 +136,7 @@ void do_emif4_init(void) * dram_init - * - Sets uboots idea of sdram size */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -157,6 +158,39 @@ int dram_init(void) return 0; } +#else +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) + size1 = get_sdr_cs_size(CS1); + + gd->ram_size = size0 + size1; + return 0; +} + +void dram_init_banksize (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} +#endif /* * mem_init() - diff --git a/arch/arm/cpu/armv7/omap3/sdrc.c b/arch/arm/cpu/armv7/omap3/sdrc.c index 8905224..2719bb5 100644 --- a/arch/arm/cpu/armv7/omap3/sdrc.c +++ b/arch/arm/cpu/armv7/omap3/sdrc.c @@ -163,6 +163,7 @@ void do_sdrc_init(u32 cs, u32 early) * dram_init - * - Sets uboots idea of sdram size */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { DECLARE_GLOBAL_DATA_PTR; @@ -188,6 +189,43 @@ int dram_init(void) return 0; } +#else +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + /* + * If a second bank of DDR is attached to CS1 this is + * where it can be started. Early init code will init + * memory on CS0. + */ + if ((sysinfo.mtype == DDR_COMBO) || (sysinfo.mtype == DDR_STACKED)) { + do_sdrc_init(CS1, NOT_EARLY); + make_cs1_contiguous(); + + size1 = get_sdr_cs_size(CS1); + } + gd->ram_size = size0 + size1; + + return 0; +} + +void dram_init_banksize (void) +{ + DECLARE_GLOBAL_DATA_PTR; + unsigned int size0 = 0, size1 = 0; + + size0 = get_sdr_cs_size(CS0); + size1 = get_sdr_cs_size(CS1); + + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = size0; + gd->bd->bi_dram[1].start = PHYS_SDRAM_1 + get_sdr_cs_offset(CS1); + gd->bd->bi_dram[1].size = size1; +} +#endif /* * mem_init - diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S index 1e0a150..f411c0f 100644 --- a/arch/arm/cpu/armv7/start.S +++ b/arch/arm/cpu/armv7/start.S @@ -65,12 +65,15 @@ _end_vect: * *************************************************************************/ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -95,6 +98,176 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr,r0 + +#if (CONFIG_OMAP34XX) + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start @ r0 <- current position of code + add r0, r0, #4 @ skip reset vector + mov r2, #64 @ r2 <- size to copy + add r2, r0, r2 @ r2 <- source end address + mov r1, #SRAM_OFFSET0 @ build vect addr + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3 - r10} @ copy from source address [r0] + stmia r1!, {r3 - r10} @ copy to target address [r1] + cmp r0, r2 @ until source end address [r2] + bne next @ loop until equal */ +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) + /* No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + bl cpy_clk_code @ put dpll adjust code behind vectors +#endif /* NAND Boot */ +#endif + /* the mask ROM code should have PLL and others stable */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 +#ifndef CONFIG_PRELOADER + beq jump_2_ram +#endif + +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop + +clear_bss: + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif /* #ifndef CONFIG_PRELOADER */ +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +jump_2_ram: + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code */ @@ -180,7 +353,7 @@ clbss_l: ldr pc, _start_armboot @ jump to C code _start_armboot: .word start_armboot - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /************************************************************************* * @@ -263,11 +436,14 @@ cpu_init_crit: @ user stack stmia sp, {r0 - r12} @ Save user registers (now in @ svc mode) r0-r12 - +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort +#else + ldr r2, IRQ_STACK_START_IN @ set base 2 words into abort @ stack +#endif ldmia r2, {r2 - r3} @ get values for "aborted" pc @ and cpsr (into parm regs) add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack @@ -303,11 +479,14 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack (enter - @ in banked mode) sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple - @ spots for abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack (enter + @ in banked mode) +#endif str lr, [r13] @ save caller lr in position 0 @ of saved stack @@ -328,10 +507,14 @@ cpu_init_crit: sub r13, r13, #4 @ space on current stack for @ scratch reg. str r0, [r13] @ save R0's value. +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r0, _armboot_start @ get data regions start sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple +#else + ldr r0, IRQ_STACK_START_IN @ get data regions start @ spots for abort stack +#endif str lr, [r0] @ save caller lr in position 0 @ of saved stack mrs r0, spsr @ get the spsr diff --git a/arch/arm/cpu/armv7/u-boot.lds b/arch/arm/cpu/armv7/u-boot.lds index 9e5b5a9..d4fd3fc 100644 --- a/arch/arm/cpu/armv7/u-boot.lds +++ b/arch/arm/cpu/armv7/u-boot.lds @@ -42,10 +42,22 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/ixp/start.S b/arch/arm/cpu/ixp/start.S index 6efe333..b2c8255 100644 --- a/arch/arm/cpu/ixp/start.S +++ b/arch/arm/cpu/ixp/start.S @@ -93,12 +93,15 @@ _fiq: .word fiq * - jump to second stage */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -123,6 +126,274 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* disable mmu, set big-endian */ + mov r0, #0xf8 + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + /* invalidate I & D caches & BTB */ + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* drain write and fill buffers */ + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + /* disable write buffer coalescing */ + mrc p15, 0, r0, c1, c0, 1 + orr r0, r0, #1 + mcr p15, 0, r0, c1, c0, 1 + CPWAIT r0 + + /* set EXP CS0 to the optimum timing */ + ldr r1, =CONFIG_SYS_EXP_CS0 + ldr r2, =IXP425_EXP_CS0 + str r1, [r2] + + /* make sure flash is visible at 0 */ +#if 0 + ldr r2, =IXP425_EXP_CFG0 + ldr r1, [r2] + orr r1, r1, #0x80000000 + str r1, [r2] +#endif + mov r1, #CONFIG_SYS_SDR_CONFIG + ldr r2, =IXP425_SDR_CONFIG + str r1, [r2] + + /* disable refresh cycles */ + mov r1, #0 + ldr r3, =IXP425_SDR_REFRESH + str r1, [r3] + + /* send nop command */ + mov r1, #3 + ldr r4, =IXP425_SDR_IR + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* set SDRAM internal refresh val */ + ldr r1, =CONFIG_SYS_SDRAM_REFRESH_CNT + str r1, [r3] + DELAY_FOR 0x4000, r0 + + /* send precharge-all command to close all open banks */ + mov r1, #2 + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* provide 8 auto-refresh cycles */ + mov r1, #4 + mov r5, #8 +111: str r1, [r4] + DELAY_FOR 0x100, r0 + subs r5, r5, #1 + bne 111b + + /* set mode register in sdram */ + mov r1, #CONFIG_SYS_SDR_MODE_CONFIG + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* send normal operation command */ + mov r1, #6 + str r1, [r4] + DELAY_FOR 0x4000, r0 + + /* copy */ + mov r0, #0 + mov r4, r0 + add r2, r0, #CONFIG_SYS_MONITOR_LEN + mov r1, #0x10000000 + mov r5, r1 + + 30: + ldr r3, [r0], #4 + str r3, [r1], #4 + cmp r0, r2 + bne 30b + + /* invalidate I & D caches & BTB */ + mcr p15, 0, r0, c7, c7, 0 + CPWAIT r0 + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* drain write and fill buffers */ + mcr p15, 0, r0, c7, c10, 4 + CPWAIT r0 + + /* move flash to 0x50000000 */ + ldr r2, =IXP425_EXP_CFG0 + ldr r1, [r2] + bic r1, r1, #0x80000000 + str r1, [r2] + + nop + nop + nop + nop + nop + nop + + /* invalidate I & Data TLB */ + mcr p15, 0, r0, c8, c7, 0 + CPWAIT r0 + + /* enable I cache */ + mrc p15, 0, r0, c1, c0, 0 + orr r0, r0, #MMU_Control_I + mcr p15, 0, r0, c1, c0, 0 + CPWAIT r0 + + mrs r0,cpsr /* set the cpu to SVC32 mode */ + bic r0,r0,#0x1f /* (superviser mode, M=10011) */ + orr r0,r0,#0x13 + msr cpsr,r0 + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /****************************************************************************/ /* */ /* the actual reset code */ @@ -304,6 +575,7 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot _start_armboot: .word start_armboot +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /****************************************************************************/ @@ -345,9 +617,13 @@ _start_armboot: .word start_armboot stmia sp, {r0 - r12} /* Calling r0-r12 */ add r8, sp, #S_PC +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -382,9 +658,13 @@ _start_armboot: .word start_armboot .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/ixp/u-boot.lds b/arch/arm/cpu/ixp/u-boot.lds index b8ff2ee..f3d9dc5 100644 --- a/arch/arm/cpu/ixp/u-boot.lds +++ b/arch/arm/cpu/ixp/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/lh7a40x/start.S b/arch/arm/cpu/lh7a40x/start.S index 14a1fbe..002116a 100644 --- a/arch/arm/cpu/lh7a40x/start.S +++ b/arch/arm/cpu/lh7a40x/start.S @@ -72,12 +72,15 @@ _fiq: .word fiq ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -102,8 +105,182 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + +#define pWDTCTL 0x80001400 /* Watchdog Timer control register */ +#define pINTENC 0x8000050C /* Interupt-Controller enable clear register */ +#define pCLKSET 0x80000420 /* clock divisor register */ + + /* disable watchdog, set watchdog control register to + * all zeros (default reset) + */ + ldr r0, =pWDTCTL + mov r1, #0x0 + str r1, [r0] + + /* + * mask all IRQs by setting all bits in the INTENC register (default) + */ + mov r1, #0xffffffff + ldr r0, =pINTENC + str r1, [r0] + + /* FCLK:HCLK:PCLK = 1:2:2 */ + /* default FCLK is 200 MHz, using 14.7456 MHz fin */ + ldr r0, =pCLKSET + ldr r1, =0x0004ee39 +@ ldr r1, =0x0005ee39 @ 1: 2: 4 + str r1, [r0] + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ /* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ +/* * the actual reset code */ @@ -195,7 +372,7 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot _start_armboot: .word start_armboot - +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -285,9 +462,13 @@ cpu_init_crit: .macro bad_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r3} @ get pc, cpsr add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -318,9 +499,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/lh7a40x/u-boot.lds b/arch/arm/cpu/lh7a40x/u-boot.lds index 5a8ccf5..cb55b0a 100644 --- a/arch/arm/cpu/lh7a40x/u-boot.lds +++ b/arch/arm/cpu/lh7a40x/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/pxa/start.S b/arch/arm/cpu/pxa/start.S index 8010b0e..064ddbc 100644 --- a/arch/arm/cpu/pxa/start.S +++ b/arch/arm/cpu/pxa/start.S @@ -82,12 +82,15 @@ _fiq: .word fiq * - jump to second stage */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -112,6 +115,162 @@ FIQ_STACK_START: .word 0x0badc0de #endif /* CONFIG_USE_IRQ */ +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ +#ifdef CONFIG_ONENAND_IPL + ldr pc, _start_oneboot + +_start_oneboot: .word start_oneboot +#else + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#endif + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /****************************************************************************/ /* */ @@ -188,6 +347,7 @@ _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot #endif +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /****************************************************************************/ /* */ @@ -367,9 +527,13 @@ setspeed_done: stmia sp, {r0 - r12} /* Calling r0-r12 */ add r8, sp, #S_PC +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r4} /* get pc, cpsr, old_r0 */ add r0, sp, #S_FRAME_SIZE /* restore sp_SVC */ @@ -404,9 +568,13 @@ setspeed_done: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/pxa/u-boot.lds b/arch/arm/cpu/pxa/u-boot.lds index d4e85ef..74a4c6e 100644 --- a/arch/arm/cpu/pxa/u-boot.lds +++ b/arch/arm/cpu/pxa/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/s3c44b0/start.S b/arch/arm/cpu/s3c44b0/start.S index 0063063..e1ab5cc 100644 --- a/arch/arm/cpu/s3c44b0/start.S +++ b/arch/arm/cpu/s3c44b0/start.S @@ -63,12 +63,15 @@ _start: b reset ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -93,7 +96,177 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit + /* + * before relocating, we have to setup RAM timing + * because memory timing is board-dependend, you will + * find a lowlevel_init.S in your board directory. + */ + bl lowlevel_init +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +/* + now copy to sram the interrupt vector +*/ + adr r0, real_vectors + add r2, r0, #1024 + ldr r1, =0x0c000000 + add r1, r1, #0x08 +vector_copy_loop: + ldmia r0!, {r3-r10} + stmia r1!, {r3-r10} + cmp r0, r2 + ble vector_copy_loop +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l + + bl coloured_LED_init + bl red_LED_on +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code */ @@ -169,6 +342,7 @@ stack_setup: _start_armboot: .word start_armboot +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* diff --git a/arch/arm/cpu/s3c44b0/u-boot.lds b/arch/arm/cpu/s3c44b0/u-boot.lds index 267d94c..bbc8c3a 100644 --- a/arch/arm/cpu/s3c44b0/u-boot.lds +++ b/arch/arm/cpu/s3c44b0/u-boot.lds @@ -39,11 +39,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/cpu/sa1100/start.S b/arch/arm/cpu/sa1100/start.S index deb4745..4730e5a 100644 --- a/arch/arm/cpu/sa1100/start.S +++ b/arch/arm/cpu/sa1100/start.S @@ -73,12 +73,15 @@ _fiq: .word fiq ************************************************************************* */ +.globl _TEXT_BASE _TEXT_BASE: .word TEXT_BASE +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) .globl _armboot_start _armboot_start: .word _start +#endif /* * These are defined in the board-specific linker script. @@ -103,6 +106,156 @@ FIQ_STACK_START: .word 0x0badc0de #endif +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +/* IRQ stack memory (calculated at run-time) + 8 bytes */ +.globl IRQ_STACK_START_IN +IRQ_STACK_START_IN: + .word 0x0badc0de + +.globl _datarel_start +_datarel_start: + .word __datarel_start + +.globl _datarelrolocal_start +_datarelrolocal_start: + .word __datarelrolocal_start + +.globl _datarellocal_start +_datarellocal_start: + .word __datarellocal_start + +.globl _datarelro_start +_datarelro_start: + .word __datarelro_start + +.globl _got_start +_got_start: + .word __got_start + +.globl _got_end +_got_end: + .word __got_end + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0,cpsr + bic r0,r0,#0x1f + orr r0,r0,#0xd3 + msr cpsr,r0 + + /* + * we do sys-critical inits only at reboot, + * not when booting from ram! + */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +/* Set stackpointer in internal RAM to call board_init_f */ +call_board_init_f: + ldr sp, =(CONFIG_SYS_INIT_SP_ADDR) + ldr r0,=0x00000000 + bl board_init_f + +/*------------------------------------------------------------------------------*/ + +/* + * void relocate_code (addr_sp, gd, addr_moni) + * + * This "function" does not return, instead it continues in RAM + * after relocating the monitor code. + * + */ + .globl relocate_code +relocate_code: + mov r4, r0 /* save addr_sp */ + mov r5, r1 /* save addr of gd */ + mov r6, r2 /* save addr of destination */ + mov r7, r2 /* save addr of destination */ + + /* Set up the stack */ +stack_setup: + mov sp, r4 + + adr r0, _start + ldr r2, _TEXT_BASE + ldr r3, _bss_start + sub r2, r3, r2 /* r2 <- size of armboot */ + add r2, r0, r2 /* r2 <- source end address */ + cmp r0, r6 + beq clear_bss + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +copy_loop: + ldmia r0!, {r9-r10} /* copy from source address [r0] */ + stmia r6!, {r9-r10} /* copy to target address [r1] */ + cmp r0, r2 /* until source end addreee [r2] */ + ble copy_loop + +#ifndef CONFIG_PRELOADER + /* fix got entries */ + ldr r1, _TEXT_BASE /* Text base */ + mov r0, r7 /* reloc addr */ + ldr r2, _got_start /* addr in Flash */ + ldr r3, _got_end /* addr in Flash */ + sub r3, r3, r1 + add r3, r3, r0 + sub r2, r2, r1 + add r2, r2, r0 + +fixloop: + ldr r4, [r2] + sub r4, r4, r1 + add r4, r4, r0 + str r4, [r2] + add r2, r2, #4 + cmp r2, r3 + bne fixloop +#endif +#endif /* #ifndef CONFIG_SKIP_RELOCATE_UBOOT */ + +clear_bss: +#ifndef CONFIG_PRELOADER + ldr r0, _bss_start + ldr r1, _bss_end + ldr r3, _TEXT_BASE /* Text base */ + mov r4, r7 /* reloc addr */ + sub r0, r0, r3 + add r0, r0, r4 + sub r1, r1, r3 + add r1, r1, r4 + mov r2, #0x00000000 /* clear */ + +clbss_l:str r2, [r0] /* clear loop... */ + add r0, r0, #4 + cmp r0, r1 + bne clbss_l +#endif + +/* + * We are done. Do not return, instead branch to second part of board + * initialization, now running from RAM. + */ + ldr r0, _TEXT_BASE + ldr r2, _board_init_r + sub r2, r2, r0 + add r2, r2, r7 /* position from board_init_r in RAM */ + /* setup parameters for board_init_r */ + mov r0, r5 /* gd_t */ + mov r1, r7 /* dest_addr */ + /* jump to it ... */ + mov lr, r2 + mov pc, lr + +_board_init_r: .word board_init_r + +#else /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* * the actual reset code @@ -169,6 +322,7 @@ clbss_l:str r2, [r0] /* clear loop... */ _start_armboot: .word start_armboot +#endif /* #if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ /* ************************************************************************* @@ -288,9 +442,13 @@ cpu_init_crit: stmia sp, {r0 - r12} @ Calling r0-r12 add r8, sp, #S_PC +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r2, _armboot_start sub r2, r2, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ set base 2 words into abort stack +#else + ldr r2, IRQ_STACK_START_IN +#endif ldmia r2, {r2 - r4} @ get pc, cpsr, old_r0 add r0, sp, #S_FRAME_SIZE @ restore sp_SVC @@ -321,9 +479,13 @@ cpu_init_crit: .endm .macro get_bad_stack +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) ldr r13, _armboot_start @ setup our mode stack sub r13, r13, #(CONFIG_STACKSIZE+CONFIG_SYS_MALLOC_LEN) sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE+8) @ reserved a couple spots in abort stack +#else + ldr r13, IRQ_STACK_START_IN @ setup our mode stack +#endif str lr, [r13] @ save caller lr / spsr mrs lr, spsr diff --git a/arch/arm/cpu/sa1100/u-boot.lds b/arch/arm/cpu/sa1100/u-boot.lds index f6197ac..2e29291 100644 --- a/arch/arm/cpu/sa1100/u-boot.lds +++ b/arch/arm/cpu/sa1100/u-boot.lds @@ -42,11 +42,23 @@ SECTIONS .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/arch/arm/include/asm/config.h b/arch/arm/include/asm/config.h index b76fd8e..4e8dfd7 100644 --- a/arch/arm/include/asm/config.h +++ b/arch/arm/include/asm/config.h @@ -21,7 +21,8 @@ #ifndef _ASM_CONFIG_H_ #define _ASM_CONFIG_H_ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) /* Relocation to SDRAM works on all ARM boards */ #define CONFIG_RELOC_FIXUP_WORKS - +#endif #endif diff --git a/arch/arm/include/asm/global_data.h b/arch/arm/include/asm/global_data.h index 02cfe45..6152f34 100644 --- a/arch/arm/include/asm/global_data.h +++ b/arch/arm/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -47,25 +47,32 @@ typedef struct global_data { #ifdef CONFIG_FSL_ESDHC unsigned long sdhc_clk; #endif -#if 0 - unsigned long cpu_clk; /* CPU clock in Hz! */ - unsigned long bus_clk; +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + unsigned long relocaddr; /* Start address of U-Boot in RAM */ phys_size_t ram_size; /* RAM size */ - unsigned long reset_status; /* reset status register at boot */ + unsigned long mon_len; /* monitor len */ + unsigned long irq_sp; /* irq stack pointer */ + unsigned long start_addr_sp; /* start_addr_stackpointer */ + unsigned long reloc_off; +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + unsigned long tlb_addr; +#endif #endif void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r8") diff --git a/arch/arm/include/asm/u-boot-arm.h b/arch/arm/include/asm/u-boot-arm.h index 6d2f8bc..faf800a 100644 --- a/arch/arm/include/asm/u-boot-arm.h +++ b/arch/arm/include/asm/u-boot-arm.h @@ -30,11 +30,20 @@ #define _U_BOOT_ARM_H_ 1 /* for the following variables, see start.S */ -extern ulong _armboot_start; /* code start */ extern ulong _bss_start; /* code + data end == BSS start */ extern ulong _bss_end; /* BSS end */ extern ulong IRQ_STACK_START; /* top of IRQ stack */ extern ulong FIQ_STACK_START; /* top of FIQ stack */ +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +extern ulong _armboot_start; /* code start */ +#else +extern ulong _TEXT_BASE; /* code start */ +extern ulong _datarel_start; +extern ulong _datarelrolocal_start; +extern ulong _datarellocal_start; +extern ulong _datarelro_start; +extern ulong IRQ_STACK_START_IN; /* 8 bytes in IRQ stack */ +#endif /* cpu/.../cpu.c */ int cpu_init(void); @@ -47,6 +56,9 @@ int arch_misc_init(void); /* board/.../... */ int board_init(void); int dram_init (void); +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +void dram_init_banksize (void); +#endif void setup_serial_tag (struct tag **params); void setup_revision_tag (struct tag **params); diff --git a/arch/arm/include/asm/u-boot.h b/arch/arm/include/asm/u-boot.h index cfd5a9b..ed33327 100644 --- a/arch/arm/include/asm/u-boot.h +++ b/arch/arm/include/asm/u-boot.h @@ -39,7 +39,6 @@ typedef struct bd_info { int bi_baudrate; /* serial console baudrate */ unsigned long bi_ip_addr; /* IP Address */ - struct environment_s *bi_env; ulong bi_arch_number; /* unique id for this board */ ulong bi_boot_params; /* where this board expects params */ struct /* RAM configuration */ @@ -49,7 +48,4 @@ typedef struct bd_info { } bi_dram[CONFIG_NR_DRAM_BANKS]; } bd_t; -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - #endif /* _U_BOOT_H_ */ diff --git a/arch/arm/lib/board.c b/arch/arm/lib/board.c index e17f182..5f2dfd0 100644 --- a/arch/arm/lib/board.c +++ b/arch/arm/lib/board.c @@ -126,7 +126,12 @@ static int init_baudrate (void) { char tmp[64]; /* long enough for environment variables */ int i = getenv_f("baudrate", tmp, sizeof (tmp)); + +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + gd->baudrate = (i > 0) +#else gd->bd->bi_baudrate = gd->baudrate = (i > 0) +#endif ? (int) simple_strtoul (tmp, NULL, 10) : CONFIG_BAUDRATE; @@ -137,7 +142,12 @@ static int display_banner (void) { printf ("\n\n%s\n\n", version_string); debug ("U-Boot code: %08lX -> %08lX BSS: -> %08lX\n", - _armboot_start, _bss_start, _bss_end); +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + _TEXT_BASE, +#else + _armboot_start, +#endif + _bss_start, _bss_end); #ifdef CONFIG_MODEM_SUPPORT debug ("Modem Support enabled\n"); #endif @@ -180,6 +190,7 @@ static int display_dram_config (void) return (0); } +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) #ifndef CONFIG_SYS_NO_FLASH static void display_flash_config (ulong size) { @@ -187,6 +198,7 @@ static void display_flash_config (ulong size) print_size (size, "\n"); } #endif /* CONFIG_SYS_NO_FLASH */ +#endif #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) static int init_func_i2c (void) @@ -234,6 +246,7 @@ typedef int (init_fnc_t) (void); int print_cpuinfo (void); +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) init_fnc_t *init_sequence[] = { #if defined(CONFIG_ARCH_CPU_INIT) arch_cpu_init, /* basic arch cpu dependent setup */ @@ -449,6 +462,459 @@ extern void davinci_eth_set_mac_addr (const u_int8_t *addr); /* NOTREACHED - no way out of command loop except booting */ } +#else +void __dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} +void dram_init_banksize(void) + __attribute__((weak, alias("__dram_init_banksize"))); + +init_fnc_t *init_sequence[] = { +#if defined(CONFIG_ARCH_CPU_INIT) + arch_cpu_init, /* basic arch cpu dependent setup */ +#endif +#if defined(CONFIG_BOARD_EARLY_INIT_F) + board_early_init_f, +#endif + timer_init, /* initialize timer */ +#ifdef CONFIG_FSL_ESDHC + get_clocks, +#endif + env_init, /* initialize environment */ + init_baudrate, /* initialze baudrate settings */ + serial_init, /* serial communications setup */ + console_init_f, /* stage 1 init of console */ + display_banner, /* say that we are here */ +#if defined(CONFIG_DISPLAY_CPUINFO) + print_cpuinfo, /* display cpu info (and speed) */ +#endif +#if defined(CONFIG_DISPLAY_BOARDINFO) + checkboard, /* display board info */ +#endif +#if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) + init_func_i2c, +#endif + dram_init, /* configure available RAM banks */ +#if defined(CONFIG_CMD_PCI) || defined (CONFIG_PCI) + arm_pci_init, +#endif + NULL, +}; + +void board_init_f (ulong bootflag) +{ + bd_t *bd; + init_fnc_t **init_fnc_ptr; + gd_t *id; + ulong addr, addr_sp; + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CONFIG_SYS_INIT_SP_ADDR); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + + memset ((void*)gd, 0, sizeof (gd_t)); + + gd->mon_len = _bss_end - _TEXT_BASE; + + for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { + if ((*init_fnc_ptr)() != 0) { + hang (); + } + } + + debug ("monitor len: %08lX\n", gd->mon_len); + /* + * Ram is setup, size stored in gd !! + */ + debug ("ramsize: %08lX\n", gd->ram_size); +#if defined(CONFIG_SYS_MEM_TOP_HIDE) + /* + * Subtract specified amount of memory to hide so that it won't + * get "touched" at all by U-Boot. By fixing up gd->ram_size + * the Linux kernel should now get passed the now "corrected" + * memory size and won't touch it either. This should work + * for arch/ppc and arch/powerpc. Only Linux board ports in + * arch/powerpc with bootwrapper support, that recalculate the + * memory size from the SDRAM controller setup will have to + * get fixed. + */ + gd->ram_size -= CONFIG_SYS_MEM_TOP_HIDE; +#endif + + addr = CONFIG_SYS_SDRAM_BASE + gd->ram_size; + +#ifdef CONFIG_LOGBUFFER +#ifndef CONFIG_ALT_LB_ADDR + /* reserve kernel log buffer */ + addr -= (LOGBUFF_RESERVE); + debug ("Reserving %dk for kernel logbuffer at %08lx\n", LOGBUFF_LEN, addr); +#endif +#endif + +#ifdef CONFIG_PRAM + /* + * reserve protected RAM + */ + i = getenv_r ("pram", (char *)tmp, sizeof (tmp)); + reg = (i > 0) ? simple_strtoul ((const char *)tmp, NULL, 10) : CONFIG_PRAM; + addr -= (reg << 10); /* size is in kB */ + debug ("Reserving %ldk for protected RAM at %08lx\n", reg, addr); +#endif /* CONFIG_PRAM */ + +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + /* reserve TLB table */ + addr -= (4096 * 4); + + /* round down to next 64 kB limit */ + addr &= ~(0x10000 - 1); + + gd->tlb_addr = addr; + debug ("TLB table at: %08lx\n", addr); +#endif + + /* round down to next 4 kB limit */ + addr &= ~(4096 - 1); + debug ("Top of RAM usable for U-Boot at: %08lx\n", addr); + +#ifdef CONFIG_VFD +# ifndef PAGE_SIZE +# define PAGE_SIZE 4096 +# endif + /* + * reserve memory for VFD display (always full pages) + */ + addr -= vfd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_VFD */ + +#ifdef CONFIG_LCD + /* reserve memory for LCD display (always full pages) */ + addr = lcd_setmem (addr); + gd->fb_base = addr; +#endif /* CONFIG_LCD */ + + /* + * reserve memory for U-Boot code, data & bss + * round down to next 4 kB limit + */ + addr -= gd->mon_len; + addr &= ~(4096 - 1); + + debug ("Reserving %ldk for U-Boot at: %08lx\n", gd->mon_len >> 10, addr); + +#ifndef CONFIG_PRELOADER + /* + * reserve memory for malloc() arena + */ + addr_sp = addr - TOTAL_MALLOC_LEN; + debug ("Reserving %dk for malloc() at: %08lx\n", + TOTAL_MALLOC_LEN >> 10, addr_sp); + /* + * (permanently) allocate a Board Info struct + * and a permanent copy of the "global" data + */ + addr_sp -= sizeof (bd_t); + bd = (bd_t *) addr_sp; + gd->bd = bd; + debug ("Reserving %zu Bytes for Board Info at: %08lx\n", + sizeof (bd_t), addr_sp); + addr_sp -= sizeof (gd_t); + id = (gd_t *) addr_sp; + debug ("Reserving %zu Bytes for Global Data at: %08lx\n", + sizeof (gd_t), addr_sp); + + /* setup stackpointer for exeptions */ + gd->irq_sp = addr_sp; +#ifdef CONFIG_USE_IRQ + addr_sp -= (CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ); + debug ("Reserving %zu Bytes for IRQ stack at: %08lx\n", + CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ, addr_sp); +#endif + /* leave 3 words for abort-stack */ + addr_sp -= 3; + + /* 8-byte alignment for ABI compliance */ + addr_sp &= ~0x07; +#else + addr_sp += 128; /* leave 32 words for abort-stack */ + gd->irq_sp = addr_sp; +#endif + + debug ("New Stack Pointer is: %08lx\n", addr_sp); + +#ifdef CONFIG_POST + post_bootmode_init(); + post_run (NULL, POST_ROM | post_bootmode_get(0)); +#endif + + gd->bd->bi_baudrate = gd->baudrate; + /* Ram ist board specific, so move it to board code ... */ + dram_init_banksize(); + display_dram_config(); /* and display it */ + + gd->relocaddr = addr; + gd->start_addr_sp = addr_sp; + gd->reloc_off = addr - _TEXT_BASE; + debug ("relocation Offset is: %08lx\n", gd->reloc_off); + memcpy (id, (void *)gd, sizeof (gd_t)); + + relocate_code (addr_sp, id, addr); + + /* NOTREACHED - relocate_code() does not return */ +} + +#if !defined(CONFIG_SYS_NO_FLASH) +static char *failed = "*** failed ***\n"; +#endif + +/************************************************************************ + * + * This is the next part if the initialization sequence: we are now + * running from RAM and have a "normal" C environment, i. e. global + * data can be written, BSS has been cleared, the stack size in not + * that critical any more, etc. + * + ************************************************************************ + */ +void board_init_r (gd_t *id, ulong dest_addr) +{ + char *s; + bd_t *bd; + ulong malloc_start; +#if !defined(CONFIG_SYS_NO_FLASH) + ulong flash_size; +#endif +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + extern void malloc_bin_reloc (void); +#if defined(CONFIG_CMD_BMP) + extern void bmp_reloc(void); +#endif +#if defined(CONFIG_CMD_I2C) + extern void i2c_reloc(void); +#endif +#endif + + gd = id; + bd = gd->bd; + + gd->flags |= GD_FLG_RELOC; /* tell others: relocation done */ + + monitor_flash_len = _bss_start - _TEXT_BASE; + debug ("monitor flash len: %08lX\n", monitor_flash_len); + board_init(); /* Setup chipselects */ + +#ifdef CONFIG_SERIAL_MULTI + serial_initialize(); +#endif + + debug ("Now running in RAM - U-Boot at: %08lx\n", dest_addr); + +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + /* + * We have to relocate the command table manually + */ + fixup_cmdtable(&__u_boot_cmd_start, + (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); +#if defined(CONFIG_CMD_BMP) + bmp_reloc(); +#endif +#if defined(CONFIG_CMD_I2C) + i2c_reloc(); +#endif +#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ + +#ifdef CONFIG_LOGBUFFER + logbuff_init_ptrs (); +#endif +#ifdef CONFIG_POST + post_output_backlog (); +#ifndef CONFIG_RELOC_FIXUP_WORKS + post_reloc (); +#endif +#endif + + /* The Malloc area is immediately below the monitor copy in DRAM */ + malloc_start = dest_addr - TOTAL_MALLOC_LEN; + mem_malloc_init (malloc_start, TOTAL_MALLOC_LEN); +#if !defined(CONFIG_RELOC_FIXUP_WORKS) + malloc_bin_reloc (); +#endif + +#if !defined(CONFIG_SYS_NO_FLASH) + puts ("FLASH: "); + + if ((flash_size = flash_init ()) > 0) { +# ifdef CONFIG_SYS_FLASH_CHECKSUM + print_size (flash_size, ""); + /* + * Compute and print flash CRC if flashchecksum is set to 'y' + * + * NOTE: Maybe we should add some WATCHDOG_RESET()? XXX + */ + s = getenv ("flashchecksum"); + if (s && (*s == 'y')) { + printf (" CRC: %08X", + crc32 (0, (const unsigned char *) CONFIG_SYS_FLASH_BASE, flash_size) + ); + } + putc ('\n'); +# else /* !CONFIG_SYS_FLASH_CHECKSUM */ + print_size (flash_size, "\n"); +# endif /* CONFIG_SYS_FLASH_CHECKSUM */ + } else { + puts (failed); + hang (); + } +#endif + +#if defined(CONFIG_CMD_NAND) + puts ("NAND: "); + nand_init(); /* go init the NAND */ +#endif + +#if defined(CONFIG_CMD_ONENAND) + onenand_init(); +#endif + +#ifdef CONFIG_HAS_DATAFLASH + AT91F_DataflashInit(); + dataflash_print_info(); +#endif + + /* initialize environment */ + env_relocate (); + +#ifdef CONFIG_VFD + /* must do this after the framebuffer is allocated */ + drv_vfd_init(); +#endif /* CONFIG_VFD */ + + /* IP Address */ + gd->bd->bi_ip_addr = getenv_IPaddr ("ipaddr"); + + stdio_init (); /* get the devices list going. */ + + jumptable_init (); + +#if defined(CONFIG_API) + /* Initialize API */ + api_init (); +#endif + + console_init_r (); /* fully init console as a device */ + +#if defined(CONFIG_ARCH_MISC_INIT) + /* miscellaneous arch dependent initialisations */ + arch_misc_init (); +#endif +#if defined(CONFIG_MISC_INIT_R) + /* miscellaneous platform dependent initialisations */ + misc_init_r (); +#endif + + /* set up exceptions */ + interrupt_init (); + /* enable exceptions */ + enable_interrupts (); + + /* Perform network card initialisation if necessary */ +#ifdef CONFIG_DRIVER_TI_EMAC + /* XXX: this needs to be moved to board init */ +extern void davinci_eth_set_mac_addr (const u_int8_t *addr); + if (getenv ("ethaddr")) { + uchar enetaddr[6]; + eth_getenv_enetaddr("ethaddr", enetaddr); + davinci_eth_set_mac_addr(enetaddr); + } +#endif + +#if defined(CONFIG_DRIVER_SMC91111) || defined (CONFIG_DRIVER_LAN91C96) + /* XXX: this needs to be moved to board init */ + if (getenv ("ethaddr")) { + uchar enetaddr[6]; + eth_getenv_enetaddr("ethaddr", enetaddr); + smc_set_mac_addr(enetaddr); + } +#endif /* CONFIG_DRIVER_SMC91111 || CONFIG_DRIVER_LAN91C96 */ + + /* Initialize from environment */ + if ((s = getenv ("loadaddr")) != NULL) { + load_addr = simple_strtoul (s, NULL, 16); + } +#if defined(CONFIG_CMD_NET) + if ((s = getenv ("bootfile")) != NULL) { + copy_filename (BootFile, s, sizeof (BootFile)); + } +#endif + +#ifdef BOARD_LATE_INIT + board_late_init (); +#endif + +#ifdef CONFIG_GENERIC_MMC + puts ("MMC: "); + mmc_initialize (gd->bd); +#endif + +#ifdef CONFIG_BITBANGMII + bb_miiphy_init(); +#endif +#if defined(CONFIG_CMD_NET) +#if defined(CONFIG_NET_MULTI) + puts ("Net: "); +#endif + eth_initialize(gd->bd); +#if defined(CONFIG_RESET_PHY_R) + debug ("Reset Ethernet PHY\n"); + reset_phy(); +#endif +#endif + +#ifdef CONFIG_POST + post_run (NULL, POST_RAM | post_bootmode_get(0)); +#endif + +#if defined(CONFIG_PRAM) || defined(CONFIG_LOGBUFFER) + /* + * Export available size of memory for Linux, + * taking into account the protected RAM at top of memory + */ + { + ulong pram; + uchar memsz[32]; +#ifdef CONFIG_PRAM + char *s; + + if ((s = getenv ("pram")) != NULL) { + pram = simple_strtoul (s, NULL, 10); + } else { + pram = CONFIG_PRAM; + } +#else + pram=0; +#endif +#ifdef CONFIG_LOGBUFFER +#ifndef CONFIG_ALT_LB_ADDR + /* Also take the logbuffer into account (pram is in kB) */ + pram += (LOGBUFF_LEN+LOGBUFF_OVERHEAD)/1024; +#endif +#endif + sprintf ((char *)memsz, "%ldk", (bd->bi_memsize / 1024) - pram); + setenv ("mem", (char *)memsz); + } +#endif + + /* main_loop() can return to retry autoboot, if so just run it again. */ + for (;;) { + main_loop (); + } + + /* NOTREACHED - no way out of command loop except booting */ +} +#endif /* defined(CONFIG_SYS_ARM_WITHOUT_RELOC) */ void hang (void) { diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 62ed54f..fe6d459 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -25,6 +25,15 @@ #include <asm/system.h> #if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define CACHE_SETUP 0x1a +#else +#define CACHE_SETUP 0x1e +#endif + +DECLARE_GLOBAL_DATA_PTR; + static void cp_delay (void) { volatile int i; @@ -32,6 +41,67 @@ static void cp_delay (void) /* copro seems to need some delay between reading and writing */ for (i = 0; i < 100; i++) nop(); + asm volatile("" : : : "memory"); +} + +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +static inline void dram_bank_mmu_setup(int bank) +{ + u32 *page_table = (u32 *)gd->tlb_addr; + bd_t *bd = gd->bd; + int i; + + debug("%s: bank: %d\n", __func__, bank); + for (i = bd->bi_dram[bank].start >> 20; + i < (bd->bi_dram[bank].start + bd->bi_dram[bank].size) >> 20; + i++) { + page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; + } +} +#endif + +/* to activate the MMU we need to set up virtual memory: use 1M areas */ +static inline void mmu_setup(void) +{ +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + u32 *page_table = (u32 *)gd->tlb_addr; +#else + static u32 __attribute__((aligned(16384))) page_table[4096]; + bd_t *bd = gd->bd; + int j; +#endif + int i; + u32 reg; + + /* Set up an identity-mapping for all 4GB, rw for everyone */ + for (i = 0; i < 4096; i++) + page_table[i] = i << 20 | (3 << 10) | 0x12; + +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + dram_bank_mmu_setup(i); + } +#else + /* Then, enable cacheable and bufferable for RAM only */ + for (j = 0; j < CONFIG_NR_DRAM_BANKS; j++) { + for (i = bd->bi_dram[j].start >> 20; + i < (bd->bi_dram[j].start + bd->bi_dram[j].size) >> 20; + i++) { + page_table[i] = i << 20 | (3 << 10) | CACHE_SETUP; + } + } +#endif + + /* Copy the page table address to cp15 */ + asm volatile("mcr p15, 0, %0, c2, c0, 0" + : : "r" (page_table) : "memory"); + /* Set the access control to all-supervisor */ + asm volatile("mcr p15, 0, %0, c3, c0, 0" + : : "r" (~0)); + /* and enable the mmu */ + reg = get_cr(); /* get control reg. */ + cp_delay(); + set_cr(reg | CR_M); } /* cache_bit must be either CR_I or CR_C */ @@ -39,6 +109,9 @@ static void cache_enable(uint32_t cache_bit) { uint32_t reg; + /* The data cache is not active unless the mmu is enabled too */ + if (cache_bit == CR_C) + mmu_setup(); reg = get_cr(); /* get control reg. */ cp_delay(); set_cr(reg | cache_bit); @@ -49,6 +122,15 @@ static void cache_disable(uint32_t cache_bit) { uint32_t reg; + if (cache_bit == CR_C) { + /* if cache isn;t enabled no need to disable */ + reg = get_cr(); + if ((reg & CR_C) != CR_C) + return; + /* if disabling data cache, disable mmu too */ + cache_bit |= CR_M; + flush_cache(0, ~0); + } reg = get_cr(); cp_delay(); set_cr(reg & ~cache_bit); diff --git a/arch/arm/lib/cache.c b/arch/arm/lib/cache.c index 61ee9d3..55b633e 100644 --- a/arch/arm/lib/cache.c +++ b/arch/arm/lib/cache.c @@ -27,10 +27,21 @@ void flush_cache (unsigned long dummy1, unsigned long dummy2) { -#ifdef CONFIG_OMAP2420 +#if defined(CONFIG_OMAP2420) || defined(CONFIG_ARM1136) void arm1136_cache_flush(void); arm1136_cache_flush(); #endif +#ifdef CONFIG_ARM926EJS + /* test and clean, page 2-23 of arm926ejs manual */ + asm("0: mrc p15, 0, r15, c7, c10, 3\n\t" "bne 0b\n" : : : "memory"); + /* disable write buffer as well (page 2-22) */ + asm("mcr p15, 0, %0, c7, c10, 4" : : "r" (0)); +#endif +#ifdef CONFIG_ARMCORTEXA8 + void v7_flush_cache_all(void); + + v7_flush_cache_all(); +#endif return; } diff --git a/arch/arm/lib/interrupts.c b/arch/arm/lib/interrupts.c index 1f2b815..9a21e7b 100644 --- a/arch/arm/lib/interrupts.c +++ b/arch/arm/lib/interrupts.c @@ -38,15 +38,20 @@ #include <common.h> #include <asm/proc-armv/ptrace.h> -#ifdef CONFIG_USE_IRQ DECLARE_GLOBAL_DATA_PTR; +#ifdef CONFIG_USE_IRQ int interrupt_init (void) { /* * setup up stacks if necessary */ +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) + IRQ_STACK_START = gd->irq_sp - 4; + IRQ_STACK_START_IN = gd->irq_sp + 8; +#else IRQ_STACK_START = _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; +#endif FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; return arch_interrupt_init(); @@ -81,6 +86,18 @@ int disable_interrupts (void) return (old & 0x80) == 0; } #else +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +int interrupt_init (void) +{ + /* + * setup up stacks if necessary + */ + IRQ_STACK_START_IN = gd->irq_sp + 8; + + return 0; +} +#endif + void enable_interrupts (void) { return; diff --git a/arch/avr32/include/asm/global_data.h b/arch/avr32/include/asm/global_data.h index efbdda9..5a7aed9 100644 --- a/arch/avr32/include/asm/global_data.h +++ b/arch/avr32/include/asm/global_data.h @@ -46,18 +46,20 @@ typedef struct global_data { void *fb_base; /* framebuffer address */ #endif void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm("r5") diff --git a/arch/avr32/include/asm/u-boot.h b/arch/avr32/include/asm/u-boot.h index 7e4001f..8acd056 100644 --- a/arch/avr32/include/asm/u-boot.h +++ b/arch/avr32/include/asm/u-boot.h @@ -26,7 +26,6 @@ typedef struct bd_info { unsigned long bi_baudrate; unsigned long bi_ip_addr; unsigned char bi_phy_id[4]; - struct environment_s *bi_env; unsigned long bi_board_number; void *bi_boot_params; struct { diff --git a/arch/avr32/lib/board.c b/arch/avr32/lib/board.c index aa589bb..e6b81cc 100644 --- a/arch/avr32/lib/board.c +++ b/arch/avr32/lib/board.c @@ -273,30 +273,13 @@ void board_init_r(gd_t *new_gd, ulong dest_addr) monitor_flash_len = _edata - _text; +#if !defined(CONFIG_RELOC_FIXUP_WORKS) /* * We have to relocate the command table manually */ - for (cmdtp = &__u_boot_cmd_start; - cmdtp != &__u_boot_cmd_end; cmdtp++) { - unsigned long addr; - - addr = (unsigned long)cmdtp->cmd + gd->reloc_off; - cmdtp->cmd = (typeof(cmdtp->cmd))addr; - - addr = (unsigned long)cmdtp->name + gd->reloc_off; - cmdtp->name = (typeof(cmdtp->name))addr; - - if (cmdtp->usage) { - addr = (unsigned long)cmdtp->usage + gd->reloc_off; - cmdtp->usage = (typeof(cmdtp->usage))addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (unsigned long)cmdtp->help + gd->reloc_off; - cmdtp->help = (typeof(cmdtp->help))addr; - } -#endif - } + fixup_cmdtable(&__u_boot_cmd_start, + (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); +#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE diff --git a/arch/blackfin/include/asm/global_data.h b/arch/blackfin/include/asm/global_data.h index c7099e6..d5514b0 100644 --- a/arch/blackfin/include/asm/global_data.h +++ b/arch/blackfin/include/asm/global_data.h @@ -3,7 +3,7 @@ * * Copyright (c) 2005-2007 Analog Devices Inc. * - * (C) Copyright 2000-2004 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -53,19 +53,21 @@ typedef struct global_data { unsigned long post_init_f_time; /* When post_init_f started */ #endif - void **jt; /* jump table */ + void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register gd_t * volatile gd asm ("P3") diff --git a/arch/i386/include/asm/global_data.h b/arch/i386/include/asm/global_data.h index 3abbf1d..3a9adc9 100644 --- a/arch/i386/include/asm/global_data.h +++ b/arch/i386/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -46,18 +46,20 @@ typedef struct { phys_size_t ram_size; /* RAM size */ unsigned long reset_status; /* reset status register at boot */ void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ extern gd_t *gd; diff --git a/arch/i386/include/asm/u-boot.h b/arch/i386/include/asm/u-boot.h index 9a1eec0..a43b3aa 100644 --- a/arch/i386/include/asm/u-boot.h +++ b/arch/i386/include/asm/u-boot.h @@ -51,7 +51,6 @@ typedef struct bd_info { unsigned long bi_busfreq; /* Bus Freq, in MHz */ unsigned int bi_baudrate; /* Console Baudrate */ unsigned long bi_boot_params; /* where this board expects params */ - struct environment_s *bi_env; struct /* RAM configuration */ { ulong start; @@ -59,7 +58,4 @@ typedef struct bd_info { }bi_dram[CONFIG_NR_DRAM_BANKS]; } bd_t; -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc - #endif /* _U_BOOT_H_ */ diff --git a/arch/i386/lib/board.c b/arch/i386/lib/board.c index 93f910b..5002203 100644 --- a/arch/i386/lib/board.c +++ b/arch/i386/lib/board.c @@ -335,13 +335,6 @@ void board_init_r(gd_t *id, ulong dest_addr) enable_interrupts(); show_boot_progress(0x28); - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - #ifdef CONFIG_STATUS_LED status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif diff --git a/arch/m68k/include/asm/global_data.h b/arch/m68k/include/asm/global_data.h index 413c200..3a36f82 100644 --- a/arch/m68k/include/asm/global_data.h +++ b/arch/m68k/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 - 2003 + * (C) Copyright 2002 - 2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -64,18 +64,20 @@ typedef struct global_data { unsigned long board_type; #endif void **jt; /* Standalone app jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #if 0 extern gd_t *global_data; diff --git a/arch/m68k/lib/board.c b/arch/m68k/lib/board.c index b254079..c29f577 100644 --- a/arch/m68k/lib/board.c +++ b/arch/m68k/lib/board.c @@ -79,14 +79,6 @@ extern flash_info_t flash_info[]; #include <environment.h> -#if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ - (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN -#endif - extern ulong __init_end; extern ulong _end; @@ -433,33 +425,14 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = (ulong)&__init_end - dest_addr; +#if !defined(CONFIG_RELOC_FIXUP_WORKS) /* * We have to relocate the command table manually */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; + fixup_cmdtable(&__u_boot_cmd_start, + (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); +#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE env_name_spec += gd->reloc_off; @@ -596,10 +569,6 @@ void board_init_r (gd_t *id, ulong dest_addr) */ timer_init(); -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - #ifdef CONFIG_STATUS_LED status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif diff --git a/arch/microblaze/include/asm/global_data.h b/arch/microblaze/include/asm/global_data.h index ec7837f..03444ef 100644 --- a/arch/microblaze/include/asm/global_data.h +++ b/arch/microblaze/include/asm/global_data.h @@ -43,18 +43,20 @@ typedef struct global_data { unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long fb_base; /* base address of frame buffer */ void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r31") diff --git a/arch/mips/include/asm/global_data.h b/arch/mips/include/asm/global_data.h index b2c4891..bf1bfc3 100644 --- a/arch/mips/include/asm/global_data.h +++ b/arch/mips/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002-2003 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -46,18 +46,20 @@ typedef struct global_data { unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buf has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("k0") diff --git a/arch/mips/include/asm/u-boot.h b/arch/mips/include/asm/u-boot.h index d9c14ca..e839ca1 100644 --- a/arch/mips/include/asm/u-boot.h +++ b/arch/mips/include/asm/u-boot.h @@ -42,7 +42,5 @@ typedef struct bd_info { unsigned long bi_flashsize; /* size of FLASH memory */ unsigned long bi_flashoffset; /* reserved area for startup monitor */ } bd_t; -#define bi_env_data bi_env->data -#define bi_env_crc bi_env->crc #endif /* _U_BOOT_H_ */ diff --git a/arch/mips/lib/board.c b/arch/mips/lib/board.c index ab4a17c..0044b19 100644 --- a/arch/mips/lib/board.c +++ b/arch/mips/lib/board.c @@ -39,14 +39,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ - (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN -#endif - #undef DEBUG extern int timer_init(void); @@ -304,34 +296,14 @@ void board_init_r (gd_t *id, ulong dest_addr) monitor_flash_len = (ulong)&uboot_end_data - dest_addr; +#if !defined(CONFIG_RELOC_FIXUP_WORKS) /* * We have to relocate the command table manually */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if 0 - printf ("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; + fixup_cmdtable(&__u_boot_cmd_start, + (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); +#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ - addr = (ulong)(cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong)(cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong)(cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } /* there are some other pointer constants we must deal with */ #ifndef CONFIG_ENV_IS_NOWHERE env_name_spec += gd->reloc_off; diff --git a/arch/nios2/include/asm/global_data.h b/arch/nios2/include/asm/global_data.h index f1b3482..2c4a719 100644 --- a/arch/nios2/include/asm/global_data.h +++ b/arch/nios2/include/asm/global_data.h @@ -37,16 +37,18 @@ typedef struct global_data { unsigned long post_init_f_time; /* When post_init_f started */ #endif void **jt; /* Standalone app jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("gp") diff --git a/arch/powerpc/cpu/mpc512x/Makefile b/arch/powerpc/cpu/mpc512x/Makefile index ae2f6dc..37b06f3 100644 --- a/arch/powerpc/cpu/mpc512x/Makefile +++ b/arch/powerpc/cpu/mpc512x/Makefile @@ -38,7 +38,6 @@ COBJS-y += serial.o COBJS-y += speed.o COBJS-$(CONFIG_FSL_DIU_FB) += diu.o COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_diu_fb.o -COBJS-$(CONFIG_FSL_DIU_FB) += ../../../../board/freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_CMD_IDE) += ide.o COBJS-$(CONFIG_IIM) += iim.o COBJS-$(CONFIG_PCI) += pci.o diff --git a/arch/powerpc/cpu/mpc512x/diu.c b/arch/powerpc/cpu/mpc512x/diu.c index 9ef5609..fa4a0bc 100644 --- a/arch/powerpc/cpu/mpc512x/diu.c +++ b/arch/powerpc/cpu/mpc512x/diu.c @@ -36,12 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; -#ifdef CONFIG_FSL_DIU_LOGO_BMP -extern unsigned int FSL_Logo_BMP[]; -#else -#define FSL_Logo_BMP NULL -#endif - static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) @@ -64,28 +58,9 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", in_be32(clkdvdr)); } -char *valid_bmp(char *addr) -{ - unsigned long h_addr; - bd_t *bd = gd->bd; - - h_addr = simple_strtoul(addr, NULL, 16); - if (h_addr < bd->bi_flashstart || - h_addr >= (bd->bi_flashstart + bd->bi_flashsize - 1)) { - printf("bmp addr %lx is not a valid flash address\n", h_addr); - return 0; - } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { - printf("bmp addr is not a bmp\n"); - return 0; - } else - return (char *)h_addr; -} - int mpc5121_diu_init(void) { unsigned int pixel_format; - char *bmp = NULL; - char *bmp_env; #if defined(CONFIG_VIDEO_XRES) & defined(CONFIG_VIDEO_YRES) xres = CONFIG_VIDEO_XRES; @@ -97,47 +72,10 @@ int mpc5121_diu_init(void) pixel_format = 0x88883316; debug("mpc5121_diu_init\n"); - bmp_env = getenv("diu_bmp_addr"); - if (bmp_env) { - bmp = valid_bmp(bmp_env); - } - if (!bmp) - bmp = (char *)FSL_Logo_BMP; - return fsl_diu_init(xres, pixel_format, 0, (unsigned char *)bmp); -} - -int mpc5121diu_init_show_bmp(cmd_tbl_t *cmdtp, - int flag, int argc, char * const argv[]) -{ - unsigned int addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - if (!strncmp(argv[1], "init", 4)) { -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - fsl_diu_clear_screen(); - drv_video_init(); -#else - return mpc5121_diu_init(); -#endif - } else { - addr = simple_strtoul(argv[1], NULL, 16); - fsl_diu_clear_screen(); - fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); - } - return 0; + return fsl_diu_init(xres, pixel_format, 0); } -U_BOOT_CMD( - diufb, CONFIG_SYS_MAXARGS, 1, mpc5121diu_init_show_bmp, - "Init or Display BMP file", - "init\n - initialize DIU\n" - "addr\n - display bmp at address 'addr'" - ); - - #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) /* @@ -158,7 +96,7 @@ void *video_hw_init(void) pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); pGD->winSizeX = xres; - pGD->winSizeY = yres - info->logo_height; + pGD->winSizeY = yres; pGD->plnSizeX = pGD->winSizeX; pGD->plnSizeY = pGD->winSizeY; @@ -167,7 +105,7 @@ void *video_hw_init(void) pGD->isaBase = 0; pGD->pciBase = 0; - pGD->memSize = info->screen_size - info->logo_size; + pGD->memSize = info->screen_size; /* Cursor Start Address */ pGD->dprBase = 0; diff --git a/arch/powerpc/cpu/mpc83xx/cpu_init.c b/arch/powerpc/cpu/mpc83xx/cpu_init.c index 83cba93..f01c09a 100644 --- a/arch/powerpc/cpu/mpc83xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc83xx/cpu_init.c @@ -126,6 +126,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ SCCR_PCICM | #endif +#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ + SCCR_PCIEXP1CM | +#endif +#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ + SCCR_PCIEXP2CM | +#endif #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ SCCR_TSECCM | #endif @@ -158,6 +164,12 @@ void cpu_init_f (volatile immap_t * im) #ifdef CONFIG_SYS_SCCR_PCICM /* PCI & DMA clock mode */ (CONFIG_SYS_SCCR_PCICM << SCCR_PCICM_SHIFT) | #endif +#ifdef CONFIG_SYS_SCCR_PCIEXP1CM /* PCIE1 clock mode */ + (CONFIG_SYS_SCCR_PCIEXP1CM << SCCR_PCIEXP1CM_SHIFT) | +#endif +#ifdef CONFIG_SYS_SCCR_PCIEXP2CM /* PCIE2 clock mode */ + (CONFIG_SYS_SCCR_PCIEXP2CM << SCCR_PCIEXP2CM_SHIFT) | +#endif #ifdef CONFIG_SYS_SCCR_TSECCM /* all TSEC's clock mode */ (CONFIG_SYS_SCCR_TSECCM << SCCR_TSECCM_SHIFT) | #endif diff --git a/arch/powerpc/cpu/mpc83xx/pci.c b/arch/powerpc/cpu/mpc83xx/pci.c index a42b230..288d99f 100644 --- a/arch/powerpc/cpu/mpc83xx/pci.c +++ b/arch/powerpc/cpu/mpc83xx/pci.c @@ -133,7 +133,7 @@ static void pci_init_bus(int bus, struct pci_region *reg) * If fewer than three regions are requested, then the region * list is terminated with a region of size 0. */ -void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) +void mpc83xx_pci_init(int num_buses, struct pci_region **reg) { volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR; int i; @@ -150,9 +150,9 @@ void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot) /* * Release PCI RST Output signal. * Power on to RST high must be at least 100 ms as per PCI spec. - * On warm boots only 1 ms is required. + * On warm boots only 1 ms is required, but we play it safe. */ - udelay(warmboot ? 1000 : 100000); + udelay(100000); for (i = 0; i < num_buses; i++) immr->pci_ctrl[i].gcr = 1; diff --git a/arch/powerpc/cpu/mpc83xx/pcie.c b/arch/powerpc/cpu/mpc83xx/pcie.c index 77f8906..1771c48 100644 --- a/arch/powerpc/cpu/mpc83xx/pcie.c +++ b/arch/powerpc/cpu/mpc83xx/pcie.c @@ -30,6 +30,22 @@ DECLARE_GLOBAL_DATA_PTR; #define PCIE_MAX_BUSES 2 +static struct { + u32 base; + u32 size; +} mpc83xx_pcie_cfg_space[] = { + { + .base = CONFIG_SYS_PCIE1_CFG_BASE, + .size = CONFIG_SYS_PCIE1_CFG_SIZE, + }, +#if defined(CONFIG_SYS_PCIE2_CFG_BASE) && defined(CONFIG_SYS_PCIE2_CFG_SIZE) + { + .base = CONFIG_SYS_PCIE2_CFG_BASE, + .size = CONFIG_SYS_PCIE2_CFG_SIZE, + }, +#endif +}; + #ifdef CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES static int mpc83xx_pcie_remap_cfg(struct pci_controller *hose, pci_dev_t dev) @@ -124,10 +140,7 @@ static void mpc83xx_pcie_register_hose(int bus, struct pci_region *reg, hose->first_busno = pci_last_busno() + 1; hose->last_busno = 0xff; - if (bus == 0) - hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE1_CFG_BASE; - else - hose->cfg_addr = (unsigned int *)CONFIG_SYS_PCIE2_CFG_BASE; + hose->cfg_addr = (unsigned int *)mpc83xx_pcie_cfg_space[bus].base; pci_set_ops(hose, pcie_read_config_byte, @@ -182,15 +195,9 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) PEX_CSB_OBCTRL_CFGWE); out_win = &pex->bridge.pex_outbound_win[0]; - if (bus) { - out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | - CONFIG_SYS_PCIE2_CFG_SIZE); - out_le32(&out_win->bar, CONFIG_SYS_PCIE2_CFG_BASE); - } else { - out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | - CONFIG_SYS_PCIE1_CFG_SIZE); - out_le32(&out_win->bar, CONFIG_SYS_PCIE1_CFG_BASE); - } + out_le32(&out_win->ar, PEX_OWAR_EN | PEX_OWAR_TYPE_CFG | + mpc83xx_pcie_cfg_space[bus].size); + out_le32(&out_win->bar, mpc83xx_pcie_cfg_space[bus].base); out_le32(&out_win->tarl, 0); out_le32(&out_win->tarh, 0); @@ -301,16 +308,21 @@ static void mpc83xx_pcie_init_bus(int bus, struct pci_region *reg) * The caller must have already set SCCR, SERDES and the PCIE_LAW BARs * must have been set to cover all of the requested regions. */ -void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot) +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg) { int i; /* * Release PCI RST Output signal. * Power on to RST high must be at least 100 ms as per PCI spec. - * On warm boots only 1 ms is required. + * On warm boots only 1 ms is required, but we play it safe. */ - udelay(warmboot ? 1000 : 100000); + udelay(100000); + + if (num_buses > ARRAY_SIZE(mpc83xx_pcie_cfg_space)) { + printf("Second PCIE host contoller not configured!\n"); + num_buses = ARRAY_SIZE(mpc83xx_pcie_cfg_space); + } for (i = 0; i < num_buses; i++) mpc83xx_pcie_init_bus(i, reg[i]); diff --git a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c index f65cd88..a31b17e 100644 --- a/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c +++ b/arch/powerpc/cpu/ppc4xx/40x_spd_sdram.c @@ -45,7 +45,7 @@ #include <common.h> #include <asm/processor.h> #include <i2c.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_440) diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c index 005315b..ec7291f 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr.c @@ -50,7 +50,7 @@ #include <common.h> #include <asm/processor.h> #include <i2c.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/mmu.h> #include "ecc.h" diff --git a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c index ff5ef5f..cf9d66d 100644 --- a/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c @@ -41,7 +41,7 @@ #include <common.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <asm/io.h> #include <asm/processor.h> @@ -469,7 +469,7 @@ phys_size_t initdram(int board_type) /*------------------------------------------------------------------ * Reset the DDR-SDRAM controller. *-----------------------------------------------------------------*/ - mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, SDR0_SRST0_DMC); mtsdr(SDR0_SRST, 0x00000000); /* diff --git a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c index 2cfc37f..e90c93e 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c @@ -38,7 +38,7 @@ #undef DEBUG #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/io.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pci.c b/arch/powerpc/cpu/ppc4xx/4xx_pci.c index bfba952..80b0c1c 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pci.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pci.c @@ -594,35 +594,35 @@ int __pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(SD0_AMP1, reg); - mtsdr(SD0_AMP1, (reg & 0x000000FF) | 0x0000FF00); - reg = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, reg | 0x80000000); + mfsdr(SDR0_AMP1, reg); + mtsdr(SDR0_AMP1, (reg & 0x000000FF) | 0x0000FF00); + reg = mfdcr(PLB3A0_ACR); + mtdcr(PLB3A0_ACR, reg | 0x80000000); /* * Set priority for all PLB4 devices to 0. */ - mfsdr(SD0_AMP0, reg); - mtsdr(SD0_AMP0, (reg & 0x000000FF) | 0x0000FF00); - reg = mfdcr(PLB4_ACR) | 0xa0000000; - mtdcr(PLB4_ACR, reg); + mfsdr(SDR0_AMP0, reg); + mtsdr(SDR0_AMP0, (reg & 0x000000FF) | 0x0000FF00); + reg = mfdcr(PLB4A0_ACR) | 0xa0000000; + mtdcr(PLB4A0_ACR, reg); /* * Set Nebula PLB4 arbiter to fair mode. */ /* Segment0 */ - reg = (mfdcr(PLB0_ACR) & ~PLB0_ACR_PPM_MASK) | PLB0_ACR_PPM_FAIR; - reg = (reg & ~PLB0_ACR_HBU_MASK) | PLB0_ACR_HBU_ENABLED; - reg = (reg & ~PLB0_ACR_RDP_MASK) | PLB0_ACR_RDP_4DEEP; - reg = (reg & ~PLB0_ACR_WRP_MASK) | PLB0_ACR_WRP_2DEEP; - mtdcr(PLB0_ACR, reg); + reg = (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; + reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; + reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; + reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; + mtdcr(PLB4A0_ACR, reg); /* Segment1 */ - reg = (mfdcr(PLB1_ACR) & ~PLB1_ACR_PPM_MASK) | PLB1_ACR_PPM_FAIR; - reg = (reg & ~PLB1_ACR_HBU_MASK) | PLB1_ACR_HBU_ENABLED; - reg = (reg & ~PLB1_ACR_RDP_MASK) | PLB1_ACR_RDP_4DEEP; - reg = (reg & ~PLB1_ACR_WRP_MASK) | PLB1_ACR_WRP_2DEEP; - mtdcr(PLB1_ACR, reg); + reg = (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_PPM_MASK) | PLB4Ax_ACR_PPM_FAIR; + reg = (reg & ~PLB4Ax_ACR_HBU_MASK) | PLB4Ax_ACR_HBU_ENABLED; + reg = (reg & ~PLB4Ax_ACR_RDP_MASK) | PLB4Ax_ACR_RDP_4DEEP; + reg = (reg & ~PLB4Ax_ACR_WRP_MASK) | PLB4Ax_ACR_WRP_2DEEP; + mtdcr(PLB4A1_ACR, reg); #if defined(CONFIG_SYS_PCI_BOARD_FIXUP_IRQ) hose->fixup_irq = board_pci_fixup_irq; diff --git a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c index 10b58b7..b76890e 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_pcie.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_pcie.c @@ -27,7 +27,7 @@ #include <common.h> #include <pci.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/errno.h> diff --git a/arch/powerpc/cpu/ppc4xx/4xx_uart.c b/arch/powerpc/cpu/ppc4xx/4xx_uart.c index e6ab570..2660aa8 100644 --- a/arch/powerpc/cpu/ppc4xx/4xx_uart.c +++ b/arch/powerpc/cpu/ppc4xx/4xx_uart.c @@ -2,6 +2,9 @@ * (C) Copyright 2000-2006 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * * See file CREDITS for list of people who contributed to this * project. * @@ -49,15 +52,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <watchdog.h> -#include <ppc4xx.h> - -#ifdef CONFIG_SERIAL_MULTI -#include <serial.h> -#endif - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -#include <malloc.h> -#endif +#include <asm/ppc4xx.h> DECLARE_GLOBAL_DATA_PTR; @@ -66,24 +61,6 @@ DECLARE_GLOBAL_DATA_PTR; defined(CONFIG_405EX) || defined(CONFIG_440) #if defined(CONFIG_440) -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) -#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000400) -#else -#define UART0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000200) -#define UART1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000300) -#endif - -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) -#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define UART2_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000500) -#define UART3_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000600) -#endif #if defined(CONFIG_440GP) #define CR0_MASK 0x3fff0000 @@ -116,16 +93,14 @@ DECLARE_GLOBAL_DATA_PTR; #define MTREG(a, d) mtsdr(a, d) #endif /* #if defined(CONFIG_440GP) */ #elif defined(CONFIG_405EP) || defined(CONFIG_405EZ) -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 #define UCR0_MASK 0x0000007f #define UCR1_MASK 0x00007f00 #define UCR0_UDIV_POS 0 #define UCR1_UDIV_POS 8 #define UDIV_MAX 127 #elif defined(CONFIG_405EX) -#define UART0_BASE 0xef600200 -#define UART1_BASE 0xef600300 +#define MFREG(a, d) mfsdr(a, d) +#define MTREG(a, d) mtsdr(a, d) #define CR0_MASK 0x000000ff #define CR0_EXTCLK_ENA 0x00800000 #define CR0_UDIV_POS 0 @@ -133,748 +108,198 @@ DECLARE_GLOBAL_DATA_PTR; #define UART0_SDR SDR0_UART0 #define UART1_SDR SDR0_UART1 #else /* CONFIG_405GP || CONFIG_405CR */ -#define UART0_BASE 0xef600300 -#define UART1_BASE 0xef600400 #define CR0_MASK 0x00001fff #define CR0_EXTCLK_ENA 0x000000c0 #define CR0_UDIV_POS 1 #define UDIV_MAX 32 #endif -/* using serial port 0 or 1 as U-Boot console ? */ -#if defined(CONFIG_UART1_CONSOLE) -#define ACTING_UART0_BASE UART1_BASE -#define ACTING_UART1_BASE UART0_BASE -#else -#define ACTING_UART0_BASE UART0_BASE -#define ACTING_UART1_BASE UART1_BASE -#endif - #if defined(CONFIG_405EP) && defined(CONFIG_SYS_EXT_SERIAL_CLOCK) #error "External serial clock not supported on AMCC PPC405EP!" #endif -#define UART_RBR 0x00 -#define UART_THR 0x00 -#define UART_IER 0x01 -#define UART_IIR 0x02 -#define UART_FCR 0x02 -#define UART_LCR 0x03 -#define UART_MCR 0x04 -#define UART_LSR 0x05 -#define UART_MSR 0x06 -#define UART_SCR 0x07 -#define UART_DLL 0x00 -#define UART_DLM 0x01 - -/*-----------------------------------------------------------------------------+ - | Line Status Register. - +-----------------------------------------------------------------------------*/ -#define asyncLSRDataReady1 0x01 -#define asyncLSROverrunError1 0x02 -#define asyncLSRParityError1 0x04 -#define asyncLSRFramingError1 0x08 -#define asyncLSRBreakInterrupt1 0x10 -#define asyncLSRTxHoldEmpty1 0x20 -#define asyncLSRTxShiftEmpty1 0x40 -#define asyncLSRRxFifoError1 0x80 - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -/*-----------------------------------------------------------------------------+ - | Fifo - +-----------------------------------------------------------------------------*/ -typedef struct { - char *rx_buffer; - ulong rx_put; - ulong rx_get; -} serial_buffer_t; - -volatile static serial_buffer_t buf_info; -#endif - -static void serial_init_common(u32 base, u32 udiv, u16 bdiv) -{ - PPC4xx_SYS_INFO sys_info; - u8 val; - - get_sys_info(&sys_info); - - /* Correct UART frequency in bd-info struct now that - * the UART divisor is available - */ -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; -#else - gd->uart_clk = sys_info.freqUART / udiv; -#endif - - out_8((u8 *)base + UART_LCR, 0x80); /* set DLAB bit */ - out_8((u8 *)base + UART_DLL, bdiv); /* set baudrate divisor */ - out_8((u8 *)base + UART_DLM, bdiv >> 8); /* set baudrate divisor */ - out_8((u8 *)base + UART_LCR, 0x03); /* clear DLAB; set 8 bits, no parity */ - out_8((u8 *)base + UART_FCR, 0x00); /* disable FIFO */ - out_8((u8 *)base + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((u8 *)base + UART_LSR); /* clear line status */ - val = in_8((u8 *)base + UART_RBR); /* read receive buffer */ - out_8((u8 *)base + UART_SCR, 0x00); /* set scratchpad */ - out_8((u8 *)base + UART_IER, 0x00); /* set interrupt enable reg */ -} - -#if (defined(CONFIG_440) || defined(CONFIG_405EX)) && \ - !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) +#if (defined(CONFIG_405EX) || defined(CONFIG_405EZ) || \ + defined(CONFIG_440)) && !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) +/* + * For some SoC's, the cpu clock is on divider chain A, UART on + * divider chain B ... so cpu clock is irrelevant. Get the + * "optimized" values that are subject to the 1/2 opb clock + * constraint. + */ +static u16 serial_bdiv(int baudrate, u32 *udiv) { sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ + u32 div; /* total divisor udiv * bdiv */ + u32 umin; /* minimum udiv */ + u16 diff; /* smallest diff */ + u16 idiff; /* current diff */ + u16 ibdiv; /* current bdiv */ + u32 i; + u32 est; /* current estimate */ + u32 max; +#if defined(CONFIG_405EZ) + u32 cpr_pllc; + u32 plloutb; + u32 reg; +#endif get_sys_info(&sysinfo); - udiv = 32; /* Assume lowest possible serial clk */ - div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ - umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ - diff = 32; /* highest possible */ - - /* i is the test udiv value -- start with the largest - * possible (32) to minimize serial clock and constrain - * search to umin. - */ - for (i = 32; i > umin; i--) { - ibdiv = div / i; - est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); - if (idiff == 0) { - udiv = i; - break; /* can't do better */ - } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ - } - } - - *pudiv = udiv; - *pbdiv = div / udiv; -} - -#elif defined(CONFIG_405EZ) - -static void serial_divs (int baudrate, unsigned long *pudiv, - unsigned short *pbdiv) -{ - sys_info_t sysinfo; - unsigned long div; /* total divisor udiv * bdiv */ - unsigned long umin; /* minimum udiv */ - unsigned short diff; /* smallest diff */ - unsigned long udiv; /* best udiv */ - unsigned short idiff; /* current diff */ - unsigned short ibdiv; /* current bdiv */ - unsigned long i; - unsigned long est; /* current estimate */ - unsigned long plloutb; - unsigned long cpr_pllc; - u32 reg; - +#if defined(CONFIG_405EZ) /* check the pll feedback source */ mfcpr(CPR0_PLLC, cpr_pllc); - - get_sys_info(&sysinfo); - plloutb = ((CONFIG_SYS_CLK_FREQ * ((cpr_pllc & PLLC_SRC_MASK) ? sysinfo.pllFwdDivB : sysinfo.pllFwdDiv) * sysinfo.pllFbkDiv) / sysinfo.pllFwdDivB); - udiv = 256; /* Assume lowest possible serial clk */ div = plloutb / (16 * baudrate); /* total divisor */ umin = (plloutb / get_OPB_freq()) << 1; /* 2 x OPB divisor */ - diff = 256; /* highest possible */ + max = 256; /* highest possible */ +#else /* 405EZ */ + div = sysinfo.freqPLB / (16 * baudrate); /* total divisor */ + umin = sysinfo.pllOpbDiv << 1; /* 2 x OPB divisor */ + max = 32; /* highest possible */ +#endif /* 405EZ */ + + *udiv = diff = max; - /* i is the test udiv value -- start with the largest - * possible (256) to minimize serial clock and constrain + /* + * i is the test udiv value -- start with the largest + * possible (max) to minimize serial clock and constrain * search to umin. */ - for (i = 256; i > umin; i--) { + for (i = max; i > umin; i--) { ibdiv = div / i; est = i * ibdiv; - idiff = (est > div) ? (est-div) : (div-est); + idiff = (est > div) ? (est - div) : (div - est); if (idiff == 0) { - udiv = i; - break; /* can't do better */ + *udiv = i; + break; /* can't do better */ } else if (idiff < diff) { - udiv = i; /* best so far */ - diff = idiff; /* update lowest diff*/ + *udiv = i; /* best so far */ + diff = idiff; /* update lowest diff*/ } } - *pudiv = udiv; - mfcpr(CPC0_PERD0, reg); +#if defined(CONFIG_405EZ) + mfcpr(CPR0_PERD0, reg); reg &= ~0x0000ffff; - reg |= ((udiv - 0) << 8) | (udiv - 0); - mtcpr(CPC0_PERD0, reg); - *pbdiv = div / udiv; + reg |= ((*udiv - 0) << 8) | (*udiv - 0); + mtcpr(CPR0_PERD0, reg); +#endif + + return div / *udiv; } -#endif /* defined(CONFIG_440) && !defined(CONFIG_SYS_EXT_SERIAL_CLK) */ +#endif /* #if (defined(CONFIG_405EP) ... */ /* - * Minimal serial functions needed to use one of the SMC ports - * as serial console interface. + * This function returns the UART clock used by the common + * NS16550 driver. Additionally the SoC internal divisors for + * optimal UART baudrate are configured. */ - -#if defined(CONFIG_440) -int serial_init_dev(unsigned long base) +int get_serial_clock(void) { - unsigned long reg; - unsigned long udiv; - unsigned short bdiv; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - unsigned long tmp; -#endif - - MFREG(UART0_SDR, reg); - reg &= ~CR0_MASK; - -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - /* For 440, the cpu clock is on divider chain A, UART on divider - * chain B ... so cpu clock is irrelevant. Get the "optimized" - * values that are subject to the 1/2 opb clock constraint - */ - serial_divs (gd->baudrate, &udiv, &bdiv); + u32 clk; + u32 udiv; +#if defined(CONFIG_405CR) || defined(CONFIG_405EP) || defined(CONFIG_405GP) + u32 tmp; #endif - - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - - /* - * Configure input clock to baudrate generator for all - * available serial ports here - */ - MTREG(UART0_SDR, reg); -#if defined(UART1_SDR) - MTREG(UART1_SDR, reg); -#endif -#if defined(UART2_SDR) - MTREG(UART2_SDR, reg); -#endif -#if defined(UART3_SDR) - MTREG(UART3_SDR, reg); +#if !defined(CONFIG_405EZ) + u32 reg; #endif - - serial_init_common(base, udiv, bdiv); - - return (0); -} - -#else /* !defined(CONFIG_440) */ - -int serial_init_dev (unsigned long base) -{ - unsigned long reg; - unsigned long tmp; - unsigned long clk; - unsigned long udiv; - unsigned short bdiv; - -#ifdef CONFIG_405EX - clk = tmp = 0; - mfsdr(UART0_SDR, reg); - reg &= ~CR0_MASK; -#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK - reg |= CR0_EXTCLK_ENA; - udiv = 1; - tmp = gd->baudrate * 16; - bdiv = (CONFIG_SYS_EXT_SERIAL_CLOCK + tmp / 2) / tmp; -#else - serial_divs(gd->baudrate, &udiv, &bdiv); +#if !defined(CONFIG_SYS_EXT_SERIAL_CLOCK) + PPC4xx_SYS_INFO sys_info; #endif - reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ /* - * Configure input clock to baudrate generator for all - * available serial ports here + * Programming of the internal divisors is SoC specific. + * Let's handle this in some #ifdef's for the SoC's. */ - mtsdr(UART0_SDR, reg); - -#if defined(UART1_SDR) - mtsdr(UART1_SDR, reg); -#endif -#elif defined(CONFIG_405EZ) - serial_divs(gd->baudrate, &udiv, &bdiv); - clk = tmp = reg = 0; -#else -#ifdef CONFIG_405EP - reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); - clk = gd->cpu_clk; - tmp = CONFIG_SYS_BASE_BAUD * 16; - udiv = (clk + tmp / 2) / tmp; - if (udiv > UDIV_MAX) /* max. n bits for udiv */ - udiv = UDIV_MAX; - reg |= (udiv) << UCR0_UDIV_POS; /* set the UART divisor */ - reg |= (udiv) << UCR1_UDIV_POS; /* set the UART divisor */ - mtdcr (CPC0_UCR, reg); -#else /* CONFIG_405EP */ +#if defined(CONFIG_405CR) || defined(CONFIG_405GP) + tmp = 0; reg = mfdcr(CPC0_CR0) & ~CR0_MASK; #ifdef CONFIG_SYS_EXT_SERIAL_CLOCK clk = CONFIG_SYS_EXT_SERIAL_CLOCK; udiv = 1; reg |= CR0_EXTCLK_ENA; -#else +#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ clk = gd->cpu_clk; #ifdef CONFIG_SYS_405_UART_ERRATA_59 udiv = 31; /* Errata 59: stuck at 31 */ -#else +#else /* CONFIG_SYS_405_UART_ERRATA_59 */ tmp = CONFIG_SYS_BASE_BAUD * 16; udiv = (clk + tmp / 2) / tmp; if (udiv > UDIV_MAX) /* max. n bits for udiv */ udiv = UDIV_MAX; -#endif -#endif +#endif /* CONFIG_SYS_405_UART_ERRATA_59 */ +#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ reg |= (udiv - 1) << CR0_UDIV_POS; /* set the UART divisor */ mtdcr (CPC0_CR0, reg); -#endif /* CONFIG_405EP */ - tmp = gd->baudrate * udiv * 16; - bdiv = (clk + tmp / 2) / tmp; -#endif /* CONFIG_405EX */ - - serial_init_common(base, udiv, bdiv); - - return (0); -} - -#endif /* if defined(CONFIG_440) */ - -void serial_setbrg_dev(unsigned long base) -{ - serial_init_dev(base); -} - -void serial_putc_dev(unsigned long base, const char c) -{ - int i; - - if (c == '\n') - serial_putc_dev(base, '\r'); - - /* check THRE bit, wait for transmiter available */ - for (i = 1; i < 3500; i++) { - if ((in_8((u8 *)base + UART_LSR) & 0x20) == 0x20) - break; - udelay (100); - } - - out_8((u8 *)base + UART_THR, c); /* put character out */ -} - -void serial_puts_dev (unsigned long base, const char *s) -{ - while (*s) - serial_putc_dev (base, *s++); -} - -int serial_getc_dev (unsigned long base) -{ - unsigned char status = 0; - - while (1) { -#if defined(CONFIG_HW_WATCHDOG) - WATCHDOG_RESET (); /* Reset HW Watchdog, if needed */ -#endif /* CONFIG_HW_WATCHDOG */ - - status = in_8((u8 *)base + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - break; - - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - - return (0x000000ff & (int) in_8((u8 *)base)); -} - -int serial_tstc_dev (unsigned long base) -{ - unsigned char status; - - status = in_8((u8 *)base + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - return (1); - - if ((status & ( asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)base + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - - return 0; -} - -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - -void serial_isr (void *arg) -{ - int space; - int c; - const int rx_get = buf_info.rx_get; - int rx_put = buf_info.rx_put; - - if (rx_get <= rx_put) - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - else - space = rx_get - rx_put; - - while (serial_tstc_dev (ACTING_UART0_BASE)) { - c = serial_getc_dev (ACTING_UART0_BASE); - if (space) { - buf_info.rx_buffer[rx_put++] = c; - space--; - } - if (rx_put == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_put = 0; - if (space < CONFIG_SERIAL_SOFTWARE_FIFO / 4) { - /* Stop flow by setting RTS inactive */ - out_8((u8 *)ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) & - (0xFF ^ 0x02)); - } - } - buf_info.rx_put = rx_put; -} - -void serial_buffered_init (void) -{ - serial_puts ("Switching to interrupt driven serial input mode.\n"); - buf_info.rx_buffer = malloc (CONFIG_SERIAL_SOFTWARE_FIFO); - buf_info.rx_put = 0; - buf_info.rx_get = 0; - - if (in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10) - serial_puts ("Check CTS signal present on serial port: OK.\n"); - else - serial_puts ("WARNING: CTS signal not present on serial port.\n"); - - irq_install_handler ( VECNUM_U0 /*UART0 */ /*int vec */ , - serial_isr /*interrupt_handler_t *handler */ , - (void *) &buf_info /*void *arg */ ); - - /* Enable "RX Data Available" Interrupt on UART */ - out_8(ACTING_UART0_BASE + UART_IER, 0x01); - /* Set DTR active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x01); - /* Start flow by setting RTS active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); - /* Setup UART FIFO: RX trigger level: 4 byte, Enable FIFO */ - out_8(ACTING_UART0_BASE + UART_FCR, (1 << 6) | 1); -} - -void serial_buffered_putc (const char c) -{ - /* Wait for CTS */ -#if defined(CONFIG_HW_WATCHDOG) - while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)) - WATCHDOG_RESET (); -#else - while (!(in_8((u8 *)ACTING_UART0_BASE + UART_MSR) & 0x10)); -#endif - serial_putc (c); -} - -void serial_buffered_puts (const char *s) -{ - serial_puts (s); -} - -int serial_buffered_getc (void) -{ - int space; - int c; - int rx_get = buf_info.rx_get; - int rx_put; - -#if defined(CONFIG_HW_WATCHDOG) - while (rx_get == buf_info.rx_put) - WATCHDOG_RESET (); +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else - while (rx_get == buf_info.rx_put); + clk = CONFIG_SYS_BASE_BAUD * 16; #endif - c = buf_info.rx_buffer[rx_get++]; - if (rx_get == CONFIG_SERIAL_SOFTWARE_FIFO) - rx_get = 0; - buf_info.rx_get = rx_get; - - rx_put = buf_info.rx_put; - if (rx_get <= rx_put) - space = CONFIG_SERIAL_SOFTWARE_FIFO - (rx_put - rx_get); - else - space = rx_get - rx_put; - - if (space > CONFIG_SERIAL_SOFTWARE_FIFO / 2) { - /* Start flow by setting RTS active */ - out_8(ACTING_UART0_BASE + UART_MCR, - in_8((u8 *)ACTING_UART0_BASE + UART_MCR) | 0x02); - } +#endif /* CONFIG_405CR */ - return c; -} +#if defined(CONFIG_405EP) + reg = mfdcr(CPC0_UCR) & ~(UCR0_MASK | UCR1_MASK); + clk = gd->cpu_clk; + tmp = CONFIG_SYS_BASE_BAUD * 16; + udiv = (clk + tmp / 2) / tmp; + if (udiv > UDIV_MAX) /* max. n bits for udiv */ + udiv = UDIV_MAX; + reg |= udiv << UCR0_UDIV_POS; /* set the UART divisor */ + reg |= udiv << UCR1_UDIV_POS; /* set the UART divisor */ + mtdcr(CPC0_UCR, reg); + clk = CONFIG_SYS_BASE_BAUD * 16; +#endif /* CONFIG_405EP */ -int serial_buffered_tstc (void) -{ - return (buf_info.rx_get != buf_info.rx_put) ? 1 : 0; -} +#if defined(CONFIG_405EX) || defined(CONFIG_440) + MFREG(UART0_SDR, reg); + reg &= ~CR0_MASK; -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + reg |= CR0_EXTCLK_ENA; + udiv = 1; + clk = CONFIG_SYS_EXT_SERIAL_CLOCK; +#else /* CONFIG_SYS_EXT_SERIAL_CLOCK */ + clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; +#endif /* CONFIG_SYS_EXT_SERIAL_CLOCK */ -#if defined(CONFIG_CMD_KGDB) -/* - AS HARNOIS : according to CONFIG_KGDB_SER_INDEX kgdb uses serial port - number 0 or number 1 - - if CONFIG_KGDB_SER_INDEX = 1 => serial port number 0 : - configuration has been already done - - if CONFIG_KGDB_SER_INDEX = 2 => serial port number 1 : - configure port 1 for serial I/O with rate = CONFIG_KGDB_BAUDRATE -*/ -#if (CONFIG_KGDB_SER_INDEX & 2) -void kgdb_serial_init (void) -{ - u8 val; - u16 br_reg; + reg |= (udiv - UDIV_SUBTRACT) << CR0_UDIV_POS; /* set the UART divisor */ - get_clocks (); - br_reg = (((((gd->cpu_clk / 16) / 18) * 10) / CONFIG_KGDB_BAUDRATE) + - 5) / 10; /* - * Init onboard 16550 UART + * Configure input clock to baudrate generator for all + * available serial ports here */ - out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x80); /* set DLAB bit */ - out_8((u8 *)ACTING_UART1_BASE + UART_DLL, (br_reg & 0x00ff)); /* set divisor for 9600 baud */ - out_8((u8 *)ACTING_UART1_BASE + UART_DLM, ((br_reg & 0xff00) >> 8)); /* set divisor for 9600 baud */ - out_8((u8 *)ACTING_UART1_BASE + UART_LCR, 0x03); /* line control 8 bits no parity */ - out_8((u8 *)ACTING_UART1_BASE + UART_FCR, 0x00); /* disable FIFO */ - out_8((u8 *)ACTING_UART1_BASE + UART_MCR, 0x00); /* no modem control DTR RTS */ - val = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); /* clear line status */ - val = in_8((u8 *)ACTING_UART1_BASE + UART_RBR); /* read receive buffer */ - out_8((u8 *)ACTING_UART1_BASE + UART_SCR, 0x00); /* set scratchpad */ - out_8((u8 *)ACTING_UART1_BASE + UART_IER, 0x00); /* set interrupt enable reg */ -} - -void putDebugChar (const char c) -{ - if (c == '\n') - serial_putc ('\r'); - - out_8((u8 *)ACTING_UART1_BASE + UART_THR, c); /* put character out */ - - /* check THRE bit, wait for transfer done */ - while ((in_8((u8 *)ACTING_UART1_BASE + UART_LSR) & 0x20) != 0x20); -} - -void putDebugStr (const char *s) -{ - while (*s) - serial_putc (*s++); -} - -int getDebugChar (void) -{ - unsigned char status = 0; - - while (1) { - status = in_8((u8 *)ACTING_UART1_BASE + UART_LSR); - if ((status & asyncLSRDataReady1) != 0x0) - break; - - if ((status & (asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1 )) != 0) { - out_8((u8 *)ACTING_UART1_BASE + UART_LSR, - asyncLSRFramingError1 | - asyncLSROverrunError1 | - asyncLSRParityError1 | - asyncLSRBreakInterrupt1); - } - } - - return (0x000000ff & (int) in_8((u8 *)ACTING_UART1_BASE)); -} - -void kgdb_interruptible (int yes) -{ - return; -} - -#else /* ! (CONFIG_KGDB_SER_INDEX & 2) */ - -void kgdb_serial_init (void) -{ - serial_printf ("[on serial] "); -} - -void putDebugChar (int c) -{ - serial_putc (c); -} - -void putDebugStr (const char *str) -{ - serial_puts (str); -} - -int getDebugChar (void) -{ - return serial_getc (); -} - -void kgdb_interruptible (int yes) -{ - return; -} -#endif /* (CONFIG_KGDB_SER_INDEX & 2) */ + MTREG(UART0_SDR, reg); +#if defined(UART1_SDR) + MTREG(UART1_SDR, reg); #endif +#if defined(UART2_SDR) + MTREG(UART2_SDR, reg); +#endif +#if defined(UART3_SDR) + MTREG(UART3_SDR, reg); +#endif +#endif /* CONFIG_405EX ... */ +#if defined(CONFIG_405EZ) + clk = gd->baudrate * serial_bdiv(gd->baudrate, &udiv) * 16; +#endif /* CONFIG_405EZ */ -#if defined(CONFIG_SERIAL_MULTI) -int serial0_init(void) -{ - return (serial_init_dev(UART0_BASE)); -} - -int serial1_init(void) -{ - return (serial_init_dev(UART1_BASE)); -} - -void serial0_setbrg (void) -{ - serial_setbrg_dev(UART0_BASE); -} - -void serial1_setbrg (void) -{ - serial_setbrg_dev(UART1_BASE); -} - -void serial0_putc(const char c) -{ - serial_putc_dev(UART0_BASE,c); -} - -void serial1_putc(const char c) -{ - serial_putc_dev(UART1_BASE, c); -} - -void serial0_puts(const char *s) -{ - serial_puts_dev(UART0_BASE, s); -} - -void serial1_puts(const char *s) -{ - serial_puts_dev(UART1_BASE, s); -} - -int serial0_getc(void) -{ - return(serial_getc_dev(UART0_BASE)); -} - -int serial1_getc(void) -{ - return(serial_getc_dev(UART1_BASE)); -} - -int serial0_tstc(void) -{ - return (serial_tstc_dev(UART0_BASE)); -} - -int serial1_tstc(void) -{ - return (serial_tstc_dev(UART1_BASE)); -} - -struct serial_device serial0_device = -{ - "serial0", - "UART0", - serial0_init, - NULL, - serial0_setbrg, - serial0_getc, - serial0_tstc, - serial0_putc, - serial0_puts, -}; - -struct serial_device serial1_device = -{ - "serial1", - "UART1", - serial1_init, - NULL, - serial1_setbrg, - serial1_getc, - serial1_tstc, - serial1_putc, - serial1_puts, -}; + /* + * Correct UART frequency in bd-info struct now that + * the UART divisor is available + */ +#ifdef CONFIG_SYS_EXT_SERIAL_CLOCK + gd->uart_clk = CONFIG_SYS_EXT_SERIAL_CLOCK; #else -/* - * Wrapper functions - */ -int serial_init(void) -{ - return serial_init_dev(ACTING_UART0_BASE); -} - -void serial_setbrg(void) -{ - serial_setbrg_dev(ACTING_UART0_BASE); -} - -void serial_putc(const char c) -{ - serial_putc_dev(ACTING_UART0_BASE, c); -} - -void serial_puts(const char *s) -{ - serial_puts_dev(ACTING_UART0_BASE, s); -} - -int serial_getc(void) -{ - return serial_getc_dev(ACTING_UART0_BASE); -} + get_sys_info(&sys_info); + gd->uart_clk = sys_info.freqUART / udiv; +#endif -int serial_tstc(void) -{ - return serial_tstc_dev(ACTING_UART0_BASE); + return clk; } -#endif /* CONFIG_SERIAL_MULTI */ - #endif /* CONFIG_405GP || CONFIG_405CR */ diff --git a/arch/powerpc/cpu/ppc4xx/cache.S b/arch/powerpc/cpu/ppc4xx/cache.S index 269716f..757d7da 100644 --- a/arch/powerpc/cpu/ppc4xx/cache.S +++ b/arch/powerpc/cpu/ppc4xx/cache.S @@ -14,7 +14,7 @@ #include <config.h> #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> diff --git a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c index b4eac40..fd81b70 100644 --- a/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c +++ b/arch/powerpc/cpu/ppc4xx/cmd_ecctest.c @@ -23,7 +23,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/cache.h> diff --git a/arch/powerpc/cpu/ppc4xx/cpu.c b/arch/powerpc/cpu/ppc4xx/cpu.c index 851065c..6009b0c 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu.c +++ b/arch/powerpc/cpu/ppc4xx/cpu.c @@ -35,7 +35,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <netdev.h> DECLARE_GLOBAL_DATA_PTR; @@ -98,8 +98,8 @@ int pci_arbiter_enabled(void) #if defined(CONFIG_440GX) || defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long val; - mfsdr(SDR0_XCR, val); - return (val & 0x80000000); + mfsdr(SDR0_XCR0, val); + return (val & SDR0_XCR0_PAE_MASK); #endif #if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ @@ -107,7 +107,7 @@ int pci_arbiter_enabled(void) unsigned long val; mfsdr(SDR0_PCI0, val); - return (val & 0x80000000); + return (val & SDR0_PCI0_PAE_MASK); #endif } #endif @@ -262,7 +262,7 @@ static int bootstrap_option(void) #endif /* SDR0_PINSTP_SHIFT */ -#if defined(CONFIG_440) +#if defined(CONFIG_440GP) static int do_chip_reset (unsigned long sys0, unsigned long sys1) { /* Changes to CPC0_SYS0 and CPC0_SYS1 require chip @@ -276,7 +276,7 @@ static int do_chip_reset (unsigned long sys0, unsigned long sys1) return 1; } -#endif +#endif /* CONFIG_440GP */ int checkcpu (void) @@ -303,122 +303,113 @@ int checkcpu (void) get_sys_info(&sys_info); #if defined(CONFIG_XILINX_440) - puts("IBM PowerPC 4"); + puts("IBM PowerPC "); #else - puts("AMCC PowerPC 4"); -#endif - -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || \ - defined(CONFIG_405EP) || defined(CONFIG_405EZ) || \ - defined(CONFIG_405EX) - puts("05"); -#endif -#if defined(CONFIG_440) -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) - puts("60"); -#else - puts("40"); -#endif + puts("AMCC PowerPC "); #endif switch (pvr) { + +#if !defined(CONFIG_440) case PVR_405GP_RB: - puts("GP Rev. B"); + puts("405GP Rev. B"); break; case PVR_405GP_RC: - puts("GP Rev. C"); + puts("405GP Rev. C"); break; case PVR_405GP_RD: - puts("GP Rev. D"); + puts("405GP Rev. D"); break; #ifdef CONFIG_405GP case PVR_405GP_RE: /* 405GP rev E and 405CR rev C have same PVR */ - puts("GP Rev. E"); + puts("405GP Rev. E"); break; #endif case PVR_405CR_RA: - puts("CR Rev. A"); + puts("405CR Rev. A"); break; case PVR_405CR_RB: - puts("CR Rev. B"); + puts("405CR Rev. B"); break; #ifdef CONFIG_405CR case PVR_405CR_RC: /* 405GP rev E and 405CR rev C have same PVR */ - puts("CR Rev. C"); + puts("405CR Rev. C"); break; #endif case PVR_405GPR_RB: - puts("GPr Rev. B"); + puts("405GPr Rev. B"); break; case PVR_405EP_RB: - puts("EP Rev. B"); + puts("405EP Rev. B"); break; case PVR_405EZ_RA: - puts("EZ Rev. A"); + puts("405EZ Rev. A"); break; case PVR_405EX1_RA: - puts("EX Rev. A"); + puts("405EX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RA: - puts("EXr Rev. A"); + puts("405EXr Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_405EX1_RC: - puts("EX Rev. C"); + puts("405EX Rev. C"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RC: - puts("EX Rev. C"); + puts("405EX Rev. C"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RC: - puts("EXr Rev. C"); + puts("405EXr Rev. C"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RC: - puts("EXr Rev. C"); + puts("405EXr Rev. C"); strcpy(addstr, "No Security support"); break; case PVR_405EX1_RD: - puts("EX Rev. D"); + puts("405EX Rev. D"); strcpy(addstr, "Security support"); break; case PVR_405EX2_RD: - puts("EX Rev. D"); + puts("405EX Rev. D"); strcpy(addstr, "No Security support"); break; case PVR_405EXR1_RD: - puts("EXr Rev. D"); + puts("405EXr Rev. D"); strcpy(addstr, "Security support"); break; case PVR_405EXR2_RD: - puts("EXr Rev. D"); + puts("405EXr Rev. D"); strcpy(addstr, "No Security support"); break; -#if defined(CONFIG_440) +#else /* CONFIG_440 */ + +#if defined(CONFIG_440GP) case PVR_440GP_RB: - puts("GP Rev. B"); + puts("440GP Rev. B"); /* See errata 1.12: CHIP_4 */ if ((mfdcr(CPC0_SYS0) != mfdcr(CPC0_STRP0)) || (mfdcr(CPC0_SYS1) != mfdcr(CPC0_STRP1)) ){ @@ -431,127 +422,127 @@ int checkcpu (void) break; case PVR_440GP_RC: - puts("GP Rev. C"); + puts("440GP Rev. C"); break; +#endif /* CONFIG_440GP */ case PVR_440GX_RA: - puts("GX Rev. A"); + puts("440GX Rev. A"); break; case PVR_440GX_RB: - puts("GX Rev. B"); + puts("440GX Rev. B"); break; case PVR_440GX_RC: - puts("GX Rev. C"); + puts("440GX Rev. C"); break; case PVR_440GX_RF: - puts("GX Rev. F"); + puts("440GX Rev. F"); break; case PVR_440EP_RA: - puts("EP Rev. A"); + puts("440EP Rev. A"); break; #ifdef CONFIG_440EP case PVR_440EP_RB: /* 440EP rev B and 440GR rev A have same PVR */ - puts("EP Rev. B"); + puts("440EP Rev. B"); break; case PVR_440EP_RC: /* 440EP rev C and 440GR rev B have same PVR */ - puts("EP Rev. C"); + puts("440EP Rev. C"); break; #endif /* CONFIG_440EP */ #ifdef CONFIG_440GR case PVR_440GR_RA: /* 440EP rev B and 440GR rev A have same PVR */ - puts("GR Rev. A"); + puts("440GR Rev. A"); break; case PVR_440GR_RB: /* 440EP rev C and 440GR rev B have same PVR */ - puts("GR Rev. B"); + puts("440GR Rev. B"); break; #endif /* CONFIG_440GR */ -#endif /* CONFIG_440 */ #ifdef CONFIG_440EPX case PVR_440EPX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); + puts("440EPx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440EPX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("EPx Rev. A"); + puts("440EPx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440EPX */ #ifdef CONFIG_440GRX case PVR_440GRX1_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); + puts("440GRx Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_440GRX2_RA: /* 440EPx rev A and 440GRx rev A have same PVR */ - puts("GRx Rev. A"); + puts("440GRx Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; #endif /* CONFIG_440GRX */ case PVR_440SP_6_RAB: - puts("SP Rev. A/B"); + puts("440SP Rev. A/B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RAB: - puts("SP Rev. A/B"); + puts("440SP Rev. A/B"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SP_6_RC: - puts("SP Rev. C"); + puts("440SP Rev. C"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SP_RC: - puts("SP Rev. C"); + puts("440SP Rev. C"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RA: - puts("SPe Rev. A"); + puts("440SPe Rev. A"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RA: - puts("SPe Rev. A"); + puts("440SPe Rev. A"); strcpy(addstr, "No RAID 6 support"); break; case PVR_440SPe_6_RB: - puts("SPe Rev. B"); + puts("440SPe Rev. B"); strcpy(addstr, "RAID 6 support"); break; case PVR_440SPe_RB: - puts("SPe Rev. B"); + puts("440SPe Rev. B"); strcpy(addstr, "No RAID 6 support"); break; #if defined(CONFIG_460EX) || defined(CONFIG_460GT) case PVR_460EX_RA: - puts("EX Rev. A"); + puts("460EX Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; case PVR_460EX_SE_RA: - puts("EX Rev. A"); + puts("460EX Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_460EX_RB: - puts("EX Rev. B"); + puts("460EX Rev. B"); mfsdr(SDR0_ECID3, reg); if (reg & 0x00100000) strcpy(addstr, "No Security/Kasumi support"); @@ -560,17 +551,17 @@ int checkcpu (void) break; case PVR_460GT_RA: - puts("GT Rev. A"); + puts("460GT Rev. A"); strcpy(addstr, "No Security/Kasumi support"); break; case PVR_460GT_SE_RA: - puts("GT Rev. A"); + puts("460GT Rev. A"); strcpy(addstr, "Security/Kasumi support"); break; case PVR_460GT_RB: - puts("GT Rev. B"); + puts("460GT Rev. B"); mfsdr(SDR0_ECID3, reg); if (reg & 0x00100000) strcpy(addstr, "No Security/Kasumi support"); @@ -580,28 +571,29 @@ int checkcpu (void) #endif case PVR_460SX_RA: - puts("SX Rev. A"); + puts("460SX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_460SX_RA_V1: - puts("SX Rev. A"); + puts("460SX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_460GX_RA: - puts("GX Rev. A"); + puts("460GX Rev. A"); strcpy(addstr, "Security support"); break; case PVR_460GX_RA_V1: - puts("GX Rev. A"); + puts("460GX Rev. A"); strcpy(addstr, "No Security support"); break; case PVR_VIRTEX5: - puts("x5 VIRTEX5"); + puts("440x5 VIRTEX5"); break; +#endif /* CONFIG_440 */ default: printf (" UNKNOWN (PVR=%08x)", pvr); diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c index b31bd0b..d54b30e 100644 --- a/arch/powerpc/cpu/ppc4xx/cpu_init.c +++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c @@ -23,10 +23,10 @@ #include <common.h> #include <watchdog.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> #include <asm/processor.h> -#include <asm/gpio.h> -#include <ppc4xx.h> +#include <asm/ppc4xx-gpio.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_405GP) || defined(CONFIG_405EP) DECLARE_GLOBAL_DATA_PTR; @@ -266,7 +266,7 @@ cpu_init_f (void) /* * Set EMAC noise filter bits */ - mtdcr(CPC0_EPCTL, CPC0_EPRCSR_E0NFE | CPC0_EPRCSR_E1NFE); + mtdcr(CPC0_EPCTL, CPC0_EPCTL_E0NFE | CPC0_EPCTL_E1NFE); #endif /* CONFIG_405EP */ #if defined(CONFIG_SYS_4xx_GPIO_TABLE) @@ -397,10 +397,10 @@ cpu_init_f (void) /* * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read */ - mtdcr(PLB0_ACR, (mfdcr(PLB0_ACR) & ~PLB0_ACR_RDP_MASK) | - PLB0_ACR_RDP_4DEEP); - mtdcr(PLB1_ACR, (mfdcr(PLB1_ACR) & ~PLB1_ACR_RDP_MASK) | - PLB1_ACR_RDP_4DEEP); + mtdcr(PLB4A0_ACR, (mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); + mtdcr(PLB4A1_ACR, (mfdcr(PLB4A1_ACR) & ~PLB4Ax_ACR_RDP_MASK) | + PLB4Ax_ACR_RDP_4DEEP); #endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } diff --git a/arch/powerpc/cpu/ppc4xx/dcr.S b/arch/powerpc/cpu/ppc4xx/dcr.S index 93465a3..e668e05 100644 --- a/arch/powerpc/cpu/ppc4xx/dcr.S +++ b/arch/powerpc/cpu/ppc4xx/dcr.S @@ -24,7 +24,7 @@ #if defined(CONFIG_4xx) && defined(CONFIG_CMD_SETGETDCR) -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c index 03b8d3c..9bba0ca 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_data_eye.c +++ b/arch/powerpc/cpu/ppc4xx/denali_data_eye.c @@ -36,7 +36,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) /*-----------------------------------------------------------------------------+ diff --git a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c index 080ea0a..c35b113 100644 --- a/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c +++ b/arch/powerpc/cpu/ppc4xx/denali_spd_ddr2.c @@ -40,7 +40,7 @@ #include <common.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <asm/io.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/ecc.c b/arch/powerpc/cpu/ppc4xx/ecc.c index 49f28d9..7fe5dbb 100644 --- a/arch/powerpc/cpu/ppc4xx/ecc.c +++ b/arch/powerpc/cpu/ppc4xx/ecc.c @@ -37,7 +37,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/processor.h> diff --git a/arch/powerpc/cpu/ppc4xx/fdt.c b/arch/powerpc/cpu/ppc4xx/fdt.c index e99b2b0..5ddb880 100644 --- a/arch/powerpc/cpu/ppc4xx/fdt.c +++ b/arch/powerpc/cpu/ppc4xx/fdt.c @@ -25,7 +25,7 @@ #include <watchdog.h> #include <command.h> #include <asm/cache.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) #include <libfdt.h> diff --git a/arch/powerpc/cpu/ppc4xx/gpio.c b/arch/powerpc/cpu/ppc4xx/gpio.c index c0d351a..20f0572 100644 --- a/arch/powerpc/cpu/ppc4xx/gpio.c +++ b/arch/powerpc/cpu/ppc4xx/gpio.c @@ -24,7 +24,10 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> + +/* Only compile this file for boards with GPIO support */ +#if defined(GPIO0_BASE) #if defined(CONFIG_SYS_4xx_GPIO_TABLE) gpio_param_s const gpio_tab[GPIO_GROUP_MAX][GPIO_MAX] = CONFIG_SYS_4xx_GPIO_TABLE; @@ -252,4 +255,6 @@ void gpio_set_chip_configuration(void) } } } + +#endif /* GPIO0_BASE */ #endif /* CONFIG_SYS_4xx_GPIO_TABLE */ diff --git a/arch/powerpc/cpu/ppc4xx/interrupts.c b/arch/powerpc/cpu/ppc4xx/interrupts.c index c89bf37..c2d4973 100644 --- a/arch/powerpc/cpu/ppc4xx/interrupts.c +++ b/arch/powerpc/cpu/ppc4xx/interrupts.c @@ -36,7 +36,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> diff --git a/arch/powerpc/cpu/ppc4xx/kgdb.S b/arch/powerpc/cpu/ppc4xx/kgdb.S index 4227a4c..417ba62 100644 --- a/arch/powerpc/cpu/ppc4xx/kgdb.S +++ b/arch/powerpc/cpu/ppc4xx/kgdb.S @@ -22,7 +22,7 @@ #include <config.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <version.h> #define CONFIG_405GP 1 /* needed for Linux kernel header files */ diff --git a/arch/powerpc/cpu/ppc4xx/miiphy.c b/arch/powerpc/cpu/ppc4xx/miiphy.c index 4fec126..3b28122 100644 --- a/arch/powerpc/cpu/ppc4xx/miiphy.c +++ b/arch/powerpc/cpu/ppc4xx/miiphy.c @@ -41,8 +41,8 @@ #include <asm/io.h> #include <ppc_asm.tmpl> #include <commproc.h> -#include <ppc4xx_enet.h> -#include <405_mal.h> +#include <asm/ppc4xx-emac.h> +#include <asm/ppc4xx-mal.h> #include <miiphy.h> #if !defined(CONFIG_PHY_CLK_FREQ) diff --git a/arch/powerpc/cpu/ppc4xx/reginfo.c b/arch/powerpc/cpu/ppc4xx/reginfo.c index a975667..2f1ab9e 100644 --- a/arch/powerpc/cpu/ppc4xx/reginfo.c +++ b/arch/powerpc/cpu/ppc4xx/reginfo.c @@ -28,7 +28,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/ppc4xx-uic.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> enum REGISTER_TYPE { IDCR1, /* Indirectly Accessed DCR via SDRAM0_CFGADDR/SDRAM0_CFGDATA */ @@ -108,9 +108,9 @@ const struct cpu_register ppc4xx_reg[] = { {"SDR0_SDSTP3", IDCR6, SDR0_SDSTP3}, {"SDR0_CUST0", IDCR6, SDR0_CUST0}, {"SDR0_CUST1", IDCR6, SDR0_CUST1}, - {"SDR0_EBC0", IDCR6, SDR0_EBC0}, - {"SDR0_AMP0", IDCR6, SD0_AMP0}, - {"SDR0_AMP1", IDCR6, SD0_AMP1}, + {"SDR0_EBC", IDCR6, SDR0_EBC}, + {"SDR0_AMP0", IDCR6, SDR0_AMP0}, + {"SDR0_AMP1", IDCR6, SDR0_AMP1}, {"SDR0_CP440", IDCR6, SDR0_CP440}, {"SDR0_CRYP0", IDCR6, SDR0_CRYP0}, {"SDR0_DDRCFG", IDCR6, SDR0_DDRCFG}, diff --git a/arch/powerpc/cpu/ppc4xx/sdram.c b/arch/powerpc/cpu/ppc4xx/sdram.c index 30c6e0e..b827daf 100644 --- a/arch/powerpc/cpu/ppc4xx/sdram.c +++ b/arch/powerpc/cpu/ppc4xx/sdram.c @@ -28,7 +28,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include "sdram.h" #include "ecc.h" diff --git a/arch/powerpc/cpu/ppc4xx/speed.c b/arch/powerpc/cpu/ppc4xx/speed.c index 906face..abd4e91 100644 --- a/arch/powerpc/cpu/ppc4xx/speed.c +++ b/arch/powerpc/cpu/ppc4xx/speed.c @@ -23,7 +23,7 @@ #include <common.h> #include <ppc_asm.tmpl> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> DECLARE_GLOBAL_DATA_PTR; @@ -902,7 +902,7 @@ void get_sys_info (PPC4xx_SYS_INFO * sysInfo) /* * Read CPR_PRIMAD register */ - mfcpr(CPC0_PRIMAD, cpr_primad); + mfcpr(CPR0_PRIMAD, cpr_primad); /* * Determine PLB_DIV. diff --git a/arch/powerpc/cpu/ppc4xx/start.S b/arch/powerpc/cpu/ppc4xx/start.S index 4bad32f..7a65d9f 100644 --- a/arch/powerpc/cpu/ppc4xx/start.S +++ b/arch/powerpc/cpu/ppc4xx/start.S @@ -64,7 +64,7 @@ * address and (s)dram will be positioned at address 0 */ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <timestamp.h> #include <version.h> @@ -340,6 +340,9 @@ _start_440: mfspr r1,SPRN_DBCR0 andis. r1, r1, 0x8000 /* test DBCR0[EDM] bit */ bne skip_debug_init /* if set, don't clear debug register */ + mfspr r1,SPRN_CCR0 + ori r1,r1,CCR0_DTB@l /* Disable Trace Broadcast */ + mtspr SPRN_CCR0,r1 mtspr SPRN_DBCR0,r0 mtspr SPRN_DBCR1,r0 mtspr SPRN_DBCR2,r0 diff --git a/arch/powerpc/cpu/ppc4xx/tlb.c b/arch/powerpc/cpu/ppc4xx/tlb.c index 24a9a9c..684da92 100644 --- a/arch/powerpc/cpu/ppc4xx/tlb.c +++ b/arch/powerpc/cpu/ppc4xx/tlb.c @@ -25,7 +25,7 @@ #if defined(CONFIG_440) -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/cache.h> #include <asm/io.h> #include <asm/mmu.h> diff --git a/arch/powerpc/cpu/ppc4xx/uic.c b/arch/powerpc/cpu/ppc4xx/uic.c index 8b1b259..324f0e9 100644 --- a/arch/powerpc/cpu/ppc4xx/uic.c +++ b/arch/powerpc/cpu/ppc4xx/uic.c @@ -36,7 +36,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> diff --git a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c index 7108777..eaa3de2 100644 --- a/arch/powerpc/cpu/ppc4xx/xilinx_irq.c +++ b/arch/powerpc/cpu/ppc4xx/xilinx_irq.c @@ -21,7 +21,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/interrupt.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <commproc.h> #include <asm/io.h> diff --git a/arch/powerpc/include/asm/4xx_pcie.h b/arch/powerpc/include/asm/4xx_pcie.h index a0e88de..90e0bd9 100644 --- a/arch/powerpc/include/asm/4xx_pcie.h +++ b/arch/powerpc/include/asm/4xx_pcie.h @@ -11,7 +11,7 @@ #ifndef __4XX_PCIE_H #define __4XX_PCIE_H -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <pci.h> #define DCRN_SDR0_CFGADDR 0x00e diff --git a/arch/powerpc/include/asm/global_data.h b/arch/powerpc/include/asm/global_data.h index c854ce9..2a323e1 100644 --- a/arch/powerpc/include/asm/global_data.h +++ b/arch/powerpc/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -176,18 +176,20 @@ typedef struct global_data { unsigned long long wdt_last; /* trace watch-dog triggering rate */ #endif void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #if 1 #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("r2") diff --git a/arch/powerpc/include/asm/ppc405.h b/arch/powerpc/include/asm/ppc405.h new file mode 100644 index 0000000..14a7a37 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405.h @@ -0,0 +1,80 @@ +/*----------------------------------------------------------------------------+ +| This source code is dual-licensed. You may use it under the terms of the +| GNU General Public License version 2, or under the license below. +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC405_H__ +#define __PPC405_H__ + +/* Define bits and masks for real-mode storage attribute control registers */ +#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) +#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) + +#ifndef CONFIG_IOP480 +#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ +#else +#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ +#endif + +/* DCR registers */ +#define PLB0_ACR 0x0087 + +/* SDR registers */ +#define SDR0_PINSTP 0x0040 + +/* CPR registers */ +#define CPR0_CLKUPD 0x0020 +#define CPR0_PLLC 0x0040 +#define CPR0_PLLD 0x0060 +#define CPR0_CPUD 0x0080 +#define CPR0_PLBD 0x00a0 +#define CPR0_OPBD0 0x00c0 +#define CPR0_PERD 0x00e0 + +/* + * DMA + */ +#define DMA_DCR_BASE 0x0100 +#define DMACR0 (DMA_DCR_BASE + 0x00) /* DMA channel control reg 0 */ +#define DMACT0 (DMA_DCR_BASE + 0x01) /* DMA count reg 0 */ +#define DMADA0 (DMA_DCR_BASE + 0x02) /* DMA destination address reg 0 */ +#define DMASA0 (DMA_DCR_BASE + 0x03) /* DMA source address reg 0 */ +#define DMASB0 (DMA_DCR_BASE + 0x04) /* DMA sg descriptor addr 0 */ +#define DMACR1 (DMA_DCR_BASE + 0x08) /* DMA channel control reg 1 */ +#define DMACT1 (DMA_DCR_BASE + 0x09) /* DMA count reg 1 */ +#define DMADA1 (DMA_DCR_BASE + 0x0a) /* DMA destination address reg 1 */ +#define DMASA1 (DMA_DCR_BASE + 0x0b) /* DMA source address reg 1 */ +#define DMASB1 (DMA_DCR_BASE + 0x0c) /* DMA sg descriptor addr 1 */ +#define DMACR2 (DMA_DCR_BASE + 0x10) /* DMA channel control reg 2 */ +#define DMACT2 (DMA_DCR_BASE + 0x11) /* DMA count reg 2 */ +#define DMADA2 (DMA_DCR_BASE + 0x12) /* DMA destination address reg 2 */ +#define DMASA2 (DMA_DCR_BASE + 0x13) /* DMA source address reg 2 */ +#define DMASB2 (DMA_DCR_BASE + 0x14) /* DMA sg descriptor addr 2 */ +#define DMACR3 (DMA_DCR_BASE + 0x18) /* DMA channel control reg 3 */ +#define DMACT3 (DMA_DCR_BASE + 0x19) /* DMA count reg 3 */ +#define DMADA3 (DMA_DCR_BASE + 0x1a) /* DMA destination address reg 3 */ +#define DMASA3 (DMA_DCR_BASE + 0x1b) /* DMA source address reg 3 */ +#define DMASB3 (DMA_DCR_BASE + 0x1c) /* DMA sg descriptor addr 3 */ +#define DMASR (DMA_DCR_BASE + 0x20) /* DMA status reg */ +#define DMASGC (DMA_DCR_BASE + 0x23) /* DMA scatter/gather command reg*/ +#define DMAADR (DMA_DCR_BASE + 0x24) /* DMA address decode reg */ + +#endif /* __PPC405_H__ */ diff --git a/arch/powerpc/include/asm/ppc405cr.h b/arch/powerpc/include/asm/ppc405cr.h new file mode 100644 index 0000000..01078f7 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405cr.h @@ -0,0 +1,105 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405CR_H_ +#define _PPC405CR_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* DCR's */ +#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */ +#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */ +#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */ +#define OCM0_DSARC 0x001a /* OCM D-side address compare */ +#define OCM0_DSCNTL 0x001b /* OCM D-side control */ +#define CPC0_PLLMR 0x00b0 /* PLL mode register */ +#define CPC0_CR0 0x00b1 /* chip control register 0 */ +#define CPC0_CR1 0x00b2 /* chip control register 1 */ +#define CPC0_PSR 0x00b4 /* chip pin strapping reg */ +#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */ +#define CPC0_SR 0x00b8 /* Power management status */ +#define CPC0_ER 0x00b9 /* Power management enable */ +#define CPC0_FR 0x00ba /* Power management force */ +#define CPC0_ECR 0x00aa /* edge conditioner register */ + +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#endif /* _PPC405CR_H_ */ diff --git a/arch/powerpc/include/asm/ppc405ep.h b/arch/powerpc/include/asm/ppc405ep.h new file mode 100644 index 0000000..9691604 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405ep.h @@ -0,0 +1,252 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405EP_H_ +#define _PPC405EP_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* DCR */ +#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */ +#define OCM0_DSARC 0x001a /* OCM D-side address compare */ +#define OCM0_DSCNTL 0x001b /* OCM D-side control */ +#define CPC0_PLLMR0 0x00f0 /* PLL mode register 0 */ +#define CPC0_BOOT 0x00f1 /* Clock status register */ +#define CPC0_CR1 0x00f2 /* Chip Control 1 register */ +#define CPC0_EPCTL 0x00f3 /* EMAC to PHY control register */ +#define CPC0_PLLMR1 0x00f4 /* PLL mode register 1 */ +#define CPC0_UCR 0x00f5 /* UART control register */ +#define CPC0_SRR 0x00f6 /* Soft Reset register */ +#define CPC0_PCI 0x00f9 /* PCI control register */ + +/* Defines for CPC0_EPCTL register */ +#define CPC0_EPCTL_E0NFE 0x80000000 +#define CPC0_EPCTL_E1NFE 0x40000000 + +/* Defines for CPC0_PCI Register */ +#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ +#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ +#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */ + +/* Defines for CPC0_BOOR Register */ +#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ + +/* Bit definitions */ +#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ +#define PLLMR0_CPU_DIV_BYPASS 0x00000000 +#define PLLMR0_CPU_DIV_2 0x00100000 +#define PLLMR0_CPU_DIV_3 0x00200000 +#define PLLMR0_CPU_DIV_4 0x00300000 + +#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ +#define PLLMR0_CPU_PLB_DIV_1 0x00000000 +#define PLLMR0_CPU_PLB_DIV_2 0x00010000 +#define PLLMR0_CPU_PLB_DIV_3 0x00020000 +#define PLLMR0_CPU_PLB_DIV_4 0x00030000 + +#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ +#define PLLMR0_OPB_PLB_DIV_1 0x00000000 +#define PLLMR0_OPB_PLB_DIV_2 0x00001000 +#define PLLMR0_OPB_PLB_DIV_3 0x00002000 +#define PLLMR0_OPB_PLB_DIV_4 0x00003000 + +#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ +#define PLLMR0_EXB_PLB_DIV_2 0x00000000 +#define PLLMR0_EXB_PLB_DIV_3 0x00000100 +#define PLLMR0_EXB_PLB_DIV_4 0x00000200 +#define PLLMR0_EXB_PLB_DIV_5 0x00000300 + +#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ +#define PLLMR0_MAL_PLB_DIV_1 0x00000000 +#define PLLMR0_MAL_PLB_DIV_2 0x00000010 +#define PLLMR0_MAL_PLB_DIV_3 0x00000020 +#define PLLMR0_MAL_PLB_DIV_4 0x00000030 + +#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ +#define PLLMR0_PCI_PLB_DIV_1 0x00000000 +#define PLLMR0_PCI_PLB_DIV_2 0x00000001 +#define PLLMR0_PCI_PLB_DIV_3 0x00000002 +#define PLLMR0_PCI_PLB_DIV_4 0x00000003 + +#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ +#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ +#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ + +#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ +#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ +#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ + +/* Defines for CPC0_PLLMR1 Register fields */ +#define PLL_ACTIVE 0x80000000 +#define CPC0_PLLMR1_SSCS 0x80000000 +#define PLL_RESET 0x40000000 +#define CPC0_PLLMR1_PLLR 0x40000000 +/* Feedback multiplier */ +#define PLL_FBKDIV 0x00F00000 +#define CPC0_PLLMR1_FBDV 0x00F00000 +#define PLL_FBKDIV_16 0x00000000 +#define PLL_FBKDIV_1 0x00100000 +#define PLL_FBKDIV_2 0x00200000 +#define PLL_FBKDIV_3 0x00300000 +#define PLL_FBKDIV_4 0x00400000 +#define PLL_FBKDIV_5 0x00500000 +#define PLL_FBKDIV_6 0x00600000 +#define PLL_FBKDIV_7 0x00700000 +#define PLL_FBKDIV_8 0x00800000 +#define PLL_FBKDIV_9 0x00900000 +#define PLL_FBKDIV_10 0x00A00000 +#define PLL_FBKDIV_11 0x00B00000 +#define PLL_FBKDIV_12 0x00C00000 +#define PLL_FBKDIV_13 0x00D00000 +#define PLL_FBKDIV_14 0x00E00000 +#define PLL_FBKDIV_15 0x00F00000 +/* Forward A divisor */ +#define PLL_FWDDIVA 0x00070000 +#define CPC0_PLLMR1_FWDVA 0x00070000 +#define PLL_FWDDIVA_8 0x00000000 +#define PLL_FWDDIVA_7 0x00010000 +#define PLL_FWDDIVA_6 0x00020000 +#define PLL_FWDDIVA_5 0x00030000 +#define PLL_FWDDIVA_4 0x00040000 +#define PLL_FWDDIVA_3 0x00050000 +#define PLL_FWDDIVA_2 0x00060000 +#define PLL_FWDDIVA_1 0x00070000 +/* Forward B divisor */ +#define PLL_FWDDIVB 0x00007000 +#define CPC0_PLLMR1_FWDVB 0x00007000 +#define PLL_FWDDIVB_8 0x00000000 +#define PLL_FWDDIVB_7 0x00001000 +#define PLL_FWDDIVB_6 0x00002000 +#define PLL_FWDDIVB_5 0x00003000 +#define PLL_FWDDIVB_4 0x00004000 +#define PLL_FWDDIVB_3 0x00005000 +#define PLL_FWDDIVB_2 0x00006000 +#define PLL_FWDDIVB_1 0x00007000 +/* PLL tune bits */ +#define PLL_TUNE_MASK 0x000003FF +#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ +#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ +#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ +#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ +#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ +#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ +#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ + +/* Defines for CPC0_PLLMR0 Register fields */ +/* CPU divisor */ +#define PLL_CPUDIV 0x00300000 +#define CPC0_PLLMR0_CCDV 0x00300000 +#define PLL_CPUDIV_1 0x00000000 +#define PLL_CPUDIV_2 0x00100000 +#define PLL_CPUDIV_3 0x00200000 +#define PLL_CPUDIV_4 0x00300000 +/* PLB divisor */ +#define PLL_PLBDIV 0x00030000 +#define CPC0_PLLMR0_CBDV 0x00030000 +#define PLL_PLBDIV_1 0x00000000 +#define PLL_PLBDIV_2 0x00010000 +#define PLL_PLBDIV_3 0x00020000 +#define PLL_PLBDIV_4 0x00030000 +/* OPB divisor */ +#define PLL_OPBDIV 0x00003000 +#define CPC0_PLLMR0_OPDV 0x00003000 +#define PLL_OPBDIV_1 0x00000000 +#define PLL_OPBDIV_2 0x00001000 +#define PLL_OPBDIV_3 0x00002000 +#define PLL_OPBDIV_4 0x00003000 +/* EBC divisor */ +#define PLL_EXTBUSDIV 0x00000300 +#define CPC0_PLLMR0_EPDV 0x00000300 +#define PLL_EXTBUSDIV_2 0x00000000 +#define PLL_EXTBUSDIV_3 0x00000100 +#define PLL_EXTBUSDIV_4 0x00000200 +#define PLL_EXTBUSDIV_5 0x00000300 +/* MAL divisor */ +#define PLL_MALDIV 0x00000030 +#define CPC0_PLLMR0_MPDV 0x00000030 +#define PLL_MALDIV_1 0x00000000 +#define PLL_MALDIV_2 0x00000010 +#define PLL_MALDIV_3 0x00000020 +#define PLL_MALDIV_4 0x00000030 +/* PCI divisor */ +#define PLL_PCIDIV 0x00000003 +#define CPC0_PLLMR0_PPFD 0x00000003 +#define PLL_PCIDIV_1 0x00000000 +#define PLL_PCIDIV_2 0x00000001 +#define PLL_PCIDIV_3 0x00000002 +#define PLL_PCIDIV_4 0x00000003 + +/* + * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, + * assuming a 33.3MHz input clock to the 405EP. + */ +#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) + +#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ + PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ + PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ + PLL_MALDIV_1 | PLL_PCIDIV_4) +#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_2) +#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) +#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_3) +#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) +#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ + PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ + PLL_MALDIV_1 | PLL_PCIDIV_1) +#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ + PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ + PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) + +#endif /* _PPC405EP_H_ */ diff --git a/arch/powerpc/include/asm/ppc405ex.h b/arch/powerpc/include/asm/ppc405ex.h new file mode 100644 index 0000000..36d3149 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405ex.h @@ -0,0 +1,90 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405EX_H_ +#define _PPC405EX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +#define CONFIG_NAND_NDFC + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) + +/* SDR */ +#define SDR0_SDCS0 0x0060 +#define SDR0_UART0 0x0120 /* UART0 Config */ +#define SDR0_UART1 0x0121 /* UART1 Config */ +#define SDR0_SRST 0x0200 +#define SDR0_CUST0 0x4000 +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +#define SDR0_SRST_DMC (0x80000000 >> 10) + +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_PFC1_U1ME 0x02000000 +#define SDR0_PFC1_U0ME 0x00080000 +#define SDR0_PFC1_U0IM 0x00040000 +#define SDR0_PFC1_SIS 0x00020000 +#define SDR0_PFC1_DMAAEN 0x00010000 +#define SDR0_PFC1_DMADEN 0x00008000 +#define SDR0_PFC1_USBEN 0x00004000 +#define SDR0_PFC1_AHBSWAP 0x00000020 +#define SDR0_PFC1_USBBIGEN 0x00000010 +#define SDR0_PFC1_GPT_FREQ 0x0000000f + +#endif /* _PPC405EX_H_ */ diff --git a/arch/powerpc/include/asm/ppc405ez.h b/arch/powerpc/include/asm/ppc405ez.h new file mode 100644 index 0000000..cb8e994 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405ez.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405EZ_H_ +#define _PPC405EZ_H_ + +#define CONFIG_NAND_NDFC + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0800) + +/* DCR register */ +#define OCM0_PLBCR1 0x0020 /* OCM PLB3 Bank 1 Config */ +#define OCM0_PLBCR2 0x0021 /* OCM PLB3 Bank 2 Config */ +#define OCM0_PLBBEAR 0x0022 /* OCM PLB3 Bus Error Add */ +#define OCM0_DSRC1 0x0028 /* OCM D-side Bank 1 Config */ +#define OCM0_DSRC2 0x0029 /* OCM D-side Bank 2 Config */ +#define OCM0_ISRC1 0x002A /* OCM I-side Bank 1Config */ +#define OCM0_ISRC2 0x002B /* OCM I-side Bank 2 Config */ +#define OCM0_DISDPC 0x002C /* OCM D-/I-side Data Par Chk */ + +/* SDR register */ +#define SDR0_NAND0 0x4000 +#define SDR0_ULTRA0 0x4040 +#define SDR0_ULTRA1 0x4050 +#define SDR0_ICINTSTAT 0x4510 + +/* CPR register */ +#define CPR0_PRIMAD 0x0080 +#define CPR0_PERD0 0x00e0 +#define CPR0_PERD1 0x00e1 +#define CPR0_PERC0 0x0180 + +#define MAL_DCR_BASE 0x380 + +#define SDR_NAND0_NDEN 0x80000000 +#define SDR_NAND0_NDBTEN 0x40000000 +#define SDR_NAND0_NDBADR_MASK 0x30000000 +#define SDR_NAND0_NDBPG_MASK 0x0f000000 +#define SDR_NAND0_NDAREN 0x00800000 +#define SDR_NAND0_NDRBEN 0x00400000 + +#define SDR_ULTRA0_NDGPIOBP 0x80000000 +#define SDR_ULTRA0_CSN_MASK 0x78000000 +#define SDR_ULTRA0_CSNSEL0 0x40000000 +#define SDR_ULTRA0_CSNSEL1 0x20000000 +#define SDR_ULTRA0_CSNSEL2 0x10000000 +#define SDR_ULTRA0_CSNSEL3 0x08000000 +#define SDR_ULTRA0_EBCRDYEN 0x04000000 +#define SDR_ULTRA0_SPISSINEN 0x02000000 +#define SDR_ULTRA0_NFSRSTEN 0x01000000 + +#define SDR_ULTRA1_LEDNENABLE 0x40000000 + +#define SDR_ICRX_STAT 0x80000000 +#define SDR_ICTX0_STAT 0x40000000 +#define SDR_ICTX1_STAT 0x20000000 + +#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ +#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ +#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ + +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ + +#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ +#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ + +#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ +#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ +#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ +#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ + +#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ +#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ +#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ +#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ + +#endif /* _PPC405EZ_H_ */ diff --git a/arch/powerpc/include/asm/ppc405gp.h b/arch/powerpc/include/asm/ppc405gp.h new file mode 100644 index 0000000..91beeb8 --- /dev/null +++ b/arch/powerpc/include/asm/ppc405gp.h @@ -0,0 +1,108 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC405GP_H_ +#define _PPC405GP_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* DCR's */ +#define DCP0_CFGADDR 0x0014 /* Decompression controller addr reg */ +#define DCP0_CFGDATA 0x0015 /* Decompression controller data reg */ +#define OCM0_ISCNTL 0x0019 /* OCM I-side control reg */ +#define OCM0_DSARC 0x001a /* OCM D-side address compare */ +#define OCM0_DSCNTL 0x001b /* OCM D-side control */ +#define CPC0_PLLMR 0x00b0 /* PLL mode register */ +#define CPC0_CR0 0x00b1 /* chip control register 0 */ +#define CPC0_CR1 0x00b2 /* chip control register 1 */ +#define CPC0_PSR 0x00b4 /* chip pin strapping reg */ +#define CPC0_EIRR 0x00b6 /* ext interrupt routing reg */ +#define CPC0_SR 0x00b8 /* Power management status */ +#define CPC0_ER 0x00b9 /* Power management enable */ +#define CPC0_FR 0x00ba /* Power management force */ +#define CPC0_ECR 0x00aa /* edge conditioner register */ + +/* values for kiar register - indirect addressing of these regs */ +#define KCONF 0x40 /* decompression core config register */ + +#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ +#define PLLMR_FWD_DIV_BYPASS 0xE0000000 +#define PLLMR_FWD_DIV_3 0xA0000000 +#define PLLMR_FWD_DIV_4 0x80000000 +#define PLLMR_FWD_DIV_6 0x40000000 + +#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ +#define PLLMR_FB_DIV_1 0x02000000 +#define PLLMR_FB_DIV_2 0x04000000 +#define PLLMR_FB_DIV_3 0x06000000 +#define PLLMR_FB_DIV_4 0x08000000 + +#define PLLMR_TUNING_MASK 0x01F80000 + +#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ +#define PLLMR_CPU_PLB_DIV_1 0x00000000 +#define PLLMR_CPU_PLB_DIV_2 0x00020000 +#define PLLMR_CPU_PLB_DIV_3 0x00040000 +#define PLLMR_CPU_PLB_DIV_4 0x00060000 + +#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ +#define PLLMR_OPB_PLB_DIV_1 0x00000000 +#define PLLMR_OPB_PLB_DIV_2 0x00008000 +#define PLLMR_OPB_PLB_DIV_3 0x00010000 +#define PLLMR_OPB_PLB_DIV_4 0x00018000 + +#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ +#define PLLMR_PCI_PLB_DIV_1 0x00000000 +#define PLLMR_PCI_PLB_DIV_2 0x00002000 +#define PLLMR_PCI_PLB_DIV_3 0x00004000 +#define PLLMR_PCI_PLB_DIV_4 0x00006000 + +#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ +#define PLLMR_EXB_PLB_DIV_2 0x00000000 +#define PLLMR_EXB_PLB_DIV_3 0x00000800 +#define PLLMR_EXB_PLB_DIV_4 0x00001000 +#define PLLMR_EXB_PLB_DIV_5 0x00001800 + +/* definitions for PPC405GPr (new mode strapping) */ +#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ + +#define PSR_PLL_FWD_MASK 0xC0000000 +#define PSR_PLL_FDBACK_MASK 0x30000000 +#define PSR_PLL_TUNING_MASK 0x0E000000 +#define PSR_PLB_CPU_MASK 0x01800000 +#define PSR_OPB_PLB_MASK 0x00600000 +#define PSR_PCI_PLB_MASK 0x00180000 +#define PSR_EB_PLB_MASK 0x00060000 +#define PSR_ROM_WIDTH_MASK 0x00018000 +#define PSR_ROM_LOC 0x00004000 +#define PSR_PCI_ASYNC_EN 0x00001000 +#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ +#define PSR_PCI_ARBIT_EN 0x00000400 +#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ + +#endif /* _PPC405GP_H_ */ diff --git a/arch/powerpc/include/asm/ppc440.h b/arch/powerpc/include/asm/ppc440.h new file mode 100644 index 0000000..0da6618 --- /dev/null +++ b/arch/powerpc/include/asm/ppc440.h @@ -0,0 +1,190 @@ +/*----------------------------------------------------------------------------+ +| This source code is dual-licensed. You may use it under the terms of the +| GNU General Public License version 2, or under the license below. +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +/* + * (C) Copyright 2006 + * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com + * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com + * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com + * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com + * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com + * + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __PPC440_H__ +#define __PPC440_H__ + +#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ + +/* + * DCRs & Related + */ + +/* Memory mapped registers */ +#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) +#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) +#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) +#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) + +/* DCR registers */ + +/* CPR register declarations */ +#define CPR0_PLLC 0x0040 +#define CPR0_PLLD 0x0060 +#define CPR0_PRIMAD0 0x0080 +#define CPR0_PRIMBD0 0x00a0 +#define CPR0_OPBD0 0x00c0 +#define CPR0_PERD 0x00e0 +#define CPR0_MALD 0x0100 +#define CPR0_SPCID 0x0120 +#define CPR0_ICFG 0x0140 + +/* SDR register definations */ +#define SDR0_SDSTP0 0x0020 +#define SDR0_SDSTP1 0x0021 +#define SDR0_PINSTP 0x0040 +#define SDR0_SDCS0 0x0060 +#define SDR0_ECID0 0x0080 +#define SDR0_ECID1 0x0081 +#define SDR0_ECID2 0x0082 +#define SDR0_ECID3 0x0083 +#define SDR0_DDR0 0x00e1 +#define SDR0_EBC 0x0100 +#define SDR0_UART0 0x0120 +#define SDR0_UART1 0x0121 +#define SDR0_UART2 0x0122 +#define SDR0_UART3 0x0123 +#define SDR0_CP440 0x0180 +#define SDR0_XCR 0x01c0 +#define SDR0_XCR0 0x01c0 +#define SDR0_XPLLC 0x01c1 +#define SDR0_XPLLD 0x01c2 +#define SDR0_SRST 0x0200 +#define SDR0_SRST0 SDR0_SRST +#define SDR0_SRST1 0x0201 +#define SDR0_AMP0 0x0240 +#define SDR0_AMP1 0x0241 +#define SDR0_USB0 0x0320 +#define SDR0_CUST0 0x4000 +#define SDR0_CUST1 0x4002 +#define SDR0_CUST2 0x4004 +#define SDR0_CUST3 0x4006 +#define SDR0_PFC0 0x4100 +#define SDR0_PFC1 0x4101 +#define SDR0_PFC2 0x4102 +#define SDR0_PFC4 0x4104 +#define SDR0_MFR 0x4300 + +#define SDR0_DDR0_DDRM_DECODE(n) ((((u32)(n)) >> 29) & 0x03) + +#define SDR0_PCI0_PAE_MASK (0x80000000 >> 0) +#define SDR0_XCR0_PAE_MASK (0x80000000 >> 0) + +#define SDR0_PFC0_GEIE_MASK 0x00003e00 +#define SDR0_PFC0_GEIE_TRE 0x00003e00 +#define SDR0_PFC0_GEIE_NOTRE 0x00000000 +#define SDR0_PFC0_TRE_MASK (0x80000000 >> 23) +#define SDR0_PFC0_TRE_DISABLE 0x00000000 +#define SDR0_PFC0_TRE_ENABLE (0x80000000 >> 23) + +/* + * Core Configuration/MMU configuration for 440 + */ +#define CCR0_DAPUIB 0x00100000 +#define CCR0_DTB 0x00008000 + +#define SDR0_SDCS_SDD (0x80000000 >> 31) + +/* todo: move this code from macro offsets to struct */ +#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) +#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) +#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) +#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) +#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) +#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) +#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) +#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) +#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) +#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) +#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) +#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) +#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) +#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) +#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) +#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) +#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) +#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) +#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) +#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) +#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) +#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) +#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) +#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) +#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) +#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) + +#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) +#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) + +#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) +#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) +#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) +#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) +#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) +#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) +#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) +#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) +#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) +#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) +#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) + +#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) +#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) +#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) +#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) +#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) +#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) +#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) +#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) +#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) + +#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) + +#endif /* __PPC440_H__ */ diff --git a/arch/powerpc/include/asm/ppc440ep_gr.h b/arch/powerpc/include/asm/ppc440ep_gr.h new file mode 100644 index 0000000..dfd1532 --- /dev/null +++ b/arch/powerpc/include/asm/ppc440ep_gr.h @@ -0,0 +1,244 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440EP_GR_H_ +#define _PPC440EP_GR_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ + +#define CONFIG_NAND_NDFC + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) + +/* SDR's */ +#define SDR0_PCI0 0x0300 +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 + +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) +#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) + +/* Pin Function Control Register 1 */ +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold + Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) + Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) + Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. + Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject + Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject + Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject + Enable */ +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable + Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation + Gated In */ + +/* USB Control Register */ +#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ +#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ +#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + +/* Miscealleneaous Function Reg. */ +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ +#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24) +#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3) + +#define SDR0_MFR_ERRATA3_EN0 0x00800000 +#define SDR0_MFR_ERRATA3_EN1 0x00400000 +#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_SRST_DMC 0x00200000 + +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 +#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 +#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 +#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 +#define CPR0_PERD_PERDV0_MASK 0x07000000 + +#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => + 0x0EF400000 */ + +/* PCI Master Local Configuration Registers */ +#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ + +/* PCI Target Local Configuration Registers */ +#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ + Attribute */ +#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ + Attribute */ +#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ + +#endif /* _PPC440EP_GR_H_ */ diff --git a/arch/powerpc/include/asm/ppc440epx_grx.h b/arch/powerpc/include/asm/ppc440epx_grx.h new file mode 100644 index 0000000..252f35b --- /dev/null +++ b/arch/powerpc/include/asm/ppc440epx_grx.h @@ -0,0 +1,464 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440EPX_GRX_H_ +#define _PPC440EPX_GRX_H_ + +#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ + +#define CONFIG_NAND_NDFC + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define SPI0_MODE (CONFIG_SYS_PERIPHERAL_BASE + 0x0090) + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) + +/* DCR */ +#define CPM0_ER 0x00b0 +#define CPM1_ER 0x00f0 +#define PLB3A0_ACR 0x0077 +#define PLB4A0_ACR 0x0081 +#define PLB4A1_ACR 0x0089 +#define OPB2PLB40_BCTRL 0x0350 +#define P4P3BO0_CFG 0x0026 + +/* SDR */ +#define SDR0_DDRCFG 0x00e0 +#define SDR0_PCI0 0x0300 +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 +#define SDR0_EMAC0RXST 0x4301 +#define SDR0_EMAC0TXST 0x4302 +#define SDR0_CRYP0 0x4500 + +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) +#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) + +/* Pin Function Control Register 1 */ +#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ +#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ +#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ +#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select + EMAC 0 */ +#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII + bridge */ +#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII + bridge */ +#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ +#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ +#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ +#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ +#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ +#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ +#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ +#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ +#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ +#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold + Req Selection */ +#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ +#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ +#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) + Selection */ +#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ +#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ +#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) + Selection */ +#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. + Selected */ +#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ +#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject + Selection */ +#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject + Disable */ +#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject + Enable */ +#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable + Selection */ +#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor + Enable */ +#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation + Gated In */ + +#define SDR0_PFC2_SELECT_MASK 0xe0000000 /* Ethernet Pin select EMAC1 */ +#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_4 0xa0000000 /* 2xRGMII using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_5 0xc0000000 /* 2xRTBI using RGMII bridge */ +#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ + +#define SDR0_USB2D0CR 0x0320 +#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC + Master Selection */ +#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ +#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ + +#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface + Selection */ +#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ +#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ + +#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ +#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ +#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ + +/* USB2 Host Control Register */ +#define SDR0_USB2H0CR 0x0340 +#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ +#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ +#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ +#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length + Adjustment */ +/* USB2PHY0 Control Register */ +#define SDR0_USB2PHY0CR 0x4103 +#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 + + /* PHY UTMI interface connection */ +#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ +#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ + +#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ +#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ +#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ + +/* VBus detect (Device mode only) */ +#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 +/* Pull-up resistance on D+ is disabled */ +#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 +/* Pull-up resistance on D+ is enabled */ +#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 + +/* PHY UTMI data width and clock select */ +#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 +#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ +#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ + +#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ +#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ +/* Loop back enabled (only test purposes) */ +#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 + +/* Force XO block on during a suspend */ +#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 +#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ +/* PHY XO block is powered-off when all ports are suspended */ +#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 + +#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ +#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only + for full-speed operation */ + +#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock + source */ +#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal + 48M clock as a reference */ +#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO + block output as a reference */ + +#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO + block*/ +#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external + clock */ +#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock + from a crystal */ + +#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ +#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq + = 12 MHz */ +#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq + = 48 MHz */ +#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq + = 24 MHz */ + +/* USB2.0 Device */ +/* + * todo: check if this can be completely removed, only used in + * cpu/ppc4xx/usbdev.c. And offsets are completely wrong. This could + * never have actually worked. Best probably is to remove this + * usbdev.c file completely (and these defines). + */ +#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE + +#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) + +#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for + Endpoint 0 plus IN Endpoints 1 to 3 */ +#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management + register */ +#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address + register */ +#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for USB2D0_INTRIN */ +#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for + OUT Endpoints 1 to 3 */ +#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for USB2D0_INTRUSB */ +#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for + common USB interrupts */ +#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable + register for IntrOut */ +#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 + test modes */ +#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for + selecting the Endpoint status/control registers */ +#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ +#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status + register for Endpoint 0. (Index register set to select Endpoint 0) */ +#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status + register for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet + size for IN Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status + register for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet + size for OUT Endpoint. (Index register set to select Endpoints 13) */ +#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received + bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ +#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in + OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ + +/* Miscealleneaous Function Reg. */ +#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ +#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ +#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 +#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ +#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ +#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ +#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ +#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ +#define SDR0_MFR_ZM_ENCODE(n) ((((u32)(n)) & 0x3) << 24) +#define SDR0_MFR_ZM_DECODE(n) ((((u32)(n)) << 24) & 0x3) +#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ +#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ +#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ +#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ +#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ + transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ +#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ +#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ +#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ +#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ +#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ +#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ +#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ +#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ +#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ +#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ +#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ +#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ + transmitter 2 */ +#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ + transmitter 3 */ + +#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ +#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ +#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ +#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 +#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 + USB 2.0 Host */ +#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to + USB 2.0 Host */ +#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to + USB 2.0 Host */ +#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ +#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ +#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ +#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ +#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ +#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ +#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ +#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ +#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ +#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ +#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ + +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define CPR0_ICFG_RLI_MASK 0x80000000 +#define CPR0_ICFG_ICS_MASK 0x00000007 +#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 +#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 +#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 +#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 +#define CPR0_PERD_PERDV0_MASK 0x07000000 + +#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => + 0x0EF400000 */ + +/* PCI Master Local Configuration Registers */ +#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ +#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ +#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ +#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ +#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ +#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ +#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ +#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ +#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ +#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ +#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ +#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ + +/* PCI Target Local Configuration Registers */ +#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ + Attribute */ +#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ +#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ + Attribute */ +#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ + +/* 440EPx boot strap options */ +#define BOOT_STRAP_OPTION_A 0x00000000 +#define BOOT_STRAP_OPTION_B 0x00000001 +#define BOOT_STRAP_OPTION_D 0x00000003 +#define BOOT_STRAP_OPTION_E 0x00000004 + +#endif /* _PPC440EPX_GRX_H_ */ diff --git a/arch/powerpc/include/asm/ppc440gp.h b/arch/powerpc/include/asm/ppc440gp.h new file mode 100644 index 0000000..3ebe2a1 --- /dev/null +++ b/arch/powerpc/include/asm/ppc440gp.h @@ -0,0 +1,72 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440GP_H_ +#define _PPC440GP_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +#define SDR0_PCI0 0x0300 + +#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) +#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) + +#define CNTRL_DCR_BASE 0x0b0 + +#define CPC0_SYS0 (CNTRL_DCR_BASE + 0x30) /* System configuration reg 0 */ +#define CPC0_SYS1 (CNTRL_DCR_BASE + 0x31) /* System configuration reg 1 */ + +#define CPC0_STRP0 (CNTRL_DCR_BASE + 0x34) /* Power-on config reg 0 (RO) */ +#define CPC0_STRP1 (CNTRL_DCR_BASE + 0x35) /* Power-on config reg 1 (RO) */ + +#define CPC0_GPIO (CNTRL_DCR_BASE + 0x38) /* GPIO config reg (440GP) */ + +#define CPC0_CR0 (CNTRL_DCR_BASE + 0x3b) /* Control 0 register */ +#define CPC0_CR1 (CNTRL_DCR_BASE + 0x3a) /* Control 1 register */ + +#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ +#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ +#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ +#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ +#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ +#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ +#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ +#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ +#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#endif /* _PPC440GP_H_ */ diff --git a/arch/powerpc/include/asm/ppc440gx.h b/arch/powerpc/include/asm/ppc440gx.h new file mode 100644 index 0000000..6f8581b --- /dev/null +++ b/arch/powerpc/include/asm/ppc440gx.h @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440GX_H_ +#define _PPC440GX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* SDR's */ +#define SDR0_PCI0 0x0300 + +#define SDR0_SDSTP2 0x4001 +#define SDR0_SDSTP3 0x4003 + +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) +#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) + +#define SDR0_PFC1_EPS_DECODE(n) ((((u32)(n)) >> 22) & 0x07) +#define SDR0_PFC1_CTEMS_MASK (0x80000000 >> 11) +#define SDR0_PFC1_CTEMS_EMS 0x00000000 +#define SDR0_PFC1_CTEMS_CPUTRACE (0x80000000 >> 11) + +#define SDR0_MFR_ECS_MASK 0x10000000 + +#define SDR0_SRST_DMC 0x00200000 + +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#endif /* _PPC440GX_H_ */ diff --git a/arch/powerpc/include/asm/ppc440sp.h b/arch/powerpc/include/asm/ppc440sp.h new file mode 100644 index 0000000..4387495 --- /dev/null +++ b/arch/powerpc/include/asm/ppc440sp.h @@ -0,0 +1,98 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440SP_H_ +#define _PPC440SP_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* SDR's */ +#define SDR0_PCI0 0x0300 +#define SDR0_SDSTP2 0x0022 +#define SDR0_SDSTP3 0x0023 + +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) +#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) + +#define SDR0_PFC1_EM_1000 (0x80000000 >> 10) + +#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */ + +#define SDR0_SRST0_DMC 0x00200000 + +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#endif /* _PPC440SP_H_ */ diff --git a/arch/powerpc/include/asm/ppc440spe.h b/arch/powerpc/include/asm/ppc440spe.h new file mode 100644 index 0000000..bad9a40 --- /dev/null +++ b/arch/powerpc/include/asm/ppc440spe.h @@ -0,0 +1,114 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC440SPE_H_ +#define _PPC440SPE_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +/* + * Some SoC specific registers (not common for all 440 SoC's) + */ + +/* Memory mapped register */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +/* SDR's */ +#define SDR0_PCI0 0x0300 +#define SDR0_SDSTP2 0x0022 +#define SDR0_SDSTP3 0x0023 + +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) +#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) +#define SDR0_SDSTP1_ERPN_MASK (0x80000000 >> 12) +#define SDR0_SDSTP1_ERPN_EBC 0 +#define SDR0_SDSTP1_ERPN_PCI (0x80000000 >> 12) +#define SDR0_SDSTP1_EBCW_MASK (0x80000000 >> 24) +#define SDR0_SDSTP1_EBCW_8_BITS 0 +#define SDR0_SDSTP1_EBCW_16_BITS (0x80000000 >> 24) + +#define SDR0_PFC1_EM_1000 (0x80000000 >> 10) + +#define SDR0_MFR_FIXD (0x80000000 >> 3) /* Workaround for PCI/DMA */ + +#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 + (EBC boot) */ +#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 + (PCI boot) */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - + Addr = 0x54 */ +#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - + Addr = 0x50 */ + +#define SDR0_SRST0_DMC 0x00200000 + +#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ +#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ +#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ +#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ +#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ +#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ +#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ +#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ + +#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ +#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ +#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ +#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ +#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ +#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ + +#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ +#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ +#define PRADV_MASK 0x07000000 /* Primary Divisor A */ +#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ +#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ + +/* Strap 1 Register */ +#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ +#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ +#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ +#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ +#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ +#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ +#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ +#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ +#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ +#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ +#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ +#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ +#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ +#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ +#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ +#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ +#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#endif /* _PPC440SPE_H_ */ diff --git a/arch/powerpc/include/asm/ppc460ex_gt.h b/arch/powerpc/include/asm/ppc460ex_gt.h new file mode 100644 index 0000000..732fcac --- /dev/null +++ b/arch/powerpc/include/asm/ppc460ex_gt.h @@ -0,0 +1,222 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC460EX_GT_H_ +#define _PPC460EX_GT_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +#define CONFIG_NAND_NDFC + +/* + * Some SoC specific registers + */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0400) +#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_PERIPHERAL_BASE + 0x0500) +#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_PERIPHERAL_BASE + 0x0600) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0b00) +#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0c00) + +/* DCR */ +#define AHB_TOP 0x00a4 +#define AHB_BOT 0x00a5 + +/* SDR */ +#define SDR0_PCI0 0x01c0 +#define SDR0_AHB_CFG 0x0370 +#define SDR0_USB2HOST_CFG 0x0371 +#define SDR0_ETH_PLL 0x4102 +#define SDR0_ETH_CFG 0x4103 +#define SDR0_ETH_STS 0x4104 + +/* + * Register bits and masks + */ +#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) +#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) + +/* CUST0 Customer Configuration Register0 */ +#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ +#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ +#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ +#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ + +#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ +#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ +#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ + +#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ +#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ +#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ + +#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ +#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((u32)(n)) & 0xF) << 24) +#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((u32)(n)) >> 24) & 0xF) + +#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ +#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((u32)(n)) & 0x3) << 22) +#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((u32)(n)) >> 22) & 0x3) + +#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ +#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ + +#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ +#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ +#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ + +#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ +#define SDR0_CUST0_NDRSC_ENCODE(n) ((((u32)(n)) & 0xFFF) << 4) +#define SDR0_CUST0_NDRSC_DECODE(n) ((((u32)(n)) >> 4) & 0xFFF) + +#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ +#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ +#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ +#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ +#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ + +/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ +#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /* Ethernet PLL lock indication */ + +/* Ethernet Configuration Register (SDR0_ETH_CFG) */ +#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback + enable */ +#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ +#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ +#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ +#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ +#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ +#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ +#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ +#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ +#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ +#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ +#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ +#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge + selector */ +#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge + selector */ + +#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ +#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ +#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ +#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ +#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ + transmitter 0 */ +#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ + transmitter 1 */ +#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ +#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ +#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ +#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ +#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ +#define SDR0_SRST0_PCI 0x00100000 /* PCI */ +#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ +#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ +#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ +#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ +#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ +#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ +#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ + transmitter 2 */ +#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ +#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ +#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ +#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ + transmitter 3 */ +#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ + +#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ +#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ +#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ +#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ +#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ +#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access + controller 0 */ +#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access + controller 1 */ +#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access + controller 2 */ +#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access + controller 3 */ +#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ +#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ +#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ +#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ +#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ +#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ +#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and + serdes */ +#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ +#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ +#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ +#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ +#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ +#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ +#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ +#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ +#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ +#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ +#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ +#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ +#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ +#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ +#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ +#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ + +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ + +#define CPR0_ICFG_RLI_MASK 0x80000000 + +#define CPR0_PLLC_RST 0x80000000 +#define CPR0_PLLC_ENG 0x40000000 + +#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) +#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) + +#endif /* _PPC460EX_GT_H_ */ diff --git a/arch/powerpc/include/asm/ppc460sx.h b/arch/powerpc/include/asm/ppc460sx.h new file mode 100644 index 0000000..f93ef0e --- /dev/null +++ b/arch/powerpc/include/asm/ppc460sx.h @@ -0,0 +1,44 @@ +/* + * (C) Copyright 2010 + * Stefan Roese, DENX Software Engineering, sr@denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _PPC460SX_H_ +#define _PPC460SX_H_ + +#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ + +/* Memory mapped registers */ +#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* Internal Peripherals */ + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_PERIPHERAL_BASE + 0x0200) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_PERIPHERAL_BASE + 0x0300) + +#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x0700) + +#define SDR0_SRST0_DMC 0x00200000 + +#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ +#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ +#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ +#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ +#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ +#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ +#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ + +#endif /* _PPC460SX_H_ */ diff --git a/include/ppc4xx_enet.h b/arch/powerpc/include/asm/ppc4xx-emac.h index 3095aed..25a0512 100644 --- a/include/ppc4xx_enet.h +++ b/arch/powerpc/include/asm/ppc4xx-emac.h @@ -44,7 +44,7 @@ #define _PPC4XX_ENET_H_ #include <net.h> -#include "405_mal.h" +#include "asm/ppc4xx-mal.h" /*-----------------------------------------------------------------------------+ @@ -149,12 +149,6 @@ typedef struct emac_4xx_hw_st { #define EMAC_STACR_OC_MASK (0x00000000) #endif -#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EX) -#define SDR0_PFC1_EM_1000 (0x00200000) -#endif - /* * XMII bridge configurations for those systems (e.g. 405EX(r)) that do * not have a pin function control (PFC) register to otherwise determine diff --git a/arch/powerpc/include/asm/gpio.h b/arch/powerpc/include/asm/ppc4xx-gpio.h index 23e29b1..23e29b1 100644 --- a/arch/powerpc/include/asm/gpio.h +++ b/arch/powerpc/include/asm/ppc4xx-gpio.h diff --git a/include/4xx_i2c.h b/arch/powerpc/include/asm/ppc4xx-i2c.h index 0c6c926..0c6c926 100644 --- a/include/4xx_i2c.h +++ b/arch/powerpc/include/asm/ppc4xx-i2c.h diff --git a/include/405_mal.h b/arch/powerpc/include/asm/ppc4xx-mal.h index 1ca9429..7198685 100644 --- a/include/405_mal.h +++ b/arch/powerpc/include/asm/ppc4xx-mal.h @@ -42,6 +42,45 @@ +----------------------------------------------------------------------------*/ #ifndef _mal_h_ #define _mal_h_ + +#if !defined(MAL_DCR_BASE) +#define MAL_DCR_BASE 0x180 +#endif +#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ +#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ +#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ +#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ +#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ +#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ +#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ +#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ +#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ +#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ +#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ +#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ +#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ +#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ +#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ +#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ +#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ +#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ +#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ +#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ +#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ +#if defined(CONFIG_440GX) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) +#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ +#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ +#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ +#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ +#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ +#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ +#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ +#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ +#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ +#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ +#endif /* CONFIG_440GX */ + /* MADMAL transmit and receive status/control bits */ /* for COMMAC bits, refer to the COMMAC header file */ diff --git a/arch/powerpc/include/asm/ppc4xx-sdram.h b/arch/powerpc/include/asm/ppc4xx-sdram.h index 4ec1ef8..ac150c2 100644 --- a/arch/powerpc/include/asm/ppc4xx-sdram.h +++ b/arch/powerpc/include/asm/ppc4xx-sdram.h @@ -951,8 +951,6 @@ #define SDRAM_RTSR_TRK1SM_ATPLS1 0x80000000 /* atpls1 state */ #define SDRAM_RTSR_TRK1SM_RESET 0xC0000000 /* reset state */ -#define SDR0_MFR_FIXD 0x10000000 /* Workaround for PCI/DMA */ - #endif /* CONFIG_SDRAM_PPC4xx_IBM_DDR2 */ #if defined(CONFIG_SDRAM_PPC4xx_DENALI_DDR2) diff --git a/arch/powerpc/include/asm/ppc4xx.h b/arch/powerpc/include/asm/ppc4xx.h new file mode 100644 index 0000000..87a16ec --- /dev/null +++ b/arch/powerpc/include/asm/ppc4xx.h @@ -0,0 +1,344 @@ +/*----------------------------------------------------------------------------+ +| This source code is dual-licensed. You may use it under the terms of +| the GNU General Public License version 2, or under the license below. +| +| This source code has been made available to you by IBM on an AS-IS +| basis. Anyone receiving this source is licensed under IBM +| copyrights to use it in any way he or she deems fit, including +| copying it, modifying it, compiling it, and redistributing it either +| with or without modifications. No license under IBM patents or +| patent applications is to be implied by the copyright license. +| +| Any user of this software should understand that IBM cannot provide +| technical support for this software and will not be responsible for +| any consequences resulting from the use of this software. +| +| Any person who transfers this source code or any derivative work +| must include the IBM copyright notice, this paragraph, and the +| preceding two paragraphs in the transferred software. +| +| COPYRIGHT I B M CORPORATION 1999 +| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M ++----------------------------------------------------------------------------*/ + +#ifndef __PPC4XX_H__ +#define __PPC4XX_H__ + +/* + * Include SoC specific headers + */ +#if defined(CONFIG_405CR) +#include <asm/ppc405cr.h> +#endif + +#if defined(CONFIG_405EP) +#include <asm/ppc405ep.h> +#endif + +#if defined(CONFIG_405EX) +#include <asm/ppc405ex.h> +#endif + +#if defined(CONFIG_405EZ) +#include <asm/ppc405ez.h> +#endif + +#if defined(CONFIG_405GP) +#include <asm/ppc405gp.h> +#endif + +#if defined(CONFIG_440EP) || defined(CONFIG_440GR) +#include <asm/ppc440ep_gr.h> +#endif + +#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) +#include <asm/ppc440epx_grx.h> +#endif + +#if defined(CONFIG_440GP) +#include <asm/ppc440gp.h> +#endif + +#if defined(CONFIG_440GX) +#include <asm/ppc440gx.h> +#endif + +#if defined(CONFIG_440SP) +#include <asm/ppc440sp.h> +#endif + +#if defined(CONFIG_440SPE) +#include <asm/ppc440spe.h> +#endif + +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#include <asm/ppc460ex_gt.h> +#endif + +#if defined(CONFIG_460SX) +#include <asm/ppc460sx.h> +#endif + +/* + * Configure which SDRAM/DDR/DDR2 controller is equipped + */ +// test-only: what to do with these??? +#if defined(CONFIG_AP1000) || defined(CONFIG_ML2) +#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ +#endif + +/* + * Common registers for all SoC's + */ +/* DCR registers */ +#define PLB3A0_ACR 0x0077 +#define PLB4A0_ACR 0x0081 +#define PLB4A1_ACR 0x0089 + +/* CPR register declarations */ + +#define PLB4Ax_ACR_PPM_MASK 0xf0000000 +#define PLB4Ax_ACR_PPM_FIXED 0x00000000 +#define PLB4Ax_ACR_PPM_FAIR 0xd0000000 +#define PLB4Ax_ACR_HBU_MASK 0x08000000 +#define PLB4Ax_ACR_HBU_DISABLED 0x00000000 +#define PLB4Ax_ACR_HBU_ENABLED 0x08000000 +#define PLB4Ax_ACR_RDP_MASK 0x06000000 +#define PLB4Ax_ACR_RDP_DISABLED 0x00000000 +#define PLB4Ax_ACR_RDP_2DEEP 0x02000000 +#define PLB4Ax_ACR_RDP_3DEEP 0x04000000 +#define PLB4Ax_ACR_RDP_4DEEP 0x06000000 +#define PLB4Ax_ACR_WRP_MASK 0x01000000 +#define PLB4Ax_ACR_WRP_DISABLED 0x00000000 +#define PLB4Ax_ACR_WRP_2DEEP 0x01000000 + +/* + * External Bus Controller + */ +/* Values for EBC0_CFGADDR register - indirect addressing of these regs */ +#define PB0CR 0x00 /* periph bank 0 config reg */ +#define PB1CR 0x01 /* periph bank 1 config reg */ +#define PB2CR 0x02 /* periph bank 2 config reg */ +#define PB3CR 0x03 /* periph bank 3 config reg */ +#define PB4CR 0x04 /* periph bank 4 config reg */ +#define PB5CR 0x05 /* periph bank 5 config reg */ +#define PB6CR 0x06 /* periph bank 6 config reg */ +#define PB7CR 0x07 /* periph bank 7 config reg */ +#define PB0AP 0x10 /* periph bank 0 access parameters */ +#define PB1AP 0x11 /* periph bank 1 access parameters */ +#define PB2AP 0x12 /* periph bank 2 access parameters */ +#define PB3AP 0x13 /* periph bank 3 access parameters */ +#define PB4AP 0x14 /* periph bank 4 access parameters */ +#define PB5AP 0x15 /* periph bank 5 access parameters */ +#define PB6AP 0x16 /* periph bank 6 access parameters */ +#define PB7AP 0x17 /* periph bank 7 access parameters */ +#define PBEAR 0x20 /* periph bus error addr reg */ +#define PBESR0 0x21 /* periph bus error status reg 0 */ +#define PBESR1 0x22 /* periph bus error status reg 1 */ +#define EBC0_CFG 0x23 /* external bus configuration reg */ + +/* + * GPIO macro register defines + */ +/* todo: merge with gpio.h header */ +#define GPIO_BASE GPIO0_BASE + +#define GPIO0_OR (GPIO0_BASE + 0x0) +#define GPIO0_TCR (GPIO0_BASE + 0x4) +#define GPIO0_OSRL (GPIO0_BASE + 0x8) +#define GPIO0_OSRH (GPIO0_BASE + 0xC) +#define GPIO0_TSRL (GPIO0_BASE + 0x10) +#define GPIO0_TSRH (GPIO0_BASE + 0x14) +#define GPIO0_ODR (GPIO0_BASE + 0x18) +#define GPIO0_IR (GPIO0_BASE + 0x1C) +#define GPIO0_RR1 (GPIO0_BASE + 0x20) +#define GPIO0_RR2 (GPIO0_BASE + 0x24) +#define GPIO0_RR3 (GPIO0_BASE + 0x28) +#define GPIO0_ISR1L (GPIO0_BASE + 0x30) +#define GPIO0_ISR1H (GPIO0_BASE + 0x34) +#define GPIO0_ISR2L (GPIO0_BASE + 0x38) +#define GPIO0_ISR2H (GPIO0_BASE + 0x3C) +#define GPIO0_ISR3L (GPIO0_BASE + 0x40) +#define GPIO0_ISR3H (GPIO0_BASE + 0x44) + +#define GPIO1_OR (GPIO1_BASE + 0x0) +#define GPIO1_TCR (GPIO1_BASE + 0x4) +#define GPIO1_OSRL (GPIO1_BASE + 0x8) +#define GPIO1_OSRH (GPIO1_BASE + 0xC) +#define GPIO1_TSRL (GPIO1_BASE + 0x10) +#define GPIO1_TSRH (GPIO1_BASE + 0x14) +#define GPIO1_ODR (GPIO1_BASE + 0x18) +#define GPIO1_IR (GPIO1_BASE + 0x1C) +#define GPIO1_RR1 (GPIO1_BASE + 0x20) +#define GPIO1_RR2 (GPIO1_BASE + 0x24) +#define GPIO1_RR3 (GPIO1_BASE + 0x28) +#define GPIO1_ISR1L (GPIO1_BASE + 0x30) +#define GPIO1_ISR1H (GPIO1_BASE + 0x34) +#define GPIO1_ISR2L (GPIO1_BASE + 0x38) +#define GPIO1_ISR2H (GPIO1_BASE + 0x3C) +#define GPIO1_ISR3L (GPIO1_BASE + 0x40) +#define GPIO1_ISR3H (GPIO1_BASE + 0x44) + +/* General Purpose Timer (GPT) Register Offsets */ +#define GPT0_TBC 0x00000000 +#define GPT0_IM 0x00000018 +#define GPT0_ISS 0x0000001C +#define GPT0_ISC 0x00000020 +#define GPT0_IE 0x00000024 +#define GPT0_COMP0 0x00000080 +#define GPT0_COMP1 0x00000084 +#define GPT0_COMP2 0x00000088 +#define GPT0_COMP3 0x0000008C +#define GPT0_COMP4 0x00000090 +#define GPT0_COMP5 0x00000094 +#define GPT0_COMP6 0x00000098 +#define GPT0_MASK0 0x000000C0 +#define GPT0_MASK1 0x000000C4 +#define GPT0_MASK2 0x000000C8 +#define GPT0_MASK3 0x000000CC +#define GPT0_MASK4 0x000000D0 +#define GPT0_MASK5 0x000000D4 +#define GPT0_MASK6 0x000000D8 +#define GPT0_DCT0 0x00000110 +#define GPT0_DCIS 0x0000011C + +#if 0 // test-only +/* + * All PPC4xx share the same NS16550 UART(s). Only base addresses + * may differ. We define here the integration of the common NS16550 + * driver for all PPC4xx SoC's. The board config header must specify + * on which UART the console should be located via CONFIG_CONS_INDEX. + */ +#if 0 /* test-only */ +#define CONFIG_SERIAL_MULTI +#endif +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#endif + +#if defined(CONFIG_440) +#include <asm/ppc440.h> +#else +#include <asm/ppc405.h> +#endif + +#include <asm/ppc4xx-sdram.h> +#include <asm/ppc4xx-ebc.h> +#if !defined(CONFIG_XILINX_440) +#include <asm/ppc4xx-uic.h> +#endif + +/* + * Macro for generating register field mnemonics + */ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + +/* + * Elide casts when assembling register mnemonics + */ +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + +/* + * Common stuff for 4xx (405 and 440) + */ + +#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ +#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) + +#define RESET_VECTOR 0xfffffffc +#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for + cache line aligned data. */ + +#define CPR0_DCR_BASE 0x0C +#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) +#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) + +#define SDR_DCR_BASE 0x0E +#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) +#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) + +#define SDRAM_DCR_BASE 0x10 +#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) +#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) + +#define EBC_DCR_BASE 0x12 +#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) +#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) + +/* + * Macros for indirect DCR access + */ +#define mtcpr(reg, d) \ + do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) +#define mfcpr(reg, d) \ + do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) + +#define mtebc(reg, d) \ + do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) +#define mfebc(reg, d) \ + do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) + +#define mtsdram(reg, d) \ + do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) +#define mfsdram(reg, d) \ + do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) + +#define mtsdr(reg, d) \ + do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) +#define mfsdr(reg, d) \ + do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) + +#ifndef __ASSEMBLY__ + +typedef struct +{ + unsigned long freqDDR; + unsigned long freqEBC; + unsigned long freqOPB; + unsigned long freqPCI; + unsigned long freqPLB; + unsigned long freqTmrClk; + unsigned long freqUART; + unsigned long freqProcessor; + unsigned long freqVCOHz; + unsigned long freqVCOMhz; /* in MHz */ + unsigned long pciClkSync; /* PCI clock is synchronous */ + unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ + unsigned long pllExtBusDiv; + unsigned long pllFbkDiv; + unsigned long pllFwdDiv; + unsigned long pllFwdDivA; + unsigned long pllFwdDivB; + unsigned long pllOpbDiv; + unsigned long pllPciDiv; + unsigned long pllPlbDiv; +} PPC4xx_SYS_INFO; + +static inline u32 get_mcsr(void) +{ + u32 val; + + asm volatile("mfspr %0, 0x23c" : "=r" (val) :); + return val; +} + +static inline void set_mcsr(u32 val) +{ + asm volatile("mtspr 0x23c, %0" : "=r" (val) :); +} + +int ppc4xx_pci_sync_clock_config(u32 async); + +#endif /* __ASSEMBLY__ */ + +/* for multi-cpu support */ +#define NA_OR_UNKNOWN_CPU -1 + +#endif /* __PPC4XX_H__ */ diff --git a/arch/powerpc/lib/board.c b/arch/powerpc/lib/board.c index 628d067..8f6a7c9 100644 --- a/arch/powerpc/lib/board.c +++ b/arch/powerpc/lib/board.c @@ -118,16 +118,6 @@ extern int board_start_ide(void); DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_ENV_IS_EMBEDDED) -#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN -#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ - (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \ - defined(CONFIG_ENV_IS_IN_NVRAM) -#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) -#else -#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN -#endif - #if !defined(CONFIG_SYS_MEM_TOP_HIDE) #define CONFIG_SYS_MEM_TOP_HIDE 0 #endif @@ -519,15 +509,12 @@ void board_init_f (ulong bootflag) bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; /* start of DRAM memory */ bd->bi_memsize = gd->ram_size; /* size of DRAM memory in bytes */ -#ifdef CONFIG_IP860 - bd->bi_sramstart = SRAM_BASE; /* start of SRAM memory */ - bd->bi_sramsize = SRAM_SIZE; /* size of SRAM memory */ -#elif defined CONFIG_MPC8220 +#ifdef CONFIG_SYS_SRAM_BASE bd->bi_sramstart = CONFIG_SYS_SRAM_BASE; /* start of SRAM memory */ bd->bi_sramsize = CONFIG_SYS_SRAM_SIZE; /* size of SRAM memory */ #else - bd->bi_sramstart = 0; /* FIXME */ /* start of SRAM memory */ - bd->bi_sramsize = 0; /* FIXME */ /* size of SRAM memory */ + bd->bi_sramstart = 0; + bd->bi_sramsize = 0; #endif #if defined(CONFIG_8xx) || defined(CONFIG_8260) || defined(CONFIG_5xx) || \ @@ -914,13 +901,6 @@ void board_init_r (gd_t *id, ulong dest_addr) */ interrupt_init (); - /* Must happen after interrupts are initialized since - * an irq handler gets installed - */ -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - #if defined(CONFIG_STATUS_LED) && defined(STATUS_LED_BOOT) status_led_set (STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif diff --git a/arch/sh/include/asm/global_data.h b/arch/sh/include/asm/global_data.h index c12b855..0c09ba9 100644 --- a/arch/sh/include/asm/global_data.h +++ b/arch/sh/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2007 @@ -38,15 +38,17 @@ typedef struct global_data unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid */ void **jt; /* Standalone app jump table */ -}gd_t; + char env_buf[32]; /* buffer for getenv() before reloc. */ +} gd_t; -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register gd_t *gd asm ("r13") diff --git a/arch/sparc/include/asm/global_data.h b/arch/sparc/include/asm/global_data.h index dea2857..7c1ac0d 100644 --- a/arch/sparc/include/asm/global_data.h +++ b/arch/sparc/include/asm/global_data.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2002 + * (C) Copyright 2002-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2007 @@ -70,19 +70,21 @@ typedef struct global_data { #ifdef CONFIG_LWMON unsigned long kbd_status; #endif - void **jt; /* jump table */ + void **jt; /* jump table */ + char env_buf[32]; /* buffer for getenv() before reloc. */ } gd_t; /* * Global Data Flags */ -#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ -#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ -#define GD_FLG_SILENT 0x00004 /* Silent mode */ -#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ -#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ -#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ -#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_RELOC 0x00001 /* Code was relocated to RAM */ +#define GD_FLG_DEVINIT 0x00002 /* Devices have been initialized */ +#define GD_FLG_SILENT 0x00004 /* Silent mode */ +#define GD_FLG_POSTFAIL 0x00008 /* Critical POST test failed */ +#define GD_FLG_POSTSTOP 0x00010 /* POST seqeunce aborted */ +#define GD_FLG_LOGINIT 0x00020 /* Log Buffer has been initialized */ +#define GD_FLG_DISABLE_CONSOLE 0x00040 /* Disable console (in & out) */ +#define GD_FLG_ENV_READY 0x00080 /* Environment imported into hash table */ #define DECLARE_GLOBAL_DATA_PTR register volatile gd_t *gd asm ("%g7") diff --git a/arch/sparc/lib/board.c b/arch/sparc/lib/board.c index 4f69709..09bcdb0 100644 --- a/arch/sparc/lib/board.c +++ b/arch/sparc/lib/board.c @@ -252,33 +252,13 @@ void board_init_f(ulong bootflag) post_run(NULL, POST_ROM | post_bootmode_get(0)); #endif +#if !defined(CONFIG_RELOC_FIXUP_WORKS) /* * We have to relocate the command table manually */ - for (cmdtp = &__u_boot_cmd_start; cmdtp != &__u_boot_cmd_end; cmdtp++) { - ulong addr; - addr = (ulong) (cmdtp->cmd) + gd->reloc_off; -#if DEBUG_COMMANDS - printf("Command \"%s\": 0x%08lx => 0x%08lx\n", - cmdtp->name, (ulong) (cmdtp->cmd), addr); -#endif - cmdtp->cmd = - (int (*)(struct cmd_tbl_s *, int, int, char *[]))addr; - - addr = (ulong) (cmdtp->name) + gd->reloc_off; - cmdtp->name = (char *)addr; - - if (cmdtp->usage) { - addr = (ulong) (cmdtp->usage) + gd->reloc_off; - cmdtp->usage = (char *)addr; - } -#ifdef CONFIG_SYS_LONGHELP - if (cmdtp->help) { - addr = (ulong) (cmdtp->help) + gd->reloc_off; - cmdtp->help = (char *)addr; - } -#endif - } + fixup_cmdtable(&__u_boot_cmd_start, + (ulong)(&__u_boot_cmd_end - &__u_boot_cmd_start)); +#endif /* !defined(CONFIG_RELOC_FIXUP_WORKS) */ #if defined(CONFIG_CMD_AMBAPP) && defined(CONFIG_SYS_AMBAPP_PRINT_ON_STARTUP) puts("AMBA:\n"); @@ -379,10 +359,6 @@ void board_init_f(ulong bootflag) /* Initialize the console (after the relocation and devices init) */ console_init_r(); -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - serial_buffered_init(); -#endif - #ifdef CONFIG_STATUS_LED status_led_set(STATUS_LED_BOOT, STATUS_LED_BLINKING); #endif diff --git a/board/amcc/acadia/memory.c b/board/amcc/acadia/memory.c index 8c2addc..703a668 100644 --- a/board/amcc/acadia/memory.c +++ b/board/amcc/acadia/memory.c @@ -29,7 +29,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> extern void board_pll_init_f(void); diff --git a/board/amcc/acadia/pll.c b/board/amcc/acadia/pll.c index b63813c..6327d6c 100644 --- a/board/amcc/acadia/pll.c +++ b/board/amcc/acadia/pll.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/processor.h> -#include <ppc405.h> +#include <asm/ppc405.h> /* test-only: move into cpu directory!!! */ @@ -53,9 +53,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x0000033c); mtcpr(CPR0_PLLD, 0x0c010200); - mtcpr(CPC0_PRIMAD, 0x04060c0c); - mtcpr(CPC0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPR0_CLKUP, 0x40000000); + mtcpr(CPR0_PRIMAD, 0x04060c0c); + mtcpr(CPR0_PERD0, 0x000c0000); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_CLKUPD, 0x40000000); } #elif defined(PLLMR0_266_160_80) @@ -85,10 +85,10 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x20000238); mtcpr(CPR0_PLLD, 0x03010400); - mtcpr(CPC0_PRIMAD, 0x03050a0a); - mtcpr(CPC0_PERC0, 0x00000000); - mtcpr(CPC0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0x07323200); + mtcpr(CPR0_PRIMAD, 0x03050a0a); + mtcpr(CPR0_PERC0, 0x00000000); + mtcpr(CPR0_PERD0, 0x070a0707); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0x07323200); mtcpr(CPR0_CLKUP, 0x40000000); } @@ -119,9 +119,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x0000033C); mtcpr(CPR0_PLLD, 0x0a010000); - mtcpr(CPC0_PRIMAD, 0x02040808); - mtcpr(CPC0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0xA6A60300); + mtcpr(CPR0_PRIMAD, 0x02040808); + mtcpr(CPR0_PERD0, 0x02080505); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0xA6A60300); mtcpr(CPR0_CLKUP, 0x40000000); } @@ -145,9 +145,9 @@ void board_pll_init_f(void) /* Initialize PLL */ mtcpr(CPR0_PLLC, 0x000003BC); mtcpr(CPR0_PLLD, 0x06060600); - mtcpr(CPC0_PRIMAD, 0x02020004); - mtcpr(CPC0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ - mtcpr(CPC0_PERD1, 0xC8C81600); + mtcpr(CPR0_PRIMAD, 0x02020004); + mtcpr(CPR0_PERD0, 0x04002828); /* SPI clk div. eq. OPB clk div. */ + mtcpr(CPR0_PERD1, 0xC8C81600); mtcpr(CPR0_CLKUP, 0x40000000); } #endif /* CPU_<speed>_405EZ */ @@ -172,7 +172,7 @@ unsigned long get_tbclk(void) /* * Read CPR_PRIMAD register */ - mfcpr(CPC0_PRIMAD, cpr_primad); + mfcpr(CPR0_PRIMAD, cpr_primad); /* * Determine CPU clock frequency diff --git a/board/amcc/bamboo/bamboo.c b/board/amcc/bamboo/bamboo.c index c90f86b..d4205e0 100644 --- a/board/amcc/bamboo/bamboo.c +++ b/board/amcc/bamboo/bamboo.c @@ -23,9 +23,9 @@ #include <common.h> #include <asm/processor.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <spd_sdram.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include "bamboo.h" void ext_bus_cntlr_init(void); @@ -554,7 +554,7 @@ void ext_bus_cntlr_init(void) | +-------------------------------------------------------------------------*/ /* Read Pin Strap Register in PPC440EP */ - mfsdr(sdr_pstrp0, sdr0_pstrp0); + mfsdr(SDR0_PINSTP, sdr0_pstrp0); bootstrap_settings = sdr0_pstrp0 & SDR0_PSTRP0_BOOTSTRAP_MASK; /*-------------------------------------------------------------------------+ diff --git a/board/amcc/bamboo/bamboo.h b/board/amcc/bamboo/bamboo.h index 4474862..f2b78a9 100644 --- a/board/amcc/bamboo/bamboo.h +++ b/board/amcc/bamboo/bamboo.h @@ -110,17 +110,6 @@ /*----------------------------------------------------------------------------+ | SDR Configuration registers +----------------------------------------------------------------------------*/ -/* Serial Device Strap Reg 0 */ -#define SDR0_SDSTP0 0x0020 -/* Serial Device Strap Reg 1 */ -#define SDR0_SDSTP1 0x0021 -/* Serial Device Strap Reg 2 */ -#define SDR0_SDSTP2 SDR0_STRP2 -/* Serial Device Strap Reg 3 */ -#define SDR0_SDSTP3 SDR0_STRP3 - -#define sdr_pstrp0 0x0040 - #define SDR0_SDSTP1_EBC_ROM_BS_MASK 0x00006000 /* EBC Boot Size Mask */ #define SDR0_SDSTP1_EBC_ROM_BS_32BIT 0x00004000 /* EBC 32 bits */ #define SDR0_SDSTP1_EBC_ROM_BS_16BIT 0x00002000 /* EBC 16 Bits */ diff --git a/board/amcc/bamboo/flash.c b/board/amcc/bamboo/flash.c index 7bf877d..07d185f 100644 --- a/board/amcc/bamboo/flash.c +++ b/board/amcc/bamboo/flash.c @@ -32,9 +32,9 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include "bamboo.h" #undef DEBUG @@ -86,7 +86,7 @@ unsigned long flash_init(void) unsigned long ebc_boot_size; unsigned long boot_selection; - mfsdr(sdr_pstrp0, val); + mfsdr(SDR0_PINSTP, val); index = (val & SDR0_PSTRP0_BOOTSTRAP_MASK) >> 29; if ((index == 5) || (index == 7)) { diff --git a/board/amcc/bubinga/flash.c b/board/amcc/bubinga/flash.c index baf89d5..4850fe1 100644 --- a/board/amcc/bubinga/flash.c +++ b/board/amcc/bubinga/flash.c @@ -29,7 +29,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 158f7bb..b26cadb 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <libfdt.h> #include <fdt_support.h> #include <i2c.h> @@ -27,7 +27,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/4xx_pcie.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/errno.h> extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/amcc/canyonlands/config.mk b/board/amcc/canyonlands/config.mk index 7a58665..3d6a608 100644 --- a/board/amcc/canyonlands/config.mk +++ b/board/amcc/canyonlands/config.mk @@ -27,7 +27,7 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE -TEXT_BASE = 0xFFFA0000 +TEXT_BASE = 0xFFF80000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/common/flash.c b/board/amcc/common/flash.c index 9aaf256..8f23375 100644 --- a/board/amcc/common/flash.c +++ b/board/amcc/common/flash.c @@ -32,7 +32,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/amcc/ebony/flash.c b/board/amcc/ebony/flash.c index 79d2c4c..df7716c 100644 --- a/board/amcc/ebony/flash.c +++ b/board/amcc/ebony/flash.c @@ -32,7 +32,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/board/amcc/ebony/init.S b/board/amcc/ebony/init.S index c911763..08a0d11 100644 --- a/board/amcc/ebony/init.S +++ b/board/amcc/ebony/init.S @@ -23,6 +23,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/katmai/init.S b/board/amcc/katmai/init.S index 59ccf2b..4a42f1f 100644 --- a/board/amcc/katmai/init.S +++ b/board/amcc/katmai/init.S @@ -26,6 +26,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/katmai/katmai.c b/board/amcc/katmai/katmai.c index 0bbc75e..7301cd5 100644 --- a/board/amcc/katmai/katmai.c +++ b/board/amcc/katmai/katmai.c @@ -23,14 +23,14 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <libfdt.h> #include <fdt_support.h> #include <netdev.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/4xx_pcie.h> #include <asm/errno.h> diff --git a/board/amcc/kilauea/kilauea.c b/board/amcc/kilauea/kilauea.c index 646f431..bd6550c 100644 --- a/board/amcc/kilauea/kilauea.c +++ b/board/amcc/kilauea/kilauea.c @@ -22,8 +22,8 @@ */ #include <common.h> -#include <ppc4xx.h> -#include <ppc405.h> +#include <asm/ppc4xx.h> +#include <asm/ppc405.h> #include <libfdt.h> #include <fdt_support.h> #include <asm/processor.h> diff --git a/board/amcc/luan/config.mk b/board/amcc/luan/config.mk index cd02aab..5e4182d 100644 --- a/board/amcc/luan/config.mk +++ b/board/amcc/luan/config.mk @@ -30,7 +30,7 @@ ifeq ($(ramsym),1) TEXT_BASE = 0xFBD00000 else -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFFB0000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/luan/flash.c b/board/amcc/luan/flash.c index 2d3b154..8088509 100644 --- a/board/amcc/luan/flash.c +++ b/board/amcc/luan/flash.c @@ -32,7 +32,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #undef DEBUG diff --git a/board/amcc/luan/init.S b/board/amcc/luan/init.S index 06428d2..7cca319 100644 --- a/board/amcc/luan/init.S +++ b/board/amcc/luan/init.S @@ -26,6 +26,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/luan/luan.c b/board/amcc/luan/luan.c index c09d730..b2595a8 100644 --- a/board/amcc/luan/luan.c +++ b/board/amcc/luan/luan.c @@ -23,7 +23,7 @@ #include <common.h> #include <command.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/ppc4xx-isram.h> #include <spd_sdram.h> diff --git a/board/amcc/makalu/makalu.c b/board/amcc/makalu/makalu.c index 4afe091..483df66 100644 --- a/board/amcc/makalu/makalu.c +++ b/board/amcc/makalu/makalu.c @@ -22,11 +22,11 @@ */ #include <common.h> -#include <ppc4xx.h> -#include <ppc405.h> +#include <asm/ppc4xx.h> +#include <asm/ppc405.h> #include <libfdt.h> #include <asm/processor.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/io.h> #include <fdt_support.h> #include <asm/errno.h> diff --git a/board/amcc/ocotea/flash.c b/board/amcc/ocotea/flash.c index a83f93a..fbc552b 100644 --- a/board/amcc/ocotea/flash.c +++ b/board/amcc/ocotea/flash.c @@ -32,7 +32,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #undef DEBUG diff --git a/board/amcc/ocotea/init.S b/board/amcc/ocotea/init.S index 2ef11cc..39f5a02 100644 --- a/board/amcc/ocotea/init.S +++ b/board/amcc/ocotea/init.S @@ -23,6 +23,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/ocotea/ocotea.c b/board/amcc/ocotea/ocotea.c index 7bffa3c..bbb5331 100644 --- a/board/amcc/ocotea/ocotea.c +++ b/board/amcc/ocotea/ocotea.c @@ -28,7 +28,7 @@ #include "ocotea.h" #include <asm/processor.h> #include <spd_sdram.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/amcc/redwood/init.S b/board/amcc/redwood/init.S index fb10520..47f700b 100644 --- a/board/amcc/redwood/init.S +++ b/board/amcc/redwood/init.S @@ -24,6 +24,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/redwood/redwood.c b/board/amcc/redwood/redwood.c index 32fb8c5..bb7565e 100644 --- a/board/amcc/redwood/redwood.c +++ b/board/amcc/redwood/redwood.c @@ -26,7 +26,7 @@ #include <common.h> #include "redwood.h" -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <i2c.h> #include <asm/io.h> diff --git a/board/amcc/sequoia/config.mk b/board/amcc/sequoia/config.mk index b57e473..c8e2dff 100644 --- a/board/amcc/sequoia/config.mk +++ b/board/amcc/sequoia/config.mk @@ -27,11 +27,7 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE -TEXT_BASE = 0xFFFA0000 -# -# When defining CONFIG_VIDEO, TEXT_BASE needs to be 0xFFF80000 -# TEXT_BASE = 0xFFF80000 -# +TEXT_BASE = 0xFFF80000 endif PLATFORM_CPPFLAGS += -DCONFIG_440=1 diff --git a/board/amcc/sequoia/sdram.c b/board/amcc/sequoia/sdram.c index cabeceb..5c01def 100644 --- a/board/amcc/sequoia/sdram.c +++ b/board/amcc/sequoia/sdram.c @@ -31,7 +31,7 @@ #include <common.h> #include <asm/processor.h> #include <asm/io.h> -#include <ppc440.h> +#include <asm/ppc440.h> /*-----------------------------------------------------------------------------+ * Prototypes diff --git a/board/amcc/sequoia/sequoia.c b/board/amcc/sequoia/sequoia.c index 6756a27..c523bca 100644 --- a/board/amcc/sequoia/sequoia.c +++ b/board/amcc/sequoia/sequoia.c @@ -25,8 +25,8 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> -#include <ppc4xx.h> -#include <asm/gpio.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-gpio.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/bitops.h> @@ -321,8 +321,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; - mtdcr(PLB4_ACR, reg); + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); return 0; } diff --git a/board/amcc/taihu/flash.c b/board/amcc/taihu/flash.c index 497fdb9..e9fbbb1 100644 --- a/board/amcc/taihu/flash.c +++ b/board/amcc/taihu/flash.c @@ -29,7 +29,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/amcc/taihu/lcd.c b/board/amcc/taihu/lcd.c index 9b2afda..15cfcb0 100644 --- a/board/amcc/taihu/lcd.c +++ b/board/amcc/taihu/lcd.c @@ -22,7 +22,7 @@ #include <common.h> #include <command.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #define LCD_CMD_ADDR 0x50100002 #define LCD_DATA_ADDR 0x50100003 diff --git a/board/amcc/taihu/taihu.c b/board/amcc/taihu/taihu.c index dd2aba5..87c9403 100644 --- a/board/amcc/taihu/taihu.c +++ b/board/amcc/taihu/taihu.c @@ -29,7 +29,7 @@ #include <asm/io.h> #include <spi.h> #include <netdev.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> extern int lcd_init(void); diff --git a/board/amcc/taishan/init.S b/board/amcc/taishan/init.S index ac4e95d..6d47851 100644 --- a/board/amcc/taishan/init.S +++ b/board/amcc/taishan/init.S @@ -24,6 +24,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/taishan/taishan.c b/board/amcc/taishan/taishan.c index cac7a78..2957a77 100644 --- a/board/amcc/taishan/taishan.c +++ b/board/amcc/taishan/taishan.c @@ -26,7 +26,7 @@ #include <common.h> #include <asm/processor.h> #include <spd_sdram.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> #include <netdev.h> #ifdef CONFIG_SYS_INIT_SHOW_RESET_REG diff --git a/board/amcc/walnut/flash.c b/board/amcc/walnut/flash.c index 3dc6aab..f72e278 100644 --- a/board/amcc/walnut/flash.c +++ b/board/amcc/walnut/flash.c @@ -29,7 +29,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #undef DEBUG diff --git a/board/amcc/yosemite/yosemite.c b/board/amcc/yosemite/yosemite.c index 98c1f3b..aaeab6f 100644 --- a/board/amcc/yosemite/yosemite.c +++ b/board/amcc/yosemite/yosemite.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <spd_sdram.h> diff --git a/board/amcc/yucca/flash.c b/board/amcc/yucca/flash.c index 5fab7bb..20b6af9 100644 --- a/board/amcc/yucca/flash.c +++ b/board/amcc/yucca/flash.c @@ -32,9 +32,9 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include "yucca.h" #ifdef DEBUG diff --git a/board/amcc/yucca/init.S b/board/amcc/yucca/init.S index b2ac3ca..c63002b 100644 --- a/board/amcc/yucca/init.S +++ b/board/amcc/yucca/init.S @@ -26,6 +26,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/amcc/yucca/yucca.c b/board/amcc/yucca/yucca.c index 0d23929..b128e46 100644 --- a/board/amcc/yucca/yucca.c +++ b/board/amcc/yucca/yucca.c @@ -26,7 +26,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <netdev.h> #include <asm/processor.h> diff --git a/board/amirix/ap1000/init.S b/board/amirix/ap1000/init.S index 65f13e1..eac7cd3 100644 --- a/board/amirix/ap1000/init.S +++ b/board/amirix/ap1000/init.S @@ -16,7 +16,7 @@ * */ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/amirix/ap1000/pci.c b/board/amirix/ap1000/pci.c index 5fbcd37..d021164 100644 --- a/board/amirix/ap1000/pci.c +++ b/board/amirix/ap1000/pci.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <pci.h> diff --git a/board/canmb/canmb.c b/board/canmb/canmb.c index 6ddc858..6c3d2ac 100644 --- a/board/canmb/canmb.c +++ b/board/canmb/canmb.c @@ -106,9 +106,9 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS0 only */ sdram_start(0); - test1 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + test1 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); sdram_start(1); - test2 = get_ram_size((ulong *)CONFIG_SYS_SDRAM_BASE, 0x80000000); + test2 = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE, 0x80000000); if (test1 > test2) { sdram_start(0); dramsize = test1; @@ -134,10 +134,10 @@ phys_size_t initdram (int board_type) /* find RAM size using SDRAM CS1 only */ if (!dramsize) sdram_start(0); - test2 = test1 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); + test2 = test1 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); if (!dramsize) { sdram_start(1); - test2 = get_ram_size((ulong *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); + test2 = get_ram_size((long *)(CONFIG_SYS_SDRAM_BASE + dramsize), 0x80000000); } if (test1 > test2) { sdram_start(0); diff --git a/board/cray/L1/L1.c b/board/cray/L1/L1.c index 33f2089..0f5f02c 100644 --- a/board/cray/L1/L1.c +++ b/board/cray/L1/L1.c @@ -23,7 +23,7 @@ #include <common.h> #include <asm/processor.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx-i2c.h> #include <command.h> #include <rtc.h> #include <post.h> diff --git a/board/cray/L1/flash.c b/board/cray/L1/flash.c index 36d186f..a3d893e 100644 --- a/board/cray/L1/flash.c +++ b/board/cray/L1/flash.c @@ -35,7 +35,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* The flash chip we use... */ diff --git a/board/cray/L1/init.S b/board/cray/L1/init.S index e8dbb93..1662141 100644 --- a/board/cray/L1/init.S +++ b/board/cray/L1/init.S @@ -41,7 +41,7 @@ /* Bank 6 - not used */ /* Bank 7 - FPGA registers */ /*-----------------------------------------------------------------------------#include <config.h> */ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/csb272/csb272.c b/board/csb272/csb272.c index 1ed3e1b..e248aa7 100644 --- a/board/csb272/csb272.c +++ b/board/csb272/csb272.c @@ -25,7 +25,7 @@ #include <asm/processor.h> #include <i2c.h> #include <miiphy.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> void sdram_init(void); diff --git a/board/csb272/init.S b/board/csb272/init.S index a6b0d40..82c6fdb 100644 --- a/board/csb272/init.S +++ b/board/csb272/init.S @@ -22,7 +22,7 @@ * *****************************************************************************/ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/csb472/csb472.c b/board/csb472/csb472.c index c138b0d..25709f2 100644 --- a/board/csb472/csb472.c +++ b/board/csb472/csb472.c @@ -25,7 +25,7 @@ #include <asm/processor.h> #include <i2c.h> #include <miiphy.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> void sdram_init(void); diff --git a/board/csb472/init.S b/board/csb472/init.S index b31bd04..e00b5f5 100644 --- a/board/csb472/init.S +++ b/board/csb472/init.S @@ -22,7 +22,7 @@ * *****************************************************************************/ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/dave/PPChameleonEVB/flash.c b/board/dave/PPChameleonEVB/flash.c index 237c807..2e1a9ab 100644 --- a/board/dave/PPChameleonEVB/flash.c +++ b/board/dave/PPChameleonEVB/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/dave/common/pci.c b/board/dave/common/pci.c index ddfbea9..3036799 100644 --- a/board/dave/common/pci.c +++ b/board/dave/common/pci.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <pci.h> diff --git a/board/davedenx/qong/config.mk b/board/davedenx/qong/config.mk index d8d0a57..39c1203 100644 --- a/board/davedenx/qong/config.mk +++ b/board/davedenx/qong/config.mk @@ -1 +1,3 @@ -TEXT_BASE = 0x8ff00000 +TEXT_BASE = 0xa0000000 + +# PLATFORM_CPPFLAGS += -DDEBUG diff --git a/board/davedenx/qong/qong.c b/board/davedenx/qong/qong.c index 781333b..e509383 100644 --- a/board/davedenx/qong/qong.c +++ b/board/davedenx/qong/qong.c @@ -33,10 +33,9 @@ DECLARE_GLOBAL_DATA_PTR; int dram_init (void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, - PHYS_SDRAM_1_SIZE); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); return 0; } @@ -49,6 +48,49 @@ static void qong_fpga_reset(void) udelay(300); } +int board_early_init_f (void) +{ +#ifdef CONFIG_QONG_FPGA + /* CS1: FPGA/Network Controller/GPIO */ + /* 16-bit, no DTACK */ + __REG(CSCR_U(1)) = 0x00000A01; + __REG(CSCR_L(1)) = 0x20040501; + __REG(CSCR_A(1)) = 0x04020C00; + + /* setup pins for FPGA */ + mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); + mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); + mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); + mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); + mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); + + /* FPGA reset Pin */ + /* rstn = 0 */ + mx31_gpio_set(QONG_FPGA_RST_PIN, 0); + mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); + + /* set interrupt pin as input */ + mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); + +#endif + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); + + /* setup pins for SPI (pmic) */ + mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); + mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); + mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); + mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); + mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); + + return 0; + +} + int board_init (void) { /* Chip selects */ @@ -99,43 +141,6 @@ int board_init (void) (0 << 0) /* FCE */ ); -#ifdef CONFIG_QONG_FPGA - /* CS1: FPGA/Network Controller/GPIO */ - /* 16-bit, no DTACK */ - __REG(CSCR_U(1)) = 0x00000A01; - __REG(CSCR_L(1)) = 0x20040501; - __REG(CSCR_A(1)) = 0x04020C00; - - /* setup pins for FPGA */ - mx31_gpio_mux(IOMUX_MODE(0x76, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x7e, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x91, MUX_CTL_OUT_FUNC | MUX_CTL_IN_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x92, MUX_CTL_GPIO)); - mx31_gpio_mux(IOMUX_MODE(0x93, MUX_CTL_GPIO)); - - /* FPGA reset Pin */ - /* rstn = 0 */ - mx31_gpio_set(QONG_FPGA_RST_PIN, 0); - mx31_gpio_direction(QONG_FPGA_RST_PIN, MX31_GPIO_DIRECTION_OUT); - - /* set interrupt pin as input */ - mx31_gpio_direction(QONG_FPGA_IRQ_PIN, MX31_GPIO_DIRECTION_IN); - -#endif - - /* setup pins for UART1 */ - mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); - mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); - mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); - mx31_gpio_mux(MUX_CTS1__UART1_CTS_B); - - /* setup pins for SPI (pmic) */ - mx31_gpio_mux(MUX_CSPI2_SS0__CSPI2_SS0_B); - mx31_gpio_mux(MUX_CSPI2_MOSI__CSPI2_MOSI); - mx31_gpio_mux(MUX_CSPI2_MISO__CSPI2_MISO); - mx31_gpio_mux(MUX_CSPI2_SCLK__CSPI2_CLK); - mx31_gpio_mux(MUX_CSPI2_SPI_RDY__CSPI2_DATAREADY_B); - /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_QONG; gd->bd->bi_boot_params = (0x80000100); /* adress of boot parameters */ diff --git a/board/davinci/common/misc.c b/board/davinci/common/misc.c index 25ca326..86a875e 100644 --- a/board/davinci/common/misc.c +++ b/board/davinci/common/misc.c @@ -33,6 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { gd->bd->bi_dram[0].start = PHYS_SDRAM_1; @@ -40,6 +41,22 @@ int dram_init(void) return(0); } +#else +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size( + (volatile void *)CONFIG_SYS_SDRAM_BASE, + CONFIG_MAX_RAM_BANK_SIZE); + return 0; +} + +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = gd->ram_size; +} +#endif #ifdef CONFIG_DRIVER_TI_EMAC diff --git a/board/eric/flash.c b/board/eric/flash.c index fded412..7459873 100644 --- a/board/eric/flash.c +++ b/board/eric/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/eric/init.S b/board/eric/init.S index c18663a..1902241 100644 --- a/board/eric/init.S +++ b/board/eric/init.S @@ -35,7 +35,7 @@ /* */ /*----------------------------------------------------------------------------- */ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/esd/adciop/flash.c b/board/esd/adciop/flash.c index dd578c8..9559efb 100644 --- a/board/esd/adciop/flash.c +++ b/board/esd/adciop/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/apc405/apc405.c b/board/esd/apc405/apc405.c index 564ee00..52477d7 100644 --- a/board/esd/apc405/apc405.c +++ b/board/esd/apc405/apc405.c @@ -30,6 +30,7 @@ #include <command.h> #include <malloc.h> #include <flash.h> +#include <mtd/cfi_flash.h> #include <asm/4xx_pci.h> #include <pci.h> @@ -39,9 +40,6 @@ DECLARE_GLOBAL_DATA_PTR; extern int do_reset (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); extern void lxt971_no_sleep(void); -extern ulong flash_get_size (ulong base, int banknum); - -int flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; /* fpga configuration data - gzip compressed and generated by bin2c */ const unsigned char fpgadata[] = @@ -185,7 +183,7 @@ int board_early_init_f (void) int board_early_init_r(void) { if (gd->board_type >= 8) - flash_banks = 1; + cfi_flash_num_flash_banks = 1; return 0; } diff --git a/board/esd/ar405/flash.c b/board/esd/ar405/flash.c index a53122b..895a836 100644 --- a/board/esd/ar405/flash.c +++ b/board/esd/ar405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/ash405/flash.c b/board/esd/ash405/flash.c index a53122b..895a836 100644 --- a/board/esd/ash405/flash.c +++ b/board/esd/ash405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/canbt/flash.c b/board/esd/canbt/flash.c index 224dde4..b210281 100644 --- a/board/esd/canbt/flash.c +++ b/board/esd/canbt/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/cms700/flash.c b/board/esd/cms700/flash.c index a53122b..895a836 100644 --- a/board/esd/cms700/flash.c +++ b/board/esd/cms700/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/common/flash.c b/board/esd/common/flash.c index 38a58fb..b9c7885 100644 --- a/board/esd/common/flash.c +++ b/board/esd/common/flash.c @@ -23,7 +23,7 @@ #include <common.h> #ifdef __PPC__ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #endif #include <asm/processor.h> diff --git a/board/esd/common/pci.c b/board/esd/common/pci.c index 83f8103..11e55c5 100644 --- a/board/esd/common/pci.c +++ b/board/esd/common/pci.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <pci.h> diff --git a/board/esd/cpci2dp/flash.c b/board/esd/cpci2dp/flash.c index 224dde4..b210281 100644 --- a/board/esd/cpci2dp/flash.c +++ b/board/esd/cpci2dp/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/cpci405/flash.c b/board/esd/cpci405/flash.c index 4fcf174..4b12e92 100644 --- a/board/esd/cpci405/flash.c +++ b/board/esd/cpci405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/cpciiser4/flash.c b/board/esd/cpciiser4/flash.c index 224dde4..b210281 100644 --- a/board/esd/cpciiser4/flash.c +++ b/board/esd/cpciiser4/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/dasa_sim/flash.c b/board/esd/dasa_sim/flash.c index 9c71b04..d6a7737 100644 --- a/board/esd/dasa_sim/flash.c +++ b/board/esd/dasa_sim/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/dp405/flash.c b/board/esd/dp405/flash.c index a53122b..895a836 100644 --- a/board/esd/dp405/flash.c +++ b/board/esd/dp405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/du405/du405.c b/board/esd/du405/du405.c index e0faa77..b1362a8 100644 --- a/board/esd/du405/du405.c +++ b/board/esd/du405/du405.c @@ -24,8 +24,8 @@ #include <common.h> #include "du405.h" #include <asm/processor.h> -#include <ppc4xx.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> #include <command.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/esd/du405/flash.c b/board/esd/du405/flash.c index c62c6a9..c30886e 100644 --- a/board/esd/du405/flash.c +++ b/board/esd/du405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/du440/du440.c b/board/esd/du440/du440.c index ad255f9..426321e 100644 --- a/board/esd/du440/du440.c +++ b/board/esd/du440/du440.c @@ -24,7 +24,7 @@ #include <asm/bitops.h> #include <command.h> #include <i2c.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include "du440.h" DECLARE_GLOBAL_DATA_PTR; @@ -265,8 +265,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; - mtdcr(PLB4_ACR, reg); + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); /* * release IO-RST# diff --git a/board/esd/hh405/flash.c b/board/esd/hh405/flash.c index a53122b..895a836 100644 --- a/board/esd/hh405/flash.c +++ b/board/esd/hh405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/hub405/flash.c b/board/esd/hub405/flash.c index a53122b..895a836 100644 --- a/board/esd/hub405/flash.c +++ b/board/esd/hub405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/ocrtc/flash.c b/board/esd/ocrtc/flash.c index eda7c57..c83e594 100644 --- a/board/esd/ocrtc/flash.c +++ b/board/esd/ocrtc/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/pci405/flash.c b/board/esd/pci405/flash.c index 67a7bb5..6ca6e4b 100644 --- a/board/esd/pci405/flash.c +++ b/board/esd/pci405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/pci405/pci405.c b/board/esd/pci405/pci405.c index dd97c7a..4018a7d 100644 --- a/board/esd/pci405/pci405.c +++ b/board/esd/pci405/pci405.c @@ -281,7 +281,6 @@ int misc_init_r (void) #define PCI0_BRDGOPT1 0x4a pci_write_config_word(PCIDEVID_405GP, PCI0_BRDGOPT1, 0x3f20); -#define PLB0_ACR 0x87 /* * Enable fairness and high bus utilization */ diff --git a/board/esd/pci405/writeibm.S b/board/esd/pci405/writeibm.S index 4e319c1..5925bc6 100644 --- a/board/esd/pci405/writeibm.S +++ b/board/esd/pci405/writeibm.S @@ -41,7 +41,7 @@ /* Bank 6 - not used */ /* Bank 7 - FPGA registers */ /*----------------------------------------------------------------------------- */ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/esd/plu405/flash.c b/board/esd/plu405/flash.c index a53122b..895a836 100644 --- a/board/esd/plu405/flash.c +++ b/board/esd/plu405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/pmc405de/pmc405de.c b/board/esd/pmc405de/pmc405de.c index b84e08a..c266ebe 100644 --- a/board/esd/pmc405de/pmc405de.c +++ b/board/esd/pmc405de/pmc405de.c @@ -26,7 +26,7 @@ #include <fdt_support.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/4xx_pci.h> #include <command.h> #include <malloc.h> diff --git a/board/esd/pmc440/pmc440.c b/board/esd/pmc440/pmc440.c index bd43a9a..5236f44 100644 --- a/board/esd/pmc440/pmc440.c +++ b/board/esd/pmc440/pmc440.c @@ -29,7 +29,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/bitops.h> @@ -68,7 +68,7 @@ struct serial_device *default_serial_console(void) */ mfsdr(SDR0_PINSTP, val); if (((val & 0xf0000000) >> 29) != 7) - return &serial1_device; + return &eserial2_device; ulong scratchreg = in_be32((void*)GPIO0_ISR3L); if (!(scratchreg & 0x80)) { @@ -90,9 +90,9 @@ struct serial_device *default_serial_console(void) } if (scratchreg & 0x01) - return &serial1_device; + return &eserial2_device; else - return &serial0_device; + return &eserial1_device; } int board_early_init_f(void) @@ -426,8 +426,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; - mtdcr(PLB4_ACR, reg); + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); #ifdef CONFIG_FPGA pmc440_init_fpga(); diff --git a/board/esd/pmc440/sdram.c b/board/esd/pmc440/sdram.c index c3528bc..34ff402 100644 --- a/board/esd/pmc440/sdram.c +++ b/board/esd/pmc440/sdram.c @@ -35,7 +35,7 @@ #include <asm/processor.h> #include <asm/io.h> #include <asm/mmu.h> -#include <ppc440.h> +#include <asm/ppc440.h> extern int denali_wait_for_dlllock(void); extern void denali_core_search_data_eye(void); diff --git a/board/esd/tasreg/flash.c b/board/esd/tasreg/flash.c index ce905e9..fe120aa 100644 --- a/board/esd/tasreg/flash.c +++ b/board/esd/tasreg/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -/*#include <ppc4xx.h>*/ +/*#include <asm/ppc4xx.h>*/ #include <asm/processor.h> /* diff --git a/board/esd/vme8349/pci.c b/board/esd/vme8349/pci.c index 94fd32a..2802be1 100644 --- a/board/esd/vme8349/pci.c +++ b/board/esd/vme8349/pci.c @@ -124,7 +124,7 @@ pci_init_board(void) udelay(2000); if (monarch == 0) { - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } else { /* * Release PCI RST Output signal diff --git a/board/esd/voh405/flash.c b/board/esd/voh405/flash.c index a53122b..895a836 100644 --- a/board/esd/voh405/flash.c +++ b/board/esd/voh405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/vom405/flash.c b/board/esd/vom405/flash.c index a53122b..895a836 100644 --- a/board/esd/vom405/flash.c +++ b/board/esd/vom405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/esd/wuh405/flash.c b/board/esd/wuh405/flash.c index a53122b..895a836 100644 --- a/board/esd/wuh405/flash.c +++ b/board/esd/wuh405/flash.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> /* diff --git a/board/freescale/common/Makefile b/board/freescale/common/Makefile index f93045f..dca3ac0 100644 --- a/board/freescale/common/Makefile +++ b/board/freescale/common/Makefile @@ -31,7 +31,7 @@ LIB = $(obj)lib$(VENDOR).a COBJS-$(CONFIG_FSL_CADMUS) += cadmus.o COBJS-$(CONFIG_FSL_VIA) += cds_via.o -COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o fsl_logo_bmp.o +COBJS-$(CONFIG_FSL_DIU_FB) += fsl_diu_fb.o COBJS-$(CONFIG_FSL_PIXIS) += pixis.o COBJS-$(CONFIG_FSL_NGPIXIS) += ngpixis.o COBJS-$(CONFIG_PQ_MDS_PIB) += pq-mds-pib.o diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index e740ad8..394b71f 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -208,10 +208,7 @@ static int fsl_diu_disable_panel(struct fb_info *info); static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align); void diu_set_pixel_clock(unsigned int pixclock); -int fsl_diu_init(int xres, - unsigned int pixel_format, - int gamma_fix, - unsigned char *splash_bmp) +int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix) { struct fb_videomode *fsl_diu_mode_db; struct diu_ad *ad = &fsl_diu_fb_ad; @@ -288,8 +285,6 @@ int fsl_diu_init(int xres, var->sync = fsl_diu_mode_db->sync; var->vmode = fsl_diu_mode_db->vmode; info->line_length = var->xres * var->bits_per_pixel / 8; - info->logo_size = 0; - info->logo_height = 0; ad->pix_fmt = pixel_format; ad->addr = cpu_to_le32((unsigned int)info->screen_base); @@ -358,13 +353,6 @@ int fsl_diu_init(int xres, fb_initialized = 1; - if (splash_bmp) { - info->logo_height = fsl_diu_display_bmp(splash_bmp, 0, 0, 0); - info->logo_size = info->logo_height * info->line_length; - debug("logo height %d, logo_size 0x%x\n", - info->logo_height,info->logo_size); - } - /* Enable the DIU */ fsl_diu_enable_panel(info); enable_lcdc(); @@ -375,8 +363,7 @@ int fsl_diu_init(int xres, char *fsl_fb_open(struct fb_info **info) { *info = &fsl_fb_info; - return (char *) ((unsigned int)(*info)->screen_base - + (*info)->logo_size); + return fsl_fb_info.screen_base; } void fsl_diu_close(void) @@ -485,118 +472,3 @@ static int allocate_buf(struct diu_addr *buf, u32 size, u32 bytes_align) buf->offset = 0; return 0; } - -int fsl_diu_display_bmp(unsigned char *bmp, - int xoffset, - int yoffset, - int transpar) -{ - struct fb_info *info = &fsl_fb_info; - unsigned char r, g, b; - unsigned int *fb_t, val; - unsigned char *bitmap; - unsigned int palette[256]; - int width, height, bpp, ncolors, raster, offset, x, y, i, k, cpp; - - if (!bmp) { - printf("Must supply a bitmap address\n"); - return 0; - } - - raster = bmp[10] + (bmp[11] << 8) + (bmp[12] << 16) + (bmp[13] << 24); - width = (bmp[21] << 24) | (bmp[20] << 16) | (bmp[19] << 8) | bmp[18]; - height = (bmp[25] << 24) | (bmp[24] << 16) | (bmp[23] << 8) | bmp[22]; - bpp = (bmp[29] << 8) | (bmp[28]); - ncolors = bmp[46] + (bmp[47] << 8) + (bmp[48] << 16) + (bmp[49] << 24); - bitmap = bmp + raster; - cpp = info->var.bits_per_pixel / 8; - - debug("bmp = 0x%08x\n", (unsigned int)bmp); - debug("bitmap = 0x%08x\n", (unsigned int)bitmap); - debug("width = %d\n", width); - debug("height = %d\n", height); - debug("bpp = %d\n", bpp); - debug("ncolors = %d\n", ncolors); - - debug("xres = %d\n", info->var.xres); - debug("yres = %d\n", info->var.yres); - debug("Screen_base = 0x%x\n", (unsigned int)info->screen_base); - - if (((width+xoffset) > info->var.xres) || - ((height+yoffset) > info->var.yres)) { - printf("bitmap is out of range, image too large or too much offset\n"); - return 0; - } - if (bpp < 24) { - for (i = 0, offset = 54; i < ncolors; i++, offset += 4) - palette[i] = (bmp[offset+2] << 16) - + (bmp[offset+1] << 8) + bmp[offset]; - } - - switch (bpp) { - case 1: - for (y = height - 1; y >= 0; y--) { - fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); - for (x = 0; x < width; x += 8) { - b = *bitmap++; - for (k = 0; k < 8; k++) { - if (b & 0x80) - *fb_t++ = palette[1]; - else - *fb_t++ = palette[0]; - b = b << 1; - } - } - for (i = (width / 2) % 4; i > 0; i--) - bitmap++; - } - break; - case 4: - for (y = height - 1; y >= 0; y--) { - fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); - for (x = 0; x < width; x += 2) { - b = *bitmap++; - r = (b >> 4) & 0x0F; - g = b & 0x0F; - *fb_t++ = palette[r]; - *fb_t++ = palette[g]; - } - for (i = (width / 2) % 4; i > 0; i--) - bitmap++; - } - break; - case 8: - for (y = height - 1; y >= 0; y--) { - fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); - for (x = 0; x < width; x++) { - *fb_t++ = palette[ *bitmap++ ]; - } - for (i = (width / 2) % 4; i > 0; i--) - bitmap++; - } - break; - case 24: - for (y = height - 1; y >= 0; y--) { - fb_t = (unsigned int *) ((unsigned int)info->screen_base + (((y+yoffset) * info->var.xres) + xoffset)*cpp); - for (x = 0; x < width; x++) { - b = *bitmap++; - g = *bitmap++; - r = *bitmap++; - val = (r << 16) + (g << 8) + b; - *fb_t++ = val; - } - for (; (x % 4) != 0; x++) /* 4-byte alignment */ - bitmap++; - } - break; - } - - return height; -} - -void fsl_diu_clear_screen(void) -{ - struct fb_info *info = &fsl_fb_info; - - memset(info->screen_base, 0, info->smem_len); -} diff --git a/board/freescale/common/fsl_diu_fb.h b/board/freescale/common/fsl_diu_fb.h index 6deba32..3a5fc9f 100644 --- a/board/freescale/common/fsl_diu_fb.h +++ b/board/freescale/common/fsl_diu_fb.h @@ -52,18 +52,8 @@ struct fb_info { char *screen_base; unsigned long screen_size; - int logo_height; - unsigned int logo_size; }; extern char *fsl_fb_open(struct fb_info **info); -extern int fsl_diu_init(int xres, - unsigned int pixel_format, - int gamma_fix, - unsigned char *splash_bmp); -extern void fsl_diu_clear_screen(void); -extern int fsl_diu_display_bmp(unsigned char *bmp, - int xoffset, - int yoffset, - int transpar); +int fsl_diu_init(int xres, unsigned int pixel_format, int gamma_fix); diff --git a/board/freescale/common/fsl_logo_bmp.c b/board/freescale/common/fsl_logo_bmp.c deleted file mode 100644 index 956dbee..0000000 --- a/board/freescale/common/fsl_logo_bmp.c +++ /dev/null @@ -1,878 +0,0 @@ -/* - * Copyright 2007 Freescale Semiconductor, Inc. - * York Sun <yorksun@freescale.com> - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/*--------------------------------------------------------------------------- - * FSL_Logo_BMP -- - * - * A 340x128x4bpp BMP logo. - *--------------------------------------------------------------------------- - */ -unsigned int FSL_Logo_BMP[] = { -0x424d765c, -0x00000000,0x00007600,0x00002800,0x00006c01,0x00008000,0x00000100,0x04000000, -0x0000005c,0x0000130b,0x0000130b,0x00001000,0x00000000,0x00000402,0x04000d91, -0xbc000b51,0x67001536,0x9a000f2a,0x4b005050,0x50009090,0x90000c70,0x92002e2f, -0x2e00cfcf,0xcf007c82,0x7c00fbfd,0xfb006f70,0x6f00b0b0,0xb00004bd,0xfa000542, -0xf9000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, 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-0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000,0x00000000, -0x00000000,0x0000babe -}; diff --git a/board/freescale/mpc5121ads/mpc5121ads.c b/board/freescale/mpc5121ads/mpc5121ads.c index 2e13ea8..a84644d 100644 --- a/board/freescale/mpc5121ads/mpc5121ads.c +++ b/board/freescale/mpc5121ads/mpc5121ads.c @@ -260,11 +260,6 @@ int misc_init_r(void) i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n", tmp_val); -#ifdef CONFIG_FSL_DIU_FB -# if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE)) - mpc5121_diu_init(); -# endif -#endif return 0; } diff --git a/board/freescale/mpc8308rdb/mpc8308rdb.c b/board/freescale/mpc8308rdb/mpc8308rdb.c index a864189..5c54357 100644 --- a/board/freescale/mpc8308rdb/mpc8308rdb.c +++ b/board/freescale/mpc8308rdb/mpc8308rdb.c @@ -36,16 +36,6 @@ DECLARE_GLOBAL_DATA_PTR; -int board_early_init_f(void) -{ - immap_t *im = (immap_t *)CONFIG_SYS_IMMR; - - if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) - gd->flags |= GD_FLG_SILENT; - - return 0; -} - static u8 read_board_info(void) { u8 val8; @@ -96,16 +86,12 @@ void pci_init_board(void) { immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; sysconf83xx_t *sysconf = &immr->sysconf; - clk83xx_t *clk = (clk83xx_t *)&immr->clk; law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *pcie_reg[] = { pcie_regions_0 }; fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); - clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM , - SCCR_PCIEXP1CM_1); - /* Deassert the resets in the control register */ out_be32(&sysconf->pecr1, 0xE0008000); udelay(2000); @@ -114,7 +100,7 @@ void pci_init_board(void) out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); - mpc83xx_pcie_init(1, pcie_reg, 0); + mpc83xx_pcie_init(1, pcie_reg); } /* * Miscellaneous late-boot configurations @@ -146,12 +132,14 @@ int board_eth_init(bd_t *bis) int rv, num_if = 0; /* Initialize TSECs first */ - if ((rv = cpu_eth_init(bis)) >= 0) + rv = cpu_eth_init(bis); + if (rv >= 0) num_if += rv; else printf("ERROR: failed to initialize TSECs.\n"); - if ((rv = pci_eth_init(bis)) >= 0) + rv = pci_eth_init(bis); + if (rv >= 0) num_if += rv; else printf("ERROR: failed to initialize PCI Ethernet.\n"); diff --git a/board/freescale/mpc8308rdb/sdram.c b/board/freescale/mpc8308rdb/sdram.c index 939c1b8..1a6b9c7 100644 --- a/board/freescale/mpc8308rdb/sdram.c +++ b/board/freescale/mpc8308rdb/sdram.c @@ -38,20 +38,6 @@ DECLARE_GLOBAL_DATA_PTR; -static void resume_from_sleep(void) -{ - u32 magic = *(u32 *)0; - - typedef void (*func_t)(void); - func_t resume = *(func_t *)4; - - if (magic == 0xf5153ae5) - resume(); - - gd->flags &= ~GD_FLG_SILENT; - puts("\nResume from sleep failed: bad magic word\n"); -} - /* Fixed sdram init -- doesn't use serial presence detect. * * This is useful for faster booting in configs where the RAM is unlikely @@ -68,12 +54,6 @@ static long fixed_sdram(void) out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); - /* - * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg], - * or the DDR2 controller may fail to initialize correctly. - */ - udelay(50000); - out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); @@ -86,13 +66,7 @@ static long fixed_sdram(void) out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); - if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) { - out_be32(&im->ddr.sdram_cfg, - CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI); - } else { - out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); - } - + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); @@ -118,9 +92,6 @@ phys_size_t initdram(int board_type) /* DDR SDRAM */ msize = fixed_sdram(); - if (in_be32(&im->pmc.pmccr1) & PMCCR1_POWER_OFF) - resume_from_sleep(); - /* return total bus SDRAM size(bytes) -- DDR */ return msize; } diff --git a/board/freescale/mpc8313erdb/mpc8313erdb.c b/board/freescale/mpc8313erdb/mpc8313erdb.c index e5f62ae..08f873d 100644 --- a/board/freescale/mpc8313erdb/mpc8313erdb.c +++ b/board/freescale/mpc8313erdb/mpc8313erdb.c @@ -80,7 +80,6 @@ void pci_init_board(void) volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; - int warmboot; /* Enable all 3 PCI_CLK_OUTPUTs. */ clk->occr |= 0xe0000000; @@ -94,12 +93,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; -#ifndef CONFIG_SYS_8313ERDB_BROKEN_PMC - warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; -#endif - - mpc83xx_pci_init(1, reg, warmboot); + mpc83xx_pci_init(1, reg); } /* diff --git a/board/freescale/mpc8315erdb/mpc8315erdb.c b/board/freescale/mpc8315erdb/mpc8315erdb.c index d5e71dc..5dc558a 100644 --- a/board/freescale/mpc8315erdb/mpc8315erdb.c +++ b/board/freescale/mpc8315erdb/mpc8315erdb.c @@ -140,7 +140,6 @@ void pci_init_board(void) volatile law83xx_t *pcie_law = sysconf->pcielaw; struct pci_region *reg[] = { pci_regions }; struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, }; - int warmboot; /* Enable all 3 PCI_CLK_OUTPUTs. */ clk->occr |= 0xe0000000; @@ -154,10 +153,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - warmboot |= immr->pmc.pmccr1 & PMCCR1_POWER_OFF; - - mpc83xx_pci_init(1, reg, warmboot); + mpc83xx_pci_init(1, reg); /* Configure the clock for PCIE controller */ clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM, @@ -175,7 +171,7 @@ void pci_init_board(void) out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - mpc83xx_pcie_init(2, pcie_reg, warmboot); + mpc83xx_pcie_init(2, pcie_reg); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c index 8680a19..7a0ff18 100644 --- a/board/freescale/mpc8323erdb/mpc8323erdb.c +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c @@ -173,7 +173,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/mpc832xemds/pci.c b/board/freescale/mpc832xemds/pci.c index e1dd757..5c7901d 100644 --- a/board/freescale/mpc832xemds/pci.c +++ b/board/freescale/mpc832xemds/pci.c @@ -86,7 +86,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); /* * Configure PCI Inbound Translation Windows @@ -147,9 +147,9 @@ void pci_init_board(void) udelay(2000); #ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); #else - mpc83xx_pci_init(2, reg, 0); + mpc83xx_pci_init(2, reg); #endif } #endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc8349emds/pci.c b/board/freescale/mpc8349emds/pci.c index 9293f70..832477f 100644 --- a/board/freescale/mpc8349emds/pci.c +++ b/board/freescale/mpc8349emds/pci.c @@ -161,9 +161,9 @@ void pci_init_board(void) udelay(2000); #ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); #else - mpc83xx_pci_init(2, reg, 0); + mpc83xx_pci_init(2, reg); #endif } @@ -182,7 +182,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); /* Configure PCI Inbound Translation Windows (3 1MB windows) */ pci_ctrl->pitar0 = 0x0; diff --git a/board/freescale/mpc8349itx/pci.c b/board/freescale/mpc8349itx/pci.c index 38baff3..7d30d9b 100644 --- a/board/freescale/mpc8349itx/pci.c +++ b/board/freescale/mpc8349itx/pci.c @@ -114,8 +114,8 @@ void pci_init_board(void) udelay(2000); #ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); #else - mpc83xx_pci_init(2, reg, 0); + mpc83xx_pci_init(2, reg); #endif } diff --git a/board/freescale/mpc8360emds/pci.c b/board/freescale/mpc8360emds/pci.c index 04a802b..c3a8663 100644 --- a/board/freescale/mpc8360emds/pci.c +++ b/board/freescale/mpc8360emds/pci.c @@ -84,7 +84,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); /* * Configure PCI Inbound Translation Windows @@ -145,9 +145,9 @@ void pci_init_board(void) udelay(2000); #ifndef CONFIG_MPC83XX_PCI2 - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); #else - mpc83xx_pci_init(2, reg, 0); + mpc83xx_pci_init(2, reg); #endif } #endif /* CONFIG_PCISLAVE */ diff --git a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c index 3771878..a6530d1 100644 --- a/board/freescale/mpc8360erdk/mpc8360erdk.c +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c @@ -344,7 +344,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } #if defined(CONFIG_OF_BOARD_SETUP) diff --git a/board/freescale/mpc837xemds/pci.c b/board/freescale/mpc837xemds/pci.c index 82f34f8..77c5bda 100644 --- a/board/freescale/mpc837xemds/pci.c +++ b/board/freescale/mpc837xemds/pci.c @@ -108,7 +108,7 @@ void pci_init_board(void) udelay(2000); - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); skip_pci: /* There is no PEX in MPC8379 parts. */ if (PARTID_NO_E(spridr) == SPR_8379) diff --git a/board/freescale/mpc837xerdb/pci.c b/board/freescale/mpc837xerdb/pci.c index 97ad227..3512bd4 100644 --- a/board/freescale/mpc837xerdb/pci.c +++ b/board/freescale/mpc837xerdb/pci.c @@ -88,7 +88,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); /* There is no PEX in MPC8379 parts. */ if (PARTID_NO_E(spridr) == SPR_8379) @@ -110,5 +110,5 @@ void pci_init_board(void) out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR); out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB); - mpc83xx_pcie_init(2, pcie_reg, 0); + mpc83xx_pcie_init(2, pcie_reg); } diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd.c b/board/freescale/mpc8610hpcd/mpc8610hpcd.c index 6578f58..f67f3e3 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd.c @@ -36,7 +36,7 @@ void sdram_init(void); phys_size_t fixed_sdram(void); -void mpc8610hpcd_diu_init(void); +int mpc8610hpcd_diu_init(void); /* called before any console output */ @@ -84,10 +84,6 @@ int misc_init_r(void) i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val)); debug("DVI Encoder Read: 0x%02lx\n",tmp_val); -#ifdef CONFIG_FSL_DIU_FB - mpc8610hpcd_diu_init(); -#endif - return 0; } diff --git a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c index 781a7c8..960c8ed 100644 --- a/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c +++ b/board/freescale/mpc8610hpcd/mpc8610hpcd_diu.c @@ -36,8 +36,6 @@ #include <video_fb.h> #endif -extern unsigned int FSL_Logo_BMP[]; - static int xres, yres; void diu_set_pixel_clock(unsigned int pixclock) @@ -61,7 +59,7 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *guts_clkdvdr); } -void mpc8610hpcd_diu_init(void) +int mpc8610hpcd_diu_init(void) { char *monitor_port; int gamma_fix; @@ -106,79 +104,45 @@ void mpc8610hpcd_diu_init(void) out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x08); } - fsl_diu_init(xres, pixel_format, gamma_fix, - (unsigned char *)FSL_Logo_BMP); + return fsl_diu_init(xres, pixel_format, gamma_fix); } -int mpc8610diu_init_show_bmp(cmd_tbl_t *cmdtp, - int flag, int argc, char * const argv[]) -{ - unsigned int addr; - - if (argc < 2) - return cmd_usage(cmdtp); - - if (!strncmp(argv[1],"init",4)) { -#if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) - fsl_diu_clear_screen(); - drv_video_init(); -#else - mpc8610hpcd_diu_init(); -#endif - } else { - addr = simple_strtoul(argv[1], NULL, 16); - fsl_diu_clear_screen(); - fsl_diu_display_bmp((unsigned char *)addr, 0, 0, 0); - } - - return 0; -} - -U_BOOT_CMD( - diufb, CONFIG_SYS_MAXARGS, 1, mpc8610diu_init_show_bmp, - "Init or Display BMP file", - "init\n - initialize DIU\n" - "addr\n - display bmp at address 'addr'" -); - - #if defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) /* * The Graphic Device */ -GraphicDevice ctfb; +static GraphicDevice ctfb; + void *video_hw_init(void) { - GraphicDevice *pGD = (GraphicDevice *) &ctfb; struct fb_info *info; - mpc8610hpcd_diu_init(); + if (mpc8610hpcd_diu_init() < 0) + return NULL; /* fill in Graphic device struct */ - sprintf(pGD->modeIdent, - "%dx%dx%d %ldkHz %ldHz", - xres, yres, 32, 64, 60); + sprintf(ctfb.modeIdent, "%ix%ix%i %ikHz %iHz", xres, yres, 32, 64, 60); - pGD->frameAdrs = (unsigned int)fsl_fb_open(&info); - pGD->winSizeX = xres; - pGD->winSizeY = yres - info->logo_height; - pGD->plnSizeX = pGD->winSizeX; - pGD->plnSizeY = pGD->winSizeY; + ctfb.frameAdrs = (unsigned int)fsl_fb_open(&info); + ctfb.winSizeX = xres; + ctfb.winSizeY = yres; + ctfb.plnSizeX = ctfb.winSizeX; + ctfb.plnSizeY = ctfb.winSizeY; - pGD->gdfBytesPP = 4; - pGD->gdfIndex = GDF_32BIT_X888RGB; + ctfb.gdfBytesPP = 4; + ctfb.gdfIndex = GDF_32BIT_X888RGB; - pGD->isaBase = 0; - pGD->pciBase = 0; - pGD->memSize = info->screen_size - info->logo_size; + ctfb.isaBase = 0; + ctfb.pciBase = 0; + ctfb.memSize = info->screen_size; /* Cursor Start Address */ - pGD->dprBase = 0; - pGD->vprBase = 0; - pGD->cprBase = 0; + ctfb.dprBase = 0; + ctfb.vprBase = 0; + ctfb.cprBase = 0; - return (void *)pGD; + return &ctfb; } #endif /* defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE) */ diff --git a/board/gdsys/dlvision/dlvision.c b/board/gdsys/dlvision/dlvision.c index ff5f183..3499bdc 100644 --- a/board/gdsys/dlvision/dlvision.c +++ b/board/gdsys/dlvision/dlvision.c @@ -25,7 +25,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> enum { HWTYPE_DLVISION_CPU = 0, diff --git a/board/gdsys/gdppc440etx/gdppc440etx.c b/board/gdsys/gdppc440etx/gdppc440etx.c index ecbc3c3..328eb95 100644 --- a/board/gdsys/gdppc440etx/gdppc440etx.c +++ b/board/gdsys/gdppc440etx/gdppc440etx.c @@ -26,7 +26,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/4xx_pci.h> diff --git a/board/gdsys/intip/intip.c b/board/gdsys/intip/intip.c index 23a10c4..aa85ea4 100644 --- a/board/gdsys/intip/intip.c +++ b/board/gdsys/intip/intip.c @@ -23,7 +23,7 @@ */ #include <common.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <libfdt.h> #include <fdt_support.h> #include <i2c.h> @@ -31,7 +31,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/4xx_pcie.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; diff --git a/board/jse/flash.c b/board/jse/flash.c index 92acdb1..5735f19 100644 --- a/board/jse/flash.c +++ b/board/jse/flash.c @@ -29,7 +29,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #if CONFIG_SYS_MAX_FLASH_BANKS != 1 diff --git a/board/jse/init.S b/board/jse/init.S index 92f43f4..bccc7e0 100644 --- a/board/jse/init.S +++ b/board/jse/init.S @@ -44,7 +44,7 @@ /* Bank 6 - not used */ /* Bank 7 - not used */ /*------------------------------------------------------------------------- */ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/jse/jse.c b/board/jse/jse.c index fb39c84..f5c52c9 100644 --- a/board/jse/jse.c +++ b/board/jse/jse.c @@ -19,7 +19,7 @@ */ # include <common.h> -# include <ppc4xx.h> +# include <asm/ppc4xx.h> # include <asm/processor.h> # include <asm/io.h> # include "jse_priv.h" diff --git a/board/jse/sdram.c b/board/jse/sdram.c index 02eb6f2..8ce8798 100644 --- a/board/jse/sdram.c +++ b/board/jse/sdram.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> # define SDRAM_LEN 0x08000000 diff --git a/board/karo/tx25/config.mk b/board/karo/tx25/config.mk index 732a14a..51ca1ab 100644 --- a/board/karo/tx25/config.mk +++ b/board/karo/tx25/config.mk @@ -1,5 +1,5 @@ ifdef CONFIG_NAND_SPL -TEXT_BASE = 0x81ec0000 +TEXT_BASE = 0x810c0000 else -TEXT_BASE = 0x81f00000 +TEXT_BASE = 0x81fc0000 endif diff --git a/board/karo/tx25/tx25.c b/board/karo/tx25/tx25.c index 2608698..dc57d5c 100644 --- a/board/karo/tx25/tx25.c +++ b/board/karo/tx25/tx25.c @@ -159,7 +159,14 @@ int board_late_init(void) int dram_init (void) { + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM_1, + PHYS_SDRAM_1_SIZE); + return 0; +} +void dram_init_banksize(void) +{ gd->bd->bi_dram[0].start = PHYS_SDRAM_1; gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, PHYS_SDRAM_1_SIZE); @@ -167,9 +174,9 @@ int dram_init (void) gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); -#endif +#else - return 0; +#endif } int checkboard(void) diff --git a/board/keymile/km_arm/km_arm.c b/board/keymile/km_arm/km_arm.c index d7cbd7a..7c0b858 100644 --- a/board/keymile/km_arm/km_arm.c +++ b/board/keymile/km_arm/km_arm.c @@ -225,6 +225,7 @@ U_BOOT_CMD( ); #endif +#if defined(CONFIG_SYS_ARM_WITHOUT_RELOC) int dram_init(void) { int i; @@ -234,9 +235,32 @@ int dram_init(void) gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), kw_sdram_bs(i)); } + + return 0; +} +#else +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + /* Fix this */ + gd->ram_size = get_ram_size((volatile void *)kw_sdram_bar(0), + kw_sdram_bs(0)); return 0; } +void dram_init_banksize(void) +{ + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = kw_sdram_bar(i); + gd->bd->bi_dram[i].size = kw_sdram_bs(i); + gd->bd->bi_dram[i].size = get_ram_size((long *)kw_sdram_bar(i), + kw_sdram_bs(i)); + } +} +#endif + /* Configure and enable MV88E1118 PHY */ void reset_phy(void) { diff --git a/board/korat/korat.c b/board/korat/korat.c index e5ec694..4f0513a 100644 --- a/board/korat/korat.c +++ b/board/korat/korat.c @@ -29,9 +29,9 @@ #include <fdt_support.h> #include <i2c.h> #include <libfdt.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/bitops.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/io.h> #include <asm/ppc4xx-uic.h> #include <asm/processor.h> @@ -553,8 +553,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; - mtdcr(PLB4_ACR, reg); + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); set_serial_number(); set_mac_addresses(); diff --git a/board/logicpd/imx27lite/config.mk b/board/logicpd/imx27lite/config.mk index a2e7768..2f9c4e6 100644 --- a/board/logicpd/imx27lite/config.mk +++ b/board/logicpd/imx27lite/config.mk @@ -1 +1 @@ -TEXT_BASE = 0xA7F00000 +TEXT_BASE = 0xc0000000 diff --git a/board/logicpd/imx27lite/imx27lite.c b/board/logicpd/imx27lite/imx27lite.c index 4427415..6eb5cc2 100644 --- a/board/logicpd/imx27lite/imx27lite.c +++ b/board/logicpd/imx27lite/imx27lite.c @@ -66,19 +66,22 @@ int board_init (void) int dram_init (void) { + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} -#if CONFIG_NR_DRAM_BANKS > 0 - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = get_ram_size((volatile void *)PHYS_SDRAM_1, +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = get_ram_size((volatile void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); -#endif #if CONFIG_NR_DRAM_BANKS > 1 gd->bd->bi_dram[1].start = PHYS_SDRAM_2; gd->bd->bi_dram[1].size = get_ram_size((volatile void *)PHYS_SDRAM_2, PHYS_SDRAM_2_SIZE); #endif - - return 0; } int checkboard(void) diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index ec113e7..9622b70 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -20,9 +20,9 @@ #include <common.h> #include <command.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/processor.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -38,8 +38,8 @@ int board_early_init_f(void) u32 reg; /* PLB Write pipelining disabled. Denali Core workaround */ - mtdcr(PLB0_ACR, 0xDE000000); - mtdcr(PLB1_ACR, 0xDE000000); + mtdcr(PLB4A0_ACR, 0xDE000000); + mtdcr(PLB4A1_ACR, 0xDE000000); /*-------------------------------------------------------------------- * Setup the interrupt controller polarities, triggers, etc. @@ -249,8 +249,8 @@ int misc_init_r(void) * This fix will make the MAL burst disabling patch for the Linux * EMAC driver obsolete. */ - reg = mfdcr(PLB4_ACR) & ~PLB4_ACR_WRP; - mtdcr(PLB4_ACR, reg); + reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK; + mtdcr(PLB4A0_ACR, reg); /* * Init matrix keyboard diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index a482387..f90efeb 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -35,7 +35,7 @@ #include <asm/mmu.h> #include <asm/io.h> #include <asm/cache.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <watchdog.h> /* diff --git a/board/matrix_vision/mvblm7/pci.c b/board/matrix_vision/mvblm7/pci.c index 1cc524b..921e80b 100644 --- a/board/matrix_vision/mvblm7/pci.c +++ b/board/matrix_vision/mvblm7/pci.c @@ -60,7 +60,6 @@ static struct pci_region pci_regions[] = { void pci_init_board(void) { int i; - int warmboot; volatile immap_t *immr; volatile pcictrl83xx_t *pci_ctrl; volatile gpio83xx_t *gpio; @@ -102,7 +101,5 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - - mpc83xx_pci_init(1, reg, warmboot); + mpc83xx_pci_init(1, reg); } diff --git a/board/mbx8xx/pcmcia.c b/board/mbx8xx/pcmcia.c index 69368d8..e672d8c 100644 --- a/board/mbx8xx/pcmcia.c +++ b/board/mbx8xx/pcmcia.c @@ -117,11 +117,7 @@ int pcmcia_hardware_enable (int slot) debug ("[%d] %s: PIPR(%p)=0x%x\n", __LINE__,__FUNCTION__, &(pcmp->pcmc_pipr),pcmp->pcmc_pipr); -#ifndef CONFIG_HMI10 - if (pcmp->pcmc_pipr & (0x18000000 >> (slot << 4))) { -#else if (pcmp->pcmc_pipr & (0x10000000 >> (slot << 4))) { -#endif /* CONFIG_HMI10 */ printf (" No Card found\n"); return (1); } diff --git a/board/ml2/init.S b/board/ml2/init.S index 9064d3b..91d053c 100644 --- a/board/ml2/init.S +++ b/board/ml2/init.S @@ -16,7 +16,7 @@ * */ -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> diff --git a/board/mosaixtech/icon/icon.c b/board/mosaixtech/icon/icon.c index ecea1ee..e09dbc3 100644 --- a/board/mosaixtech/icon/icon.c +++ b/board/mosaixtech/icon/icon.c @@ -23,14 +23,14 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <i2c.h> #include <libfdt.h> #include <fdt_support.h> #include <netdev.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/4xx_pcie.h> #include <asm/errno.h> #include <asm/mmu.h> diff --git a/board/mosaixtech/icon/init.S b/board/mosaixtech/icon/init.S index 70ed6ce..a0168b5 100644 --- a/board/mosaixtech/icon/init.S +++ b/board/mosaixtech/icon/init.S @@ -24,6 +24,7 @@ #include <ppc_asm.tmpl> #include <config.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> /* * TLB TABLE diff --git a/board/mpc8308_p1m/Makefile b/board/mpc8308_p1m/Makefile new file mode 100644 index 0000000..e9bfa2b --- /dev/null +++ b/board/mpc8308_p1m/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2006 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# (C) Copyright 2010 +# Ilya Yanok, Emcraft Systems, yanok@emcraft.com +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o sdram.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak $(obj).depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mpc8308_p1m/config.mk b/board/mpc8308_p1m/config.mk new file mode 100644 index 0000000..183d3e8 --- /dev/null +++ b/board/mpc8308_p1m/config.mk @@ -0,0 +1,3 @@ +ifndef TEXT_BASE +TEXT_BASE = 0xFC000000 +endif diff --git a/board/mpc8308_p1m/mpc8308_p1m.c b/board/mpc8308_p1m/mpc8308_p1m.c new file mode 100644 index 0000000..d92833b --- /dev/null +++ b/board/mpc8308_p1m/mpc8308_p1m.c @@ -0,0 +1,106 @@ +/* + * Copyright (C) 2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <i2c.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <pci.h> +#include <mpc83xx.h> +#include <netdev.h> +#include <asm/io.h> +#include <asm/fsl_serdes.h> +#include <asm/fsl_mpc83xx_serdes.h> + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + printf("Board: MPC8308 P1M\n"); + + return 0; +} + +static struct pci_region pcie_regions_0[] = { + { + .bus_start = CONFIG_SYS_PCIE1_MEM_BASE, + .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS, + .size = CONFIG_SYS_PCIE1_MEM_SIZE, + .flags = PCI_REGION_MEM, + }, + { + .bus_start = CONFIG_SYS_PCIE1_IO_BASE, + .phys_start = CONFIG_SYS_PCIE1_IO_PHYS, + .size = CONFIG_SYS_PCIE1_IO_SIZE, + .flags = PCI_REGION_IO, + }, +}; + +void pci_init_board(void) +{ + immap_t *immr = (immap_t *)CONFIG_SYS_IMMR; + sysconf83xx_t *sysconf = &immr->sysconf; + law83xx_t *pcie_law = sysconf->pcielaw; + struct pci_region *pcie_reg[] = { pcie_regions_0 }; + + fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX, + FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V); + + /* Deassert the resets in the control register */ + out_be32(&sysconf->pecr1, 0xE0008000); + udelay(2000); + + /* Configure PCI Express Local Access Windows */ + out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR); + out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB); + + mpc83xx_pcie_init(1, pcie_reg); +} + +#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup(blob, bd); + fdt_fixup_dr_usb(blob, bd); +} +#endif + +int board_eth_init(bd_t *bis) +{ + int rv, num_if = 0; + + /* Initialize TSECs first */ + rv = cpu_eth_init(bis); + if (rv >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize TSECs.\n"); + + rv = pci_eth_init(bis); + if (rv >= 0) + num_if += rv; + else + printf("ERROR: failed to initialize PCI Ethernet.\n"); + + return num_if; +} diff --git a/board/mpc8308_p1m/sdram.c b/board/mpc8308_p1m/sdram.c new file mode 100644 index 0000000..a6e44e6 --- /dev/null +++ b/board/mpc8308_p1m/sdram.c @@ -0,0 +1,93 @@ +/* + * Copyright (C) 2007 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * This files is mostly identical to the original from + * board/freescale/mpc8308rdb/sdram.c + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS for A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc83xx.h> + +#include <asm/bitops.h> +#include <asm/io.h> + +#include <asm/processor.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* Fixed sdram init -- doesn't use serial presence detect. + * + * This is useful for faster booting in configs where the RAM is unlikely + * to be changed, or for things like NAND booting where space is tight. + */ +static long fixed_sdram(void) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024; + u32 msize_log2 = __ilog2(msize); + + out_be32(&im->sysconf.ddrlaw[0].bar, + CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000); + out_be32(&im->sysconf.ddrlaw[0].ar, LBLAWAR_EN | (msize_log2 - 1)); + out_be32(&im->sysconf.ddrcdr, CONFIG_SYS_DDRCDR_VALUE); + + out_be32(&im->ddr.csbnds[0].csbnds, (msize - 1) >> 24); + out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG); + + /* Currently we use only one CS, so disable the other bank. */ + out_be32(&im->ddr.cs_config[1], 0); + + out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL); + out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3); + out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1); + out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2); + out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0); + + out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG); + out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2); + out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE); + out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2); + + out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL); + sync(); + + /* enable DDR controller */ + setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN); + sync(); + + return get_ram_size(CONFIG_SYS_DDR_SDRAM_BASE, msize); +} + +phys_size_t initdram(int board_type) +{ + immap_t *im = (immap_t *)CONFIG_SYS_IMMR; + u32 msize; + + if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im) + return -1; + + /* DDR SDRAM */ + msize = fixed_sdram(); + + /* return total bus SDRAM size(bytes) -- DDR */ + return msize; +} diff --git a/board/mpl/common/flash.c b/board/mpl/common/flash.c index 682f0e7..61f031a 100644 --- a/board/mpl/common/flash.c +++ b/board/mpl/common/flash.c @@ -38,7 +38,7 @@ #include <common.h> #if !defined(CONFIG_PATI) -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include "common_util.h" #if defined(CONFIG_MIP405) diff --git a/board/mpl/common/memtst.c b/board/mpl/common/memtst.c index 68973f9..9c08065 100644 --- a/board/mpl/common/memtst.c +++ b/board/mpl/common/memtst.c @@ -48,7 +48,7 @@ int testdram (void) #include <common.h> #include <asm/processor.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx-i2c.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/mpl/mip405/init.S b/board/mpl/mip405/init.S index f3d94c3..39a1d68 100644 --- a/board/mpl/mip405/init.S +++ b/board/mpl/mip405/init.S @@ -39,8 +39,6 @@ * Bank 6 - not used * Bank 7 - PLD Register *-----------------------------------------------------------------------------*/ -#include <ppc4xx.h> - #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/MIP405.h> @@ -49,6 +47,7 @@ #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> #include "mip405.h" diff --git a/board/mpl/mip405/mip405.c b/board/mpl/mip405/mip405.c index 7400ca6..e93d994 100644 --- a/board/mpl/mip405/mip405.c +++ b/board/mpl/mip405/mip405.c @@ -65,7 +65,8 @@ #include <common.h> #include "mip405.h" #include <asm/processor.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> #include <miiphy.h> #include "../common/common_util.h" #include <stdio_dev.h> diff --git a/board/mpl/pip405/init.S b/board/mpl/pip405/init.S index 18e8b09..b77517f 100644 --- a/board/mpl/pip405/init.S +++ b/board/mpl/pip405/init.S @@ -39,8 +39,6 @@ * Bank 6 - used to switch on the 12V for the Multipurpose socket * Bank 7 - Config Register *-----------------------------------------------------------------------------*/ -#include <ppc4xx.h> - #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ #include <configs/PIP405.h> @@ -49,6 +47,7 @@ #include <asm/cache.h> #include <asm/mmu.h> +#include <asm/ppc4xx.h> #include "pip405.h" .globl ext_bus_cntlr_init diff --git a/board/netstal/common/fixed_sdram.c b/board/netstal/common/fixed_sdram.c index 2f21fbb..51b34b2 100644 --- a/board/netstal/common/fixed_sdram.c +++ b/board/netstal/common/fixed_sdram.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include "nm.h" diff --git a/board/netstal/hcu4/hcu4.c b/board/netstal/hcu4/hcu4.c index 6fd6138..aaf3616 100644 --- a/board/netstal/hcu4/hcu4.c +++ b/board/netstal/hcu4/hcu4.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/u-boot.h> diff --git a/board/netstal/hcu5/hcu5.c b/board/netstal/hcu5/hcu5.c index 5eb8efc..f94d05b 100644 --- a/board/netstal/hcu5/hcu5.c +++ b/board/netstal/hcu5/hcu5.c @@ -20,7 +20,7 @@ #include <common.h> #include <asm/processor.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <asm/io.h> #include <asm/4xx_pci.h> @@ -327,7 +327,7 @@ int board_with_pci(void) u32 reg; mfsdr(SDR0_PCI0, reg); - return (reg & SDR0_XCR_PAE_MASK); + return (reg & SDR0_PCI0_PAE_MASK); } /* @@ -352,28 +352,28 @@ int pci_pre_init(struct pci_controller *hose) * Set priority for all PLB3 devices to 0. * Set PLB3 arbiter to fair mode. */ - mfsdr(SD0_AMP1, addr); - mtsdr(SD0_AMP1, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB3_ACR); - mtdcr(PLB3_ACR, addr | 0x80000000); /* Sequoia */ + mfsdr(SDR0_AMP1, addr); + mtsdr(SDR0_AMP1, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB3A0_ACR); + mtdcr(PLB3A0_ACR, addr | 0x80000000); /* Sequoia */ /* * Set priority for all PLB4 devices to 0. */ - mfsdr(SD0_AMP0, addr); - mtsdr(SD0_AMP0, (addr & 0x000000FF) | 0x0000FF00); - addr = mfdcr(PLB4_ACR) | 0xa0000000; /* Was 0x8---- */ - mtdcr(PLB4_ACR, addr); /* Sequoia */ + mfsdr(SDR0_AMP0, addr); + mtsdr(SDR0_AMP0, (addr & 0x000000FF) | 0x0000FF00); + addr = mfdcr(PLB4A0_ACR) | 0xa0000000; /* Was 0x8---- */ + mtdcr(PLB4A0_ACR, addr); /* Sequoia */ /* * As of errata version 0.4, CHIP_8: Incorrect Write to DDR SDRAM. * Workaround: Disable write pipelining to DDR SDRAM by setting - * PLB0_ACR[WRP] = 0. + * PLB4A0_ACR[WRP] = 0. */ - mtdcr(PLB0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB4A0_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ /* Segment1 */ - mtdcr(PLB1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ + mtdcr(PLB4A1_ACR, 0); /* PATCH HAB: WRITE PIPELINING OFF */ return board_with_pci(); } diff --git a/board/netstal/hcu5/sdram.c b/board/netstal/hcu5/sdram.c index 0546cd7..e5ac46b 100644 --- a/board/netstal/hcu5/sdram.c +++ b/board/netstal/hcu5/sdram.c @@ -35,7 +35,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/cache.h> -#include <ppc440.h> +#include <asm/ppc440.h> void hcu_led_set(u32 value); void dcbz_area(u32 start_address, u32 num_bytes); diff --git a/board/netstal/mcu25/mcu25.c b/board/netstal/mcu25/mcu25.c index ed28e20..36fb388 100644 --- a/board/netstal/mcu25/mcu25.c +++ b/board/netstal/mcu25/mcu25.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> #include <asm/u-boot.h> diff --git a/board/pcs440ep/pcs440ep.c b/board/pcs440ep/pcs440ep.c index a61e945..70d8fe2 100644 --- a/board/pcs440ep/pcs440ep.c +++ b/board/pcs440ep/pcs440ep.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <malloc.h> #include <command.h> #include <crc.h> diff --git a/board/prodrive/alpr/alpr.c b/board/prodrive/alpr/alpr.c index 060e7eb..1784982 100644 --- a/board/prodrive/alpr/alpr.c +++ b/board/prodrive/alpr/alpr.c @@ -26,7 +26,7 @@ #include <libfdt.h> #include <fdt_support.h> #include <spd_sdram.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-emac.h> #include <miiphy.h> #include <asm/processor.h> #include <asm/4xx_pci.h> diff --git a/board/prodrive/alpr/fpga.c b/board/prodrive/alpr/fpga.c index f3bc1fa..93f2449 100644 --- a/board/prodrive/alpr/fpga.c +++ b/board/prodrive/alpr/fpga.c @@ -31,7 +31,7 @@ #include <ACEX1K.h> #include <command.h> #include <asm/processor.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include "fpga.h" DECLARE_GLOBAL_DATA_PTR; diff --git a/board/prodrive/alpr/init.S b/board/prodrive/alpr/init.S index 9f9812a..119bc53 100644 --- a/board/prodrive/alpr/init.S +++ b/board/prodrive/alpr/init.S @@ -24,6 +24,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/prodrive/p3p440/init.S b/board/prodrive/p3p440/init.S index 66acaf2..6230695 100644 --- a/board/prodrive/p3p440/init.S +++ b/board/prodrive/p3p440/init.S @@ -26,6 +26,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/quad100hd/nand.c b/board/quad100hd/nand.c index 35525bc..a222099 100644 --- a/board/quad100hd/nand.c +++ b/board/quad100hd/nand.c @@ -24,7 +24,7 @@ #include <common.h> #include <config.h> #if defined(CONFIG_CMD_NAND) -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/io.h> #include <nand.h> diff --git a/board/quad100hd/quad100hd.c b/board/quad100hd/quad100hd.c index f878c49..2f72d2b 100644 --- a/board/quad100hd/quad100hd.c +++ b/board/quad100hd/quad100hd.c @@ -33,7 +33,7 @@ #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/board/sandburst/common/flash.c b/board/sandburst/common/flash.c index dd712e3..c65cb96 100644 --- a/board/sandburst/common/flash.c +++ b/board/sandburst/common/flash.c @@ -29,7 +29,7 @@ * Sandburst Corporation */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> diff --git a/board/sandburst/common/ppc440gx_i2c.c b/board/sandburst/common/ppc440gx_i2c.c index 68acdd8..85b63fc 100644 --- a/board/sandburst/common/ppc440gx_i2c.c +++ b/board/sandburst/common/ppc440gx_i2c.c @@ -26,8 +26,8 @@ * Sandburst Corporation. */ #include <common.h> -#include <ppc4xx.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> #include <i2c.h> #include <command.h> #include "ppc440gx_i2c.h" diff --git a/board/sandburst/common/ppc440gx_i2c.h b/board/sandburst/common/ppc440gx_i2c.h index 0676c0e..7496db4 100644 --- a/board/sandburst/common/ppc440gx_i2c.h +++ b/board/sandburst/common/ppc440gx_i2c.h @@ -26,8 +26,8 @@ * Sandburst Corporation */ #include <common.h> -#include <ppc4xx.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> #include <i2c.h> #ifdef CONFIG_HARD_I2C diff --git a/board/sandburst/karef/init.S b/board/sandburst/karef/init.S index 2bdae06..11ab5af 100644 --- a/board/sandburst/karef/init.S +++ b/board/sandburst/karef/init.S @@ -26,6 +26,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/sandburst/metrobox/init.S b/board/sandburst/metrobox/init.S index fa78a3f..be3f885 100644 --- a/board/sandburst/metrobox/init.S +++ b/board/sandburst/metrobox/init.S @@ -24,6 +24,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /************************************************************************** * TLB TABLE diff --git a/board/sbc8349/pci.c b/board/sbc8349/pci.c index ca53356..e06874c 100644 --- a/board/sbc8349/pci.c +++ b/board/sbc8349/pci.c @@ -84,5 +84,5 @@ pci_init_board(void) udelay(2000); - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } diff --git a/board/sc3/init.S b/board/sc3/init.S index 6052c66..d374db4 100644 --- a/board/sc3/init.S +++ b/board/sc3/init.S @@ -27,7 +27,7 @@ *------------------------------------------------------------------------------- */ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/sc3/sc3.c b/board/sc3/sc3.c index 63927f7..f148ad6 100644 --- a/board/sc3/sc3.c +++ b/board/sc3/sc3.c @@ -331,16 +331,16 @@ int board_early_init_f (void) } /* Code decompression disabled */ - mtdcr (KIAR, KCONF); - mtdcr (KIDR, 0x2B); + mtdcr (DCP0_CFGADDR, KCONF); + mtdcr (DCP0_CFGDATA, 0x2B); /* CPC0_ER: enable sleep mode of (currently) unused components */ /* CPC0_FR: force unused components into sleep mode */ - mtdcr (CPMER, 0x3F800000); - mtdcr (CPMFR, 0x14000000); + mtdcr (CPC0_ER, 0x3F800000); + mtdcr (CPC0_FR, 0x14000000); /* set PLB priority */ - mtdcr (0x87, 0x08000000); + mtdcr (PLB0_ACR, 0x08000000); /* --------------- DMA stuff ------------------------------------- */ mtdcr (0x126, 0x49200000); diff --git a/board/sheldon/simpc8313/simpc8313.c b/board/sheldon/simpc8313/simpc8313.c index c2164c9..9126c42 100644 --- a/board/sheldon/simpc8313/simpc8313.c +++ b/board/sheldon/simpc8313/simpc8313.c @@ -67,7 +67,6 @@ void pci_init_board(void) volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; - int warmboot; /* Enable all 3 PCI_CLK_OUTPUTs. */ clk->occr |= 0xe0000000; @@ -81,9 +80,7 @@ void pci_init_board(void) pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR; pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB; - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - - mpc83xx_pci_init(1, reg, warmboot); + mpc83xx_pci_init(1, reg); } /* diff --git a/board/snmc/qs850/flash.c b/board/snmc/qs850/flash.c index a26a679..b592285 100644 --- a/board/snmc/qs850/flash.c +++ b/board/snmc/qs850/flash.c @@ -25,7 +25,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/u-boot.h> #include <asm/processor.h> diff --git a/board/snmc/qs860t/flash.c b/board/snmc/qs860t/flash.c index 48c2258..e725115 100644 --- a/board/snmc/qs860t/flash.c +++ b/board/snmc/qs860t/flash.c @@ -25,7 +25,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/u-boot.h> #include <asm/processor.h> diff --git a/board/syteco/jadecpu/config.mk b/board/syteco/jadecpu/config.mk index c661f0b..91994b0 100644 --- a/board/syteco/jadecpu/config.mk +++ b/board/syteco/jadecpu/config.mk @@ -1 +1 @@ -TEXT_BASE = 0x46000000 +TEXT_BASE = 0x10000000 diff --git a/board/syteco/jadecpu/jadecpu.c b/board/syteco/jadecpu/jadecpu.c index 04d2f9d..69476f8 100644 --- a/board/syteco/jadecpu/jadecpu.c +++ b/board/syteco/jadecpu/jadecpu.c @@ -154,12 +154,19 @@ int misc_init_r(void) */ int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM; - gd->bd->bi_dram[0].size = PHYS_SDRAM_SIZE; + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((volatile void *)PHYS_SDRAM, + PHYS_SDRAM_SIZE); return 0; } +void dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM; + gd->bd->bi_dram[0].size = gd->ram_size; +} + int board_eth_init(bd_t *bis) { int rc = 0; diff --git a/board/t3corp/t3corp.c b/board/t3corp/t3corp.c index ddf5897..04d6a2e 100644 --- a/board/t3corp/t3corp.c +++ b/board/t3corp/t3corp.c @@ -19,7 +19,7 @@ */ #include <common.h> -#include <ppc440.h> +#include <asm/ppc440.h> #include <libfdt.h> #include <fdt_support.h> #include <i2c.h> @@ -27,7 +27,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/4xx_pcie.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> int board_early_init_f(void) { diff --git a/board/tb0229/flash.c b/board/tb0229/flash.c index 1554642..75d7769 100644 --- a/board/tb0229/flash.c +++ b/board/tb0229/flash.c @@ -24,7 +24,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */ diff --git a/board/ti/beagle/config.mk b/board/ti/beagle/config.mk index 879b2e2..6fb10e3 100644 --- a/board/ti/beagle/config.mk +++ b/board/ti/beagle/config.mk @@ -30,4 +30,4 @@ # (mem base + reserved) # For use with external or internal boots. -TEXT_BASE = 0x80e80000 +TEXT_BASE = 0x80008000 diff --git a/board/tqc/tqm834x/pci.c b/board/tqc/tqm834x/pci.c index fcf4379..f35ea89 100644 --- a/board/tqc/tqm834x/pci.c +++ b/board/tqc/tqm834x/pci.c @@ -112,5 +112,5 @@ pci_init_board(void) udelay(2000); - mpc83xx_pci_init(1, reg, 0); + mpc83xx_pci_init(1, reg); } diff --git a/board/tqc/tqm834x/tqm834x.c b/board/tqc/tqm834x/tqm834x.c index 8d046f4..2aa97f2 100644 --- a/board/tqc/tqm834x/tqm834x.c +++ b/board/tqc/tqm834x/tqm834x.c @@ -30,6 +30,8 @@ #include <miiphy.h> #include <asm/mmu.h> #include <pci.h> +#include <flash.h> +#include <mtd/cfi_flash.h> DECLARE_GLOBAL_DATA_PTR; @@ -52,12 +54,8 @@ DECLARE_GLOBAL_DATA_PTR; #define INITIAL_CS_CONFIG (CSCONFIG_EN | CSCONFIG_ROW_BIT_12 | \ CSCONFIG_COL_BIT_9) -/* Global variable used to store detected number of banks */ -int tqm834x_num_flash_banks; - /* External definitions */ ulong flash_get_size (ulong base, int banknum); -extern flash_info_t flash_info[]; /* Local functions */ static int detect_num_flash_banks(void); @@ -190,7 +188,7 @@ static int detect_num_flash_banks(void) ulong bank2_size; ulong total_size; - tqm834x_num_flash_banks = 2; /* assume two banks */ + cfi_flash_num_flash_banks = 2; /* assume two banks */ /* Get bank 1 and 2 information */ bank1_size = flash_get_size(CONFIG_SYS_FLASH_BASE, 0); @@ -244,13 +242,13 @@ static int detect_num_flash_banks(void) * we got the some data reading from Flash. * There is only one mirrored bank. */ - tqm834x_num_flash_banks = 1; + cfi_flash_num_flash_banks = 1; total_size = bank1_size; } } } - debug("Number of flash banks detected: %d\n", tqm834x_num_flash_banks); + debug("Number of flash banks detected: %d\n", cfi_flash_num_flash_banks); /* set OR0 and BR0 */ set_lbc_or(0, CONFIG_SYS_OR_TIMING_FLASH | diff --git a/board/tqc/tqm8xx/tqm8xx.c b/board/tqc/tqm8xx/tqm8xx.c index cde780b..940cc8f 100644 --- a/board/tqc/tqm8xx/tqm8xx.c +++ b/board/tqc/tqm8xx/tqm8xx.c @@ -430,29 +430,6 @@ static long int dram_size (long int mamr_value, long int *base, long int maxsize /* ------------------------------------------------------------------------- */ -#ifdef CONFIG_PS2MULT - -#ifdef CONFIG_HMI10 -#define BASE_BAUD ( 1843200 / 16 ) -struct serial_state rs_table[] = { - { BASE_BAUD, 4, (void*)0xec140000 }, - { BASE_BAUD, 2, (void*)0xec150000 }, - { BASE_BAUD, 6, (void*)0xec160000 }, - { BASE_BAUD, 10, (void*)0xec170000 }, -}; - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ - ps2mult_early_init(); - return (0); -} -#endif -#endif /* CONFIG_HMI10 */ - -#endif /* CONFIG_PS2MULT */ - - #ifdef CONFIG_MISC_INIT_R extern void load_sernum_ethaddr(void); int misc_init_r (void) diff --git a/board/ve8313/ve8313.c b/board/ve8313/ve8313.c index 2272ff0..166e459 100644 --- a/board/ve8313/ve8313.c +++ b/board/ve8313/ve8313.c @@ -184,7 +184,6 @@ void pci_init_board(void) volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk; volatile law83xx_t *pci_law = immr->sysconf.pcilaw; struct pci_region *reg[] = { pci_regions }; - int warmboot; /* Enable all 3 PCI_CLK_OUTPUTs. */ setbits_be32(&clk->occr, 0xe0000000); @@ -198,9 +197,7 @@ void pci_init_board(void) out_be32(&pci_law[1].bar, CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR); out_be32(&pci_law[1].ar, LBLAWAR_EN | LBLAWAR_1MB); - warmboot = gd->bd->bi_bootflags & BOOTFLAG_WARM; - - mpc83xx_pci_init(1, reg, warmboot); + mpc83xx_pci_init(1, reg); } #endif diff --git a/board/w7o/flash.c b/board/w7o/flash.c index 6774949..184661b 100644 --- a/board/w7o/flash.c +++ b/board/w7o/flash.c @@ -24,7 +24,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <watchdog.h> diff --git a/board/w7o/init.S b/board/w7o/init.S index 5477f98..b3aadca 100644 --- a/board/w7o/init.S +++ b/board/w7o/init.S @@ -22,7 +22,7 @@ * *****************************************************************************/ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/w7o/post1.S b/board/w7o/post1.S index a6f46c8..0aaca02 100644 --- a/board/w7o/post1.S +++ b/board/w7o/post1.S @@ -27,7 +27,7 @@ * Routine to exercise memory for the bringing up of our boards. */ #include <config.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ diff --git a/board/xes/xpedite1000/init.S b/board/xes/xpedite1000/init.S index fa50c8e..27769cc 100644 --- a/board/xes/xpedite1000/init.S +++ b/board/xes/xpedite1000/init.S @@ -23,6 +23,7 @@ #include <ppc_asm.tmpl> #include <asm/mmu.h> #include <config.h> +#include <asm/ppc4xx.h> /* * TLB TABLE diff --git a/board/zeus/update.c b/board/zeus/update.c index 6119627..141f14b 100644 --- a/board/zeus/update.c +++ b/board/zeus/update.c @@ -26,7 +26,7 @@ #include <command.h> #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <i2c.h> #if defined(CONFIG_ZEUS) diff --git a/board/zeus/zeus.c b/board/zeus/zeus.c index e295151..a29e518 100644 --- a/board/zeus/zeus.c +++ b/board/zeus/zeus.c @@ -30,7 +30,7 @@ #include <asm/processor.h> #include <asm/io.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> DECLARE_GLOBAL_DATA_PTR; @@ -222,27 +222,8 @@ static int restore_default(void) char *buf_save; u32 crc; - /* - * Unprotect and erase environment area - */ - flash_protect(FLAG_PROTECT_CLEAR, - CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1, - &flash_info[0]); + set_default_env(""); - flash_sect_erase(CONFIG_ENV_ADDR_REDUND, - CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1); - - /* - * Now restore default environment from U-Boot image - * -> ipaddr, serverip... - */ - memset(env_ptr, 0, sizeof(env_t)); - memcpy(env_ptr->data, default_environment, ENV_SIZE); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; -#endif - env_crc_update(); gd->env_valid = 1; /* @@ -251,6 +232,10 @@ static int restore_default(void) * -> ethaddr, eth1addr, serial# */ buf = buf_save = malloc(FACTORY_RESET_ENV_SIZE); + if (buf == NULL) { + printf("ERROR: malloc() failed\n"); + return -1; + } if (eeprom_read(FACTORY_RESET_I2C_EEPROM, FACTORY_RESET_ENV_OFFS, (u8 *)buf, FACTORY_RESET_ENV_SIZE)) { puts("\nError reading EEPROM!\n"); @@ -104,8 +104,6 @@ uc101 powerpc mpc5xxx v38b powerpc mpc5xxx pf5200 powerpc mpc5xxx - esd aev powerpc mpc5xxx tqm5200 tqc -smmaco4 powerpc mpc5xxx tqm5200 tqc -spieval powerpc mpc5xxx tqm5200 tqc sorcery powerpc mpc8220 A3000 powerpc mpc824x a3000 barco powerpc mpc824x @@ -170,7 +168,6 @@ QS823 powerpc mpc8xx qs850 snmc QS850 powerpc mpc8xx qs850 snmc QS860T powerpc mpc8xx qs860t snmc stxxtc powerpc mpc8xx stxxtc stx -HMI10 powerpc mpc8xx tqm8xx tqc SM850 powerpc mpc8xx tqm8xx tqc AMX860 powerpc mpc8xx amx860 westel csb272 powerpc ppc4xx @@ -331,6 +328,7 @@ ppmc8260 powerpc mpc8260 RPXsuper powerpc mpc8260 rpxsuper rsdproto powerpc mpc8260 MPC8266ADS powerpc mpc8260 mpc8266ads freescale +mpc8308_p1m powerpc mpc83xx MPC8308RDB powerpc mpc83xx mpc8308rdb freescale MPC8323ERDB powerpc mpc83xx mpc8323erdb freescale MPC8349EMDS powerpc mpc83xx mpc8349emds freescale diff --git a/common/cmd_bdinfo.c b/common/cmd_bdinfo.c index 84c6ec8..6b611b1 100644 --- a/common/cmd_bdinfo.c +++ b/common/cmd_bdinfo.c @@ -330,7 +330,6 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) bd_t *bd = gd->bd; print_num ("arch_number", bd->bi_arch_number); - print_num ("env_t", (ulong)bd->bi_env); print_num ("boot_params", (ulong)bd->bi_boot_params); for (i=0; i<CONFIG_NR_DRAM_BANKS; ++i) { @@ -344,7 +343,16 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) printf ("ip_addr = %pI4\n", &bd->bi_ip_addr); #endif printf ("baudrate = %d bps\n", bd->bi_baudrate); - +#if !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +#if !(defined(CONFIG_SYS_NO_ICACHE) && defined(CONFIG_SYS_NO_DCACHE)) + print_num ("TLB addr", gd->tlb_addr); +#endif + print_num ("relocaddr", gd->relocaddr); + print_num ("reloc off", gd->reloc_off); + print_num ("irq_sp", gd->irq_sp); /* irq stack pointer */ + print_num ("sp start ", gd->start_addr_sp); + print_num ("FB base ", gd->fb_base); +#endif return 0; } diff --git a/common/cmd_bmp.c b/common/cmd_bmp.c index d51cc55..6fa8a15 100644 --- a/common/cmd_bmp.c +++ b/common/cmd_bmp.c @@ -137,6 +137,12 @@ static cmd_tbl_t cmd_bmp_sub[] = { U_BOOT_CMD_MKENT(display, 5, 0, do_bmp_display, "", ""), }; +#ifndef CONFIG_RELOC_FIXUP_WORKS +void bmp_reloc(void) { + fixup_cmdtable(cmd_bmp_sub, ARRAY_SIZE(cmd_bmp_sub)); +} +#endif + /* * Subroutine: do_bmp * diff --git a/common/cmd_bootm.c b/common/cmd_bootm.c index 4c6ed48..db59e6f 100644 --- a/common/cmd_bootm.c +++ b/common/cmd_bootm.c @@ -77,6 +77,7 @@ static int image_info (unsigned long addr); #if defined(CONFIG_CMD_IMLS) #include <flash.h> +#include <mtd/cfi_flash.h> extern flash_info_t flash_info[]; /* info for FLASH chips */ static int do_imls (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); #endif @@ -118,6 +119,9 @@ extern void lynxkdi_boot (image_header_t *); #ifdef CONFIG_BOOTM_RTEMS static boot_os_fn do_bootm_rtems; #endif +#if defined(CONFIG_BOOTM_OSE) +static boot_os_fn do_bootm_ose; +#endif #if defined(CONFIG_CMD_ELF) static boot_os_fn do_bootm_vxworks; static boot_os_fn do_bootm_qnxelf; @@ -141,6 +145,9 @@ static boot_os_fn *boot_os[] = { #ifdef CONFIG_BOOTM_RTEMS [IH_OS_RTEMS] = do_bootm_rtems, #endif +#if defined(CONFIG_BOOTM_OSE) + [IH_OS_OSE] = do_bootm_ose, +#endif #if defined(CONFIG_CMD_ELF) [IH_OS_VXWORKS] = do_bootm_vxworks, [IH_OS_QNX] = do_bootm_qnxelf, @@ -1382,6 +1389,39 @@ static int do_bootm_rtems (int flag, int argc, char * const argv[], } #endif /* CONFIG_BOOTM_RTEMS */ +#if defined(CONFIG_BOOTM_OSE) +static int do_bootm_ose (int flag, int argc, char * const argv[], + bootm_headers_t *images) +{ + void (*entry_point)(void); + + if ((flag != 0) && (flag != BOOTM_STATE_OS_GO)) + return 1; + +#if defined(CONFIG_FIT) + if (!images->legacy_hdr_valid) { + fit_unsupported_reset ("OSE"); + return 1; + } +#endif + + entry_point = (void (*)(void))images->ep; + + printf ("## Transferring control to OSE (at address %08lx) ...\n", + (ulong)entry_point); + + show_boot_progress (15); + + /* + * OSE Parameters: + * None + */ + (*entry_point)(); + + return 1; +} +#endif /* CONFIG_BOOTM_OSE */ + #if defined(CONFIG_CMD_ELF) static int do_bootm_vxworks (int flag, int argc, char * const argv[], bootm_headers_t *images) diff --git a/common/cmd_flash.c b/common/cmd_flash.c index ff43965..2a02eb9 100644 --- a/common/cmd_flash.c +++ b/common/cmd_flash.c @@ -42,6 +42,8 @@ int find_dev_and_part(const char *id, struct mtd_device **dev, #endif #ifndef CONFIG_SYS_NO_FLASH +#include <flash.h> +#include <mtd/cfi_flash.h> extern flash_info_t flash_info[]; /* info for FLASH chips */ /* @@ -417,11 +419,7 @@ int flash_sect_erase (ulong addr_first, ulong addr_last) { flash_info_t *info; ulong bank; -#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT - int s_first[CONFIG_SYS_MAX_FLASH_BANKS_DETECT], s_last[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; -#else int s_first[CONFIG_SYS_MAX_FLASH_BANKS], s_last[CONFIG_SYS_MAX_FLASH_BANKS]; -#endif int erased = 0; int planned; int rcode = 0; @@ -635,11 +633,7 @@ int flash_sect_protect (int p, ulong addr_first, ulong addr_last) { flash_info_t *info; ulong bank; -#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT - int s_first[CONFIG_SYS_MAX_FLASH_BANKS_DETECT], s_last[CONFIG_SYS_MAX_FLASH_BANKS_DETECT]; -#else int s_first[CONFIG_SYS_MAX_FLASH_BANKS], s_last[CONFIG_SYS_MAX_FLASH_BANKS]; -#endif int protected, i; int planned; int rcode; diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index 1283c82..0a0cfce 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -1284,10 +1284,19 @@ static cmd_tbl_t cmd_i2c_sub[] = { U_BOOT_CMD_MKENT(speed, 1, 1, do_i2c_bus_speed, "", ""), }; +#ifndef CONFIG_RELOC_FIXUP_WORKS +void i2c_reloc(void) { + fixup_cmdtable(cmd_i2c_sub, ARRAY_SIZE(cmd_i2c_sub)); +} +#endif + static int do_i2c(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) { cmd_tbl_t *c; + if (argc < 2) + return cmd_usage(cmdtp); + /* Strip off leading 'i2c' command argument */ argc--; argv++; diff --git a/common/cmd_ide.c b/common/cmd_ide.c index 6aeca76..ea0f4a7 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -818,7 +818,7 @@ set_pcmcia_timing (int pmode) static void input_swap_data(int dev, ulong *sect_buf, int words) { -#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) +#if defined(CONFIG_CPC45) uchar i; volatile uchar *pbuf_even = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_EVEN); volatile uchar *pbuf_odd = (uchar *)(ATA_CURR_BASE(dev)+ATA_DATA_ODD); @@ -858,7 +858,7 @@ input_swap_data(int dev, ulong *sect_buf, int words) static void output_data(int dev, ulong *sect_buf, int words) { -#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) +#if defined(CONFIG_CPC45) uchar *dbuf; volatile uchar *pbuf_even; volatile uchar *pbuf_odd; @@ -910,7 +910,7 @@ output_data(int dev, ulong *sect_buf, int words) static void input_data(int dev, ulong *sect_buf, int words) { -#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) +#if defined(CONFIG_CPC45) uchar *dbuf; volatile uchar *pbuf_even; volatile uchar *pbuf_odd; @@ -1544,7 +1544,6 @@ static void ide_reset (void) #if defined(CONFIG_IDE_LED) && \ !defined(CONFIG_CPC45) && \ - !defined(CONFIG_HMI10) && \ !defined(CONFIG_KUP4K) && \ !defined(CONFIG_KUP4X) @@ -1586,7 +1585,7 @@ int ide_device_present(int dev) static void output_data_shorts(int dev, ushort *sect_buf, int shorts) { -#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) +#if defined(CONFIG_CPC45) uchar *dbuf; volatile uchar *pbuf_even; volatile uchar *pbuf_odd; @@ -1618,7 +1617,7 @@ output_data_shorts(int dev, ushort *sect_buf, int shorts) static void input_data_shorts(int dev, ushort *sect_buf, int shorts) { -#if defined(CONFIG_HMI10) || defined(CONFIG_CPC45) +#if defined(CONFIG_CPC45) uchar *dbuf; volatile uchar *pbuf_even; volatile uchar *pbuf_odd; diff --git a/common/cmd_nvedit.c b/common/cmd_nvedit.c index c941b95..c3d63b8 100644 --- a/common/cmd_nvedit.c +++ b/common/cmd_nvedit.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -24,27 +24,26 @@ * MA 02111-1307 USA */ -/************************************************************************** - * +/* * Support for persistent environment data * - * The "environment" is stored as a list of '\0' terminated - * "name=value" strings. The end of the list is marked by a double - * '\0'. New entries are always added at the end. Deleting an entry - * shifts the remaining entries to the front. Replacing an entry is a - * combination of deleting the old value and adding the new one. - * - * The environment is preceeded by a 32 bit CRC over the data part. + * The "environment" is stored on external storage as a list of '\0' + * terminated "name=value" strings. The end of the list is marked by + * a double '\0'. The environment is preceeded by a 32 bit CRC over + * the data part and, in case of redundant environment, a byte of + * flags. * - ************************************************************************** + * This linearized representation will also be used before + * relocation, i. e. as long as we don't have a full C runtime + * environment. After that, we use a hash table. */ #include <common.h> #include <command.h> #include <environment.h> -#if defined(CONFIG_CMD_EDITENV) +#include <search.h> +#include <errno.h> #include <malloc.h> -#endif #include <watchdog.h> #include <serial.h> #include <linux/stddef.h> @@ -72,8 +71,10 @@ SPI_FLASH|MG_DISK|NVRAM|MMC|NOWHERE} #define XMK_STR(x) #x #define MK_STR(x) XMK_STR(x) -/************************************************************************ -************************************************************************/ +/* + * Maximum expected input data size for import command + */ +#define MAX_ENV_SIZE (1 << 20) /* 1 MiB */ /* * Table with supported baudrates (defined in config_xyz.h) @@ -82,7 +83,7 @@ static const unsigned long baudrate_table[] = CONFIG_SYS_BAUDRATE_TABLE; #define N_BAUDRATES (sizeof(baudrate_table) / sizeof(baudrate_table[0])) /* - * This variable is incremented on each do_setenv (), so it can + * This variable is incremented on each do_env_set(), so it can * be used via get_env_id() as an indication, if the environment * has changed or not. So it is possible to reread an environment * variable only if the environment was changed ... done so for @@ -94,61 +95,51 @@ int get_env_id (void) { return env_id; } -/************************************************************************ - * Command interface: print one or all environment variables - */ /* - * state 0: finish printing this string and return (matched!) - * state 1: no matching to be done; print everything - * state 2: continue searching for matched name + * Command interface: print one or all environment variables + * + * Returns 0 in case of error, or length of printed string */ -static int printenv(char *name, int state) +static int env_print(char *name) { - int i, j; - char c, buf[17]; - - i = 0; - buf[16] = '\0'; - - while (state && env_get_char(i) != '\0') { - if (state == 2 && envmatch((uchar *)name, i) >= 0) - state = 0; - - j = 0; - do { - buf[j++] = c = env_get_char(i++); - if (j == sizeof(buf) - 1) { - if (state <= 1) - puts(buf); - j = 0; - } - } while (c != '\0'); + char *res = NULL; + size_t len; + + if (name) { /* print a single name */ + ENTRY e, *ep; + + e.key = name; + e.data = NULL; + ep = hsearch (e, FIND); + if (ep == NULL) + return 0; + len = printf ("%s=%s\n", ep->key, ep->data); + return len; + } - if (state <= 1) { - if (j) - puts(buf); - putc('\n'); - } + /* print whole list */ + len = hexport('\n', &res, 0); - if (ctrlc()) - return -1; + if (len > 0) { + puts(res); + free(res); + return len; } - if (state == 0) - i = 0; - return i; + /* should never happen */ + return 0; } -int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_env_print (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { int i; int rcode = 0; if (argc == 1) { /* print all env vars */ - rcode = printenv(NULL, 1); - if (rcode < 0) + rcode = env_print(NULL); + if (!rcode) return 1; printf("\nEnvironment size: %d/%ld bytes\n", rcode, (ulong)ENV_SIZE); @@ -157,9 +148,9 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) /* print selected env vars */ for (i = 1; i < argc; ++i) { - char *name = argv[i]; - if (printenv(name, 2)) { - printf("## Error: \"%s\" not defined\n", name); + int rc = env_print(argv[i]); + if (!rc) { + printf("## Error: \"%s\" not defined\n", argv[i]); ++rcode; } } @@ -167,25 +158,18 @@ int do_printenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return rcode; } -/************************************************************************ +/* * Set a new environment variable, * or replace or delete an existing one. - * - * This function will ONLY work with a in-RAM copy of the environment */ -int _do_setenv (int flag, int argc, char * const argv[]) +int _do_env_set (int flag, int argc, char * const argv[]) { - int i, len, oldval; + bd_t *bd = gd->bd; + int i, len; int console = -1; - uchar *env, *nxt = NULL; - char *name; - bd_t *bd = gd->bd; - - uchar *env_data = env_get_addr(0); - - if (!env_data) /* need copy in RAM */ - return 1; + char *name, *value, *s; + ENTRY e, *ep; name = argv[1]; @@ -198,13 +182,9 @@ int _do_setenv (int flag, int argc, char * const argv[]) /* * search if variable with this name already exists */ - oldval = -1; - for (env=env_data; *env; env=nxt+1) { - for (nxt=env; *nxt; ++nxt) - ; - if ((oldval = envmatch((uchar *)name, env-env_data)) >= 0) - break; - } + e.key = name; + e.data = NULL; + ep = hsearch (e, FIND); /* Check for console redirection */ if (strcmp(name,"stdin") == 0) { @@ -238,36 +218,25 @@ int _do_setenv (int flag, int argc, char * const argv[]) } /* - * Delete any existing definition + * Some variables like "ethaddr" and "serial#" can be set only + * once and cannot be deleted; also, "ver" is readonly. */ - if (oldval >= 0) { + if (ep) { /* variable exists */ #ifndef CONFIG_ENV_OVERWRITE - - /* - * Ethernet Address and serial# can be set only once, - * ver is readonly. - */ - if ( -#ifdef CONFIG_HAS_UID - /* Allow serial# forced overwrite with 0xdeaf4add flag */ - ((strcmp (name, "serial#") == 0) && (flag != 0xdeaf4add)) || -#else - (strcmp (name, "serial#") == 0) || -#endif + if ((strcmp (name, "serial#") == 0) || ((strcmp (name, "ethaddr") == 0) #if defined(CONFIG_OVERWRITE_ETHADDR_ONCE) && defined(CONFIG_ETHADDR) - && (strcmp ((char *)env_get_addr(oldval),MK_STR(CONFIG_ETHADDR)) != 0) + && (strcmp (ep->data,MK_STR(CONFIG_ETHADDR)) != 0) #endif /* CONFIG_OVERWRITE_ETHADDR_ONCE && CONFIG_ETHADDR */ ) ) { printf ("Can't overwrite \"%s\"\n", name); return 1; } #endif - /* * Switch to new baudrate if new baudrate is supported */ - if (strcmp(argv[1],"baudrate") == 0) { + if (strcmp(name,"baudrate") == 0) { int baudrate = simple_strtoul(argv[2], NULL, 10); int i; for (i=0; i<N_BAUDRATES; ++i) { @@ -294,75 +263,50 @@ int _do_setenv (int flag, int argc, char * const argv[]) break; } } - - if (*++nxt == '\0') { - if (env > env_data) { - env--; - } else { - *env = '\0'; - } - } else { - for (;;) { - *env = *nxt++; - if ((*env == '\0') && (*nxt == '\0')) - break; - ++env; - } - } - *++env = '\0'; } /* Delete only ? */ if ((argc < 3) || argv[2] == NULL) { - env_crc_update (); - return 0; + int rc = hdelete(name); + return !rc; } /* - * Append new definition at the end + * Insert / replace new value */ - for (env=env_data; *env || *(env+1); ++env) - ; - if (env > env_data) - ++env; - /* - * Overflow when: - * "name" + "=" + "val" +"\0\0" > ENV_SIZE - (env-env_data) - */ - len = strlen(name) + 2; - /* add '=' for first arg, ' ' for all others */ - for (i=2; i<argc; ++i) { + for (i=2,len=0; i<argc; ++i) { len += strlen(argv[i]) + 1; } - if (len > (&env_data[ENV_SIZE]-env)) { - printf ("## Error: environment overflow, \"%s\" deleted\n", name); + if ((value = malloc(len)) == NULL) { + printf("## Can't malloc %d bytes\n", len); return 1; } - while ((*env = *name++) != '\0') - env++; - for (i=2; i<argc; ++i) { - char *val = argv[i]; + for (i=2,s=value; i<argc; ++i) { + char *v = argv[i]; - *env = (i==2) ? '=' : ' '; - while ((*++env = *val++) != '\0') + while ((*s++ = *v++) != '\0') ; + *(s-1) = ' '; + } + if (s != value) + *--s = '\0'; + + e.key = name; + e.data = value; + ep = hsearch(e, ENTER); + free(value); + if (!ep) { + printf("## Error inserting \"%s\" variable, errno=%d\n", + name, errno); + return 1; } - - /* end is marked with double '\0' */ - *++env = '\0'; - - /* Update CRC */ - env_crc_update (); /* * Some variables should be updated when the corresponding - * entry in the enviornment is changed + * entry in the environment is changed */ - if (strcmp(argv[1],"ethaddr") == 0) - return 0; - - if (strcmp(argv[1],"ipaddr") == 0) { + if (strcmp(name,"ipaddr") == 0) { char *s = argv[2]; /* always use only one arg */ char *e; unsigned long addr; @@ -375,13 +319,12 @@ int _do_setenv (int flag, int argc, char * const argv[]) } bd->bi_ip_addr = htonl(addr); return 0; - } - if (strcmp(argv[1],"loadaddr") == 0) { + } else if (strcmp(argv[1],"loadaddr") == 0) { load_addr = simple_strtoul(argv[2], NULL, 16); return 0; } #if defined(CONFIG_CMD_NET) - if (strcmp(argv[1],"bootfile") == 0) { + else if (strcmp(argv[1],"bootfile") == 0) { copy_filename (BootFile, argv[2], sizeof(BootFile)); return 0; } @@ -393,38 +336,29 @@ int setenv (char *varname, char *varvalue) { char * const argv[4] = { "setenv", varname, varvalue, NULL }; if ((varvalue == NULL) || (varvalue[0] == '\0')) - return _do_setenv (0, 2, argv); + return _do_env_set(0, 2, argv); else - return _do_setenv (0, 3, argv); -} - -#ifdef CONFIG_HAS_UID -void forceenv (char *varname, char *varvalue) -{ - char * const argv[4] = { "forceenv", varname, varvalue, NULL }; - _do_setenv (0xdeaf4add, 3, argv); + return _do_env_set(0, 3, argv); } -#endif -int do_setenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_env_set (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { if (argc < 2) return cmd_usage(cmdtp); - return _do_setenv (flag, argc, argv); + return _do_env_set(flag, argc, argv); } -/************************************************************************ +/* * Prompt for environment variable */ - #if defined(CONFIG_CMD_ASKENV) -int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_env_ask ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { extern char console_buffer[CONFIG_SYS_CBSIZE]; char message[CONFIG_SYS_CBSIZE]; int size = CONFIG_SYS_CBSIZE - 1; - int len; + int i, len, pos; char *local_args[4]; local_args[0] = argv[0]; @@ -432,38 +366,30 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) local_args[2] = NULL; local_args[3] = NULL; - if (argc < 2) - return cmd_usage(cmdtp); - /* Check the syntax */ switch (argc) { case 1: return cmd_usage(cmdtp); - case 2: /* askenv envname */ - sprintf (message, "Please enter '%s':", argv[1]); + case 2: /* env_ask envname */ + sprintf(message, "Please enter '%s':", argv[1]); break; - case 3: /* askenv envname size */ - sprintf (message, "Please enter '%s':", argv[1]); - size = simple_strtoul (argv[2], NULL, 10); + case 3: /* env_ask envname size */ + sprintf(message, "Please enter '%s':", argv[1]); + size = simple_strtoul(argv[2], NULL, 10); break; - default: /* askenv envname message1 ... messagen size */ - { - int i; - int pos = 0; - - for (i = 2; i < argc - 1; i++) { + default: /* env_ask envname message1 ... messagen size */ + for (i=2,pos=0; i < argc - 1; i++) { if (pos) { message[pos++] = ' '; } - strcpy (message+pos, argv[i]); + strcpy(message+pos, argv[i]); pos += strlen(argv[i]); } message[pos] = '\0'; - size = simple_strtoul (argv[argc - 1], NULL, 10); - } + size = simple_strtoul(argv[argc - 1], NULL, 10); break; } @@ -474,7 +400,7 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 1; /* prompt for input */ - len = readline (message); + len = readline(message); if (size < len) console_buffer[size] = '\0'; @@ -486,15 +412,15 @@ int do_askenv ( cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } /* Continue calling setenv code */ - return _do_setenv (flag, len, local_args); + return _do_env_set(flag, len, local_args); } #endif -/************************************************************************ +/* * Interactively edit an environment variable */ #if defined(CONFIG_CMD_EDITENV) -int do_editenv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_env_edit(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { char buffer[CONFIG_SYS_CBSIZE]; char *init_val; @@ -516,35 +442,37 @@ int do_editenv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } #endif /* CONFIG_CMD_EDITENV */ -/************************************************************************ +/* * Look up variable from environment, * return address of storage for that variable, * or NULL if not found */ - char *getenv (char *name) { - int i, nxt; + if (gd->flags & GD_FLG_ENV_READY) { /* after import into hashtable */ + ENTRY e, *ep; - WATCHDOG_RESET(); + WATCHDOG_RESET(); - for (i=0; env_get_char(i) != '\0'; i=nxt+1) { - int val; + e.key = name; + e.data = NULL; + ep = hsearch (e, FIND); - for (nxt=i; env_get_char(nxt) != '\0'; ++nxt) { - if (nxt >= CONFIG_ENV_SIZE) { - return (NULL); - } - } - if ((val=envmatch((uchar *)name, i)) < 0) - continue; - return ((char *)env_get_addr(val)); + return (ep ? ep->data : NULL); } - return (NULL); + /* restricted capabilities before import */ + + if (getenv_f(name, (char *)(gd->env_buf), sizeof(gd->env_buf)) > 0) + return (char *)(gd->env_buf); + + return NULL; } -int getenv_f(char *name, char *buf, unsigned len) +/* + * Look up variable from environment for restricted C runtime env. + */ +int getenv_f (char *name, char *buf, unsigned len) { int i, nxt; @@ -577,7 +505,7 @@ int getenv_f(char *name, char *buf, unsigned len) #if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) -int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +int do_env_save (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { extern char * env_name_spec; @@ -587,7 +515,7 @@ int do_saveenv (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) } U_BOOT_CMD( - saveenv, 1, 0, do_saveenv, + saveenv, 1, 0, do_env_save, "save environment variables to persistent storage", "" ); @@ -595,7 +523,7 @@ U_BOOT_CMD( #endif -/************************************************************************ +/* * Match a name / name=value pair * * s1 is either a simple 'name', or a 'name=value' pair. @@ -614,12 +542,345 @@ int envmatch (uchar *s1, int i2) return(-1); } +static int do_env_default(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + if ((argc != 2) || (strcmp(argv[1], "-f") != 0)) { + cmd_usage(cmdtp); + return 1; + } + set_default_env("## Resetting to default environment\n"); + return 0; +} + +static int do_env_delete(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + printf("Not implemented yet\n"); + return 0; +} -/**************************************************/ +/* + * env export [-t | -b | -c] addr [size] + * -t: export as text format; if size is given, data will be + * padded with '\0' bytes; if not, one terminating '\0' + * will be added (which is included in the "filesize" + * setting so you can for exmple copy this to flash and + * keep the termination). + * -b: export as binary format (name=value pairs separated by + * '\0', list end marked by double "\0\0") + * -c: export as checksum protected environment format as + * used for example by "saveenv" command + * addr: memory address where environment gets stored + * size: size of output buffer + * + * With "-c" and size is NOT given, then the export command will + * format the data as currently used for the persistent storage, + * i. e. it will use CONFIG_ENV_SECT_SIZE as output block size and + * prepend a valid CRC32 checksum and, in case of resundant + * environment, a "current" redundancy flag. If size is given, this + * value will be used instead of CONFIG_ENV_SECT_SIZE; again, CRC32 + * checksum and redundancy flag will be inserted. + * + * With "-b" and "-t", always only the real data (including a + * terminating '\0' byte) will be written; here the optional size + * argument will be used to make sure not to overflow the user + * provided buffer; the command will abort if the size is not + * sufficient. Any remainign space will be '\0' padded. + * + * On successful return, the variable "filesize" will be set. + * Note that filesize includes the trailing/terminating '\0' byte(s). + * + * Usage szenario: create a text snapshot/backup of the current settings: + * + * => env export -t 100000 + * => era ${backup_addr} +${filesize} + * => cp.b 100000 ${backup_addr} ${filesize} + * + * Re-import this snapshot, deleting all other settings: + * + * => env import -d -t ${backup_addr} + */ +static int do_env_export(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + char buf[32]; + char *addr, *cmd, *res; + size_t size; + ssize_t len; + env_t *envp; + char sep = '\n'; + int chk = 0; + int fmt = 0; + + cmd = *argv; + + while (--argc > 0 && **++argv == '-') { + char *arg = *argv; + while (*++arg) { + switch (*arg) { + case 'b': /* raw binary format */ + if (fmt++) + goto sep_err; + sep = '\0'; + break; + case 'c': /* external checksum format */ + if (fmt++) + goto sep_err; + sep = '\0'; + chk = 1; + break; + case 't': /* text format */ + if (fmt++) + goto sep_err; + sep = '\n'; + break; + default: + cmd_usage(cmdtp); + return 1; + } + } + } + + if (argc < 1) { + cmd_usage(cmdtp); + return 1; + } + + addr = (char *)simple_strtoul(argv[0], NULL, 16); + + if (argc == 2) { + size = simple_strtoul(argv[1], NULL, 16); + memset(addr, '\0', size); + } else { + size = 0; + } + + if (sep) { /* export as text file */ + len = hexport(sep, &addr, size); + if (len < 0) { + error("Cannot export environment: errno = %d\n", + errno); + return 1; + } + sprintf(buf, "%zX", len); + setenv("filesize", buf); + + return 0; + } + + envp = (env_t *)addr; + + if (chk) /* export as checksum protected block */ + res = (char *)envp->data; + else /* export as raw binary data */ + res = addr; + + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", + errno); + return 1; + } + + if (chk) { + envp->crc = crc32(0, envp->data, ENV_SIZE); +#ifdef CONFIG_ENV_ADDR_REDUND + envp->flags = ACTIVE_FLAG; +#endif + } + sprintf(buf, "%zX", len + offsetof(env_t,data)); + setenv("filesize", buf); + + return 0; + +sep_err: + printf("## %s: only one of \"-b\", \"-c\" or \"-t\" allowed\n", + cmd); + return 1; +} + +/* + * env import [-d] [-t | -b | -c] addr [size] + * -d: delete existing environment before importing; + * otherwise overwrite / append to existion definitions + * -t: assume text format; either "size" must be given or the + * text data must be '\0' terminated + * -b: assume binary format ('\0' separated, "\0\0" terminated) + * -c: assume checksum protected environment format + * addr: memory address to read from + * size: length of input data; if missing, proper '\0' + * termination is mandatory + */ +static int do_env_import(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[]) +{ + char *cmd, *addr; + char sep = '\n'; + int chk = 0; + int fmt = 0; + int del = 0; + size_t size; + + cmd = *argv; + + while (--argc > 0 && **++argv == '-') { + char *arg = *argv; + while (*++arg) { + switch (*arg) { + case 'b': /* raw binary format */ + if (fmt++) + goto sep_err; + sep = '\0'; + break; + case 'c': /* external checksum format */ + if (fmt++) + goto sep_err; + sep = '\0'; + chk = 1; + break; + case 't': /* text format */ + if (fmt++) + goto sep_err; + sep = '\n'; + break; + case 'd': + del = 1; + break; + default: + cmd_usage(cmdtp); + return 1; + } + } + } + + if (argc < 1) { + cmd_usage(cmdtp); + return 1; + } + + if (!fmt) + printf("## Warning: defaulting to text format\n"); + + addr = (char *)simple_strtoul(argv[0], NULL, 16); + + if (argc == 2) { + size = simple_strtoul(argv[1], NULL, 16); + } else { + char *s = addr; + + size = 0; + + while (size < MAX_ENV_SIZE) { + if ((*s == sep) && (*(s+1) == '\0')) + break; + ++s; + ++size; + } + if (size == MAX_ENV_SIZE) { + printf("## Warning: Input data exceeds %d bytes" + " - truncated\n", MAX_ENV_SIZE); + } + ++size; + printf("## Info: input data size = %zd = 0x%zX\n", size, size); + } + + if (chk) { + uint32_t crc; + env_t *ep = (env_t *)addr; + + size -= offsetof(env_t, data); + memcpy(&crc, &ep->crc, sizeof(crc)); + + if (crc32(0, ep->data, size) != crc) { + puts("## Error: bad CRC, import failed\n"); + return 1; + } + addr = (char *)ep->data; + } + + if (himport(addr, size, sep, del ? 0 : H_NOCLEAR) == 0) { + error("Environment import failed: errno = %d\n", errno); + return 1; + } + gd->flags |= GD_FLG_ENV_READY; + + return 0; + +sep_err: + printf("## %s: only one of \"-b\", \"-c\" or \"-t\" allowed\n", + cmd); + return 1; +} + +#if defined(CONFIG_CMD_RUN) +extern int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); +#endif + +/* + * New command line interface: "env" command with subcommands + */ +static cmd_tbl_t cmd_env_sub[] = { +#if defined(CONFIG_CMD_ASKENV) + U_BOOT_CMD_MKENT(ask, CONFIG_SYS_MAXARGS, 1, do_env_ask, "", ""), +#endif + U_BOOT_CMD_MKENT(default, 1, 0, do_env_default, "", ""), + U_BOOT_CMD_MKENT(delete, 2, 0, do_env_delete, "", ""), +#if defined(CONFIG_CMD_EDITENV) + U_BOOT_CMD_MKENT(edit, 2, 0, do_env_edit, "", ""), +#endif + U_BOOT_CMD_MKENT(export, 4, 0, do_env_export, "", ""), + U_BOOT_CMD_MKENT(import, 5, 0, do_env_import, "", ""), + U_BOOT_CMD_MKENT(print, CONFIG_SYS_MAXARGS, 1, do_env_print, "", ""), +#if defined(CONFIG_CMD_RUN) + U_BOOT_CMD_MKENT(run, CONFIG_SYS_MAXARGS, 1, do_run, "", ""), +#endif +#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE) + U_BOOT_CMD_MKENT(save, 1, 0, do_env_save, "", ""), +#endif + U_BOOT_CMD_MKENT(set, CONFIG_SYS_MAXARGS, 0, do_env_set, "", ""), +}; + +static int do_env (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + cmd_tbl_t *cp; + + /* drop initial "env" arg */ + argc--; + argv++; + + cp = find_cmd_tbl(argv[0], cmd_env_sub, ARRAY_SIZE(cmd_env_sub)); + + if (cp) + return cp->cmd(cmdtp, flag, argc, argv); + + cmd_usage(cmdtp); + return 1; +} + +U_BOOT_CMD( + env, CONFIG_SYS_MAXARGS, 1, do_env, + "environment handling commands", +#if defined(CONFIG_CMD_ASKENV) + "ask name [message] [size] - ask for environment variable\nenv " +#endif + "default -f - reset default environment\n" +#if defined(CONFIG_CMD_EDITENV) + "env edit name - edit environment variable\n" +#endif + "env export [-t | -b | -c] addr [size] - export environmnt\n" + "env import [-d] [-t | -b | -c] addr [size] - import environmnt\n" + "env print [name ...] - print environment\n" +#if defined(CONFIG_CMD_RUN) + "env run var [...] - run commands in an environment variable\n" +#endif + "env save - save environment\n" + "env set [-f] name [arg ...]\n" +); + +/* + * Old command line interface, kept for compatibility + */ #if defined(CONFIG_CMD_EDITENV) U_BOOT_CMD( - editenv, 2, 0, do_editenv, + editenv, 2, 0, do_env_edit, "edit environment variable", "name\n" " - edit environment variable 'name'" @@ -627,7 +888,7 @@ U_BOOT_CMD( #endif U_BOOT_CMD( - printenv, CONFIG_SYS_MAXARGS, 1, do_printenv, + printenv, CONFIG_SYS_MAXARGS, 1, do_env_print, "print environment variables", "\n - print values of all environment variables\n" "printenv name ...\n" @@ -635,7 +896,7 @@ U_BOOT_CMD( ); U_BOOT_CMD( - setenv, CONFIG_SYS_MAXARGS, 0, do_setenv, + setenv, CONFIG_SYS_MAXARGS, 0, do_env_set, "set environment variables", "name value ...\n" " - set environment variable 'name' to 'value ...'\n" @@ -646,7 +907,7 @@ U_BOOT_CMD( #if defined(CONFIG_CMD_ASKENV) U_BOOT_CMD( - askenv, CONFIG_SYS_MAXARGS, 1, do_askenv, + askenv, CONFIG_SYS_MAXARGS, 1, do_env_ask, "get environment variables from stdin", "name [message] [size]\n" " - get environment variable 'name' from stdin (max 'size' chars)\n" @@ -661,7 +922,6 @@ U_BOOT_CMD( #endif #if defined(CONFIG_CMD_RUN) -int do_run (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); U_BOOT_CMD( run, CONFIG_SYS_MAXARGS, 1, do_run, "run commands in an environment variable", diff --git a/common/command.c b/common/command.c index 30a9801..d47d719 100644 --- a/common/command.c +++ b/common/command.c @@ -160,6 +160,7 @@ int cmd_usage(cmd_tbl_t *cmdtp) int var_complete(int argc, char * const argv[], char last_char, int maxv, char *cmdv[]) { +#if 0 /* need to reimplement */ static char tmp_buf[512]; int space; @@ -170,7 +171,7 @@ int var_complete(int argc, char * const argv[], char last_char, int maxv, char * if (!space && argc == 2) return env_complete(argv[1], maxv, cmdv, sizeof(tmp_buf), tmp_buf); - +#endif return 0; } @@ -464,3 +465,40 @@ int cmd_get_data_size(char* arg, int default_size) return default_size; } #endif + +#if !defined(CONFIG_RELOC_FIXUP_WORKS) +DECLARE_GLOBAL_DATA_PTR; + +void fixup_cmdtable(cmd_tbl_t *cmdtp, int size) +{ + int i; + + if (gd->reloc_off == 0) + return; + + for (i = 0; i < size; i++) { + ulong addr; + + addr = (ulong) (cmdtp->cmd) + gd->reloc_off; +#if DEBUG_COMMANDS + printf("Command \"%s\": 0x%08lx => 0x%08lx\n", + cmdtp->name, (ulong) (cmdtp->cmd), addr); +#endif + cmdtp->cmd = + (int (*)(struct cmd_tbl_s *, int, int, char * const []))addr; + addr = (ulong)(cmdtp->name) + gd->reloc_off; + cmdtp->name = (char *)addr; + if (cmdtp->usage) { + addr = (ulong)(cmdtp->usage) + gd->reloc_off; + cmdtp->usage = (char *)addr; + } +#ifdef CONFIG_SYS_LONGHELP + if (cmdtp->help) { + addr = (ulong)(cmdtp->help) + gd->reloc_off; + cmdtp->help = (char *)addr; + } +#endif + cmdtp++; + } +} +#endif diff --git a/common/dlmalloc.c b/common/dlmalloc.c index 2276532..ae5702d 100644 --- a/common/dlmalloc.c +++ b/common/dlmalloc.c @@ -222,7 +222,6 @@ - /* Preliminaries */ #ifndef __STD_C @@ -935,10 +934,10 @@ struct mallinfo mALLINFo(); #endif /* ---------- To make a malloc.h, end cutting here ------------ */ -#else /* Moved to malloc.h */ +#endif /* 0 */ /* Moved to malloc.h */ #include <malloc.h> -#if 0 +#ifdef DEBUG #if __STD_C static void malloc_update_mallinfo (void); void malloc_stats (void); @@ -946,9 +945,7 @@ void malloc_stats (void); static void malloc_update_mallinfo (); void malloc_stats(); #endif -#endif /* 0 */ - -#endif /* 0 */ /* Moved to malloc.h */ +#endif /* DEBUG */ DECLARE_GLOBAL_DATA_PTR; @@ -1618,9 +1615,9 @@ static struct mallinfo current_mallinfo = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }; /* Tracking mmaps */ -#if 0 +#ifdef DEBUG static unsigned int n_mmaps = 0; -#endif /* 0 */ +#endif /* DEBUG */ static unsigned long mmapped_mem = 0; #if HAVE_MMAP static unsigned int max_n_mmaps = 0; @@ -3101,7 +3098,7 @@ size_t malloc_usable_size(mem) Void_t* mem; /* Utility to update current_mallinfo for malloc_stats and mallinfo() */ -#if 0 +#ifdef DEBUG static void malloc_update_mallinfo() { int i; @@ -3139,7 +3136,7 @@ static void malloc_update_mallinfo() current_mallinfo.keepcost = chunksize(top); } -#endif /* 0 */ +#endif /* DEBUG */ @@ -3158,7 +3155,7 @@ static void malloc_update_mallinfo() */ -#if 0 +#ifdef DEBUG void malloc_stats() { malloc_update_mallinfo(); @@ -3173,19 +3170,19 @@ void malloc_stats() (unsigned int)max_n_mmaps); #endif } -#endif /* 0 */ +#endif /* DEBUG */ /* mallinfo returns a copy of updated current mallinfo. */ -#if 0 +#ifdef DEBUG struct mallinfo mALLINFo() { malloc_update_mallinfo(); return current_mallinfo; } -#endif /* 0 */ +#endif /* DEBUG */ diff --git a/common/env_common.c b/common/env_common.c index 460309b..a415ef8 100644 --- a/common/env_common.c +++ b/common/env_common.c @@ -1,10 +1,10 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Andreas Heppel <aheppel@sysgo.de> - + * * See file CREDITS for list of people who contributed to this * project. * @@ -28,17 +28,12 @@ #include <command.h> #include <environment.h> #include <linux/stddef.h> +#include <search.h> +#include <errno.h> #include <malloc.h> DECLARE_GLOBAL_DATA_PTR; -#undef DEBUG_ENV -#ifdef DEBUG_ENV -#define DEBUGF(fmt,args...) printf(fmt ,##args) -#else -#define DEBUGF(fmt,args...) -#endif - extern env_t *env_ptr; extern void env_relocate_spec (void); @@ -134,33 +129,22 @@ uchar default_environment[] = { "\0" }; -void env_crc_update (void) -{ - env_ptr->crc = crc32(0, env_ptr->data, ENV_SIZE); -} - static uchar env_get_char_init (int index) { uchar c; /* if crc was bad, use the default environment */ if (gd->env_valid) - { c = env_get_char_spec(index); - } else { + else c = default_environment[index]; - } return (c); } uchar env_get_char_memory (int index) { - if (gd->env_valid) { - return ( *((uchar *)(gd->env_addr + index)) ); - } else { - return ( default_environment[index] ); - } + return *env_get_addr(index); } uchar env_get_char (int index) @@ -178,70 +162,84 @@ uchar env_get_char (int index) uchar *env_get_addr (int index) { - if (gd->env_valid) { - return ( ((uchar *)(gd->env_addr + index)) ); - } else { - return (&default_environment[index]); - } + if (gd->env_valid) + return (uchar *)(gd->env_addr + index); + else + return &default_environment[index]; } -void set_default_env(void) +void set_default_env(const char *s) { if (sizeof(default_environment) > ENV_SIZE) { - puts ("*** Error - default environment is too large\n\n"); + puts("*** Error - default environment is too large\n\n"); return; } - memset(env_ptr, 0, sizeof(env_t)); - memcpy(env_ptr->data, default_environment, - sizeof(default_environment)); -#ifdef CONFIG_SYS_REDUNDAND_ENVIRONMENT - env_ptr->flags = 0xFF; -#endif - env_crc_update (); - gd->env_valid = 1; + if (s) { + if (*s == '!') { + printf("*** Warning - %s, " + "using default environment\n\n", + s+1); + } else { + puts(s); + } + } else { + puts("Using default environment\n\n"); + } + + if (himport((char *)default_environment, + sizeof(default_environment), '\0', 0) == 0) { + error("Environment import failed: errno = %d\n", errno); + } + gd->flags |= GD_FLG_ENV_READY; } -void env_relocate (void) +/* + * Check if CRC is valid and (if yes) import the environment. + * Note that "buf" may or may not be aligned. + */ +int env_import(const char *buf, int check) { -#ifndef CONFIG_RELOC_FIXUP_WORKS - DEBUGF ("%s[%d] offset = 0x%lx\n", __FUNCTION__,__LINE__, - gd->reloc_off); -#endif + env_t *ep = (env_t *)buf; -#ifdef ENV_IS_EMBEDDED - /* - * The environment buffer is embedded with the text segment, - * just relocate the environment pointer - */ -#ifndef CONFIG_RELOC_FIXUP_WORKS - env_ptr = (env_t *)((ulong)env_ptr + gd->reloc_off); -#endif - DEBUGF ("%s[%d] embedded ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); -#else - /* - * We must allocate a buffer for the environment - */ - env_ptr = (env_t *)malloc (CONFIG_ENV_SIZE); - DEBUGF ("%s[%d] malloced ENV at %p\n", __FUNCTION__,__LINE__,env_ptr); -#endif + if (check) { + uint32_t crc; + + memcpy(&crc, &ep->crc, sizeof(crc)); + + if (crc32(0, ep->data, ENV_SIZE) != crc) { + set_default_env("!bad CRC"); + return 0; + } + } + + if (himport((char *)ep->data, ENV_SIZE, '\0', 0)) { + gd->flags |= GD_FLG_ENV_READY; + return 1; + } + error("Cannot import environment: errno = %d\n", errno); + + set_default_env("!import failed"); + + return 0; +} + +void env_relocate (void) +{ if (gd->env_valid == 0) { #if defined(CONFIG_ENV_IS_NOWHERE) /* Environment not changable */ - puts ("Using default environment\n\n"); + set_default_env(NULL); #else - puts ("*** Warning - bad CRC, using default environment\n\n"); show_boot_progress (-60); #endif - set_default_env(); - } - else { + set_default_env("!bad CRC"); + } else { env_relocate_spec (); } - gd->env_addr = (ulong)&(env_ptr->data); } -#ifdef CONFIG_AUTO_COMPLETE +#if 0 /* need to reimplement - def CONFIG_AUTO_COMPLETE */ int env_complete(char *var, int maxv, char *cmdv[], int bufsz, char *buf) { int i, nxt, len, vallen, found; diff --git a/common/env_dataflash.c b/common/env_dataflash.c index 27a3bbc..270f2b3 100644 --- a/common/env_dataflash.c +++ b/common/env_dataflash.c @@ -1,4 +1,5 @@ -/* LowLevel function for DataFlash environment support +/* + * LowLevel function for DataFlash environment support * Author : Gilles Gastaldi (Atmel) * * This program is free software; you can redistribute it and/or @@ -15,13 +16,14 @@ * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA - * */ #include <common.h> #include <command.h> #include <environment.h> #include <linux/stddef.h> #include <dataflash.h> +#include <search.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -29,39 +31,59 @@ env_t *env_ptr = NULL; char * env_name_spec = "dataflash"; -extern int read_dataflash (unsigned long addr, unsigned long size, char -*result); -extern int write_dataflash (unsigned long addr_dest, unsigned long addr_src, - unsigned long size); -extern int AT91F_DataflashInit (void); -extern uchar default_environment[]; +extern int read_dataflash(unsigned long addr, unsigned long size, + char *result); +extern int write_dataflash(unsigned long addr_dest, + unsigned long addr_src, unsigned long size); +extern int AT91F_DataflashInit(void); +extern uchar default_environment[]; -uchar env_get_char_spec (int index) +uchar env_get_char_spec(int index) { uchar c; + read_dataflash(CONFIG_ENV_ADDR + index + offsetof(env_t,data), - 1, (char *)&c); + 1, (char *)&c); return (c); } -void env_relocate_spec (void) +void env_relocate_spec(void) { - read_dataflash(CONFIG_ENV_ADDR, CONFIG_ENV_SIZE, (char *)env_ptr); + char buf[CONFIG_ENV_SIZE]; + + read_dataflash(CONFIG_ENV_ADDR, CONFIG_ENV_SIZE, buf); + + env_import(buf, 1); } +#ifdef CONFIG_ENV_OFFSET_REDUND +#error No support for redundant environment on dataflash yet! +#endif + int saveenv(void) { - /* env must be copied to do not alter env structure in memory*/ - unsigned char temp[CONFIG_ENV_SIZE]; - memcpy(temp, env_ptr, CONFIG_ENV_SIZE); - return write_dataflash(CONFIG_ENV_ADDR, (unsigned long)temp, CONFIG_ENV_SIZE); + env_t env_new; + ssize_t len; + char *res; + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + + return write_dataflash(CONFIG_ENV_ADDR, + (unsigned long)&env_new, + CONFIG_ENV_SIZE); } -/************************************************************************ - * Initialize Environment use +/* + * Initialize environment use * - * We are still running from ROM, so data use is limited + * We are still running from ROM, so data use is limited. * Use a (moderately small) buffer on the stack */ int env_init(void) @@ -69,30 +91,36 @@ int env_init(void) ulong crc, len, new; unsigned off; uchar buf[64]; - if (gd->env_valid == 0){ - AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */ - - /* read old CRC */ - read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc), - sizeof(ulong), (char *)&crc); - new = 0; - len = ENV_SIZE; - off = offsetof(env_t,data); - while (len > 0) { - int n = (len > sizeof(buf)) ? sizeof(buf) : len; - read_dataflash(CONFIG_ENV_ADDR + off, n, (char *)buf); - new = crc32 (new, buf, n); - len -= n; - off += n; - } - if (crc == new) { - gd->env_addr = offsetof(env_t,data); - gd->env_valid = 1; - } else { - gd->env_addr = (ulong)&default_environment[0]; - gd->env_valid = 0; - } + + if (gd->env_valid) + return 0; + + AT91F_DataflashInit(); /* prepare for DATAFLASH read/write */ + + /* read old CRC */ + read_dataflash(CONFIG_ENV_ADDR + offsetof(env_t, crc), + sizeof(ulong), (char *)&crc); + + new = 0; + len = ENV_SIZE; + off = offsetof(env_t,data); + while (len > 0) { + int n = (len > sizeof(buf)) ? sizeof(buf) : len; + + read_dataflash(CONFIG_ENV_ADDR + off, n, (char *)buf); + + new = crc32 (new, buf, n); + len -= n; + off += n; + } + + if (crc == new) { + gd->env_addr = offsetof(env_t,data); + gd->env_valid = 1; + } else { + gd->env_addr = (ulong)&default_environment[0]; + gd->env_valid = 0; } - return (0); + return 0; } diff --git a/common/env_eeprom.c b/common/env_eeprom.c index 8fe59f8..792b44f 100644 --- a/common/env_eeprom.c +++ b/common/env_eeprom.c @@ -1,10 +1,10 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Andreas Heppel <aheppel@sysgo.de> - + * * See file CREDITS for list of people who contributed to this * project. * @@ -31,16 +31,19 @@ #if defined(CONFIG_I2C_ENV_EEPROM_BUS) #include <i2c.h> #endif +#include <search.h> +#include <errno.h> +#include <linux/compiler.h> /* for BUG_ON */ DECLARE_GLOBAL_DATA_PTR; env_t *env_ptr = NULL; -char * env_name_spec = "EEPROM"; +char *env_name_spec = "EEPROM"; int env_eeprom_bus = -1; -static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) +static int eeprom_bus_read(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { int rcode; #if defined(CONFIG_I2C_ENV_EEPROM_BUS) @@ -51,9 +54,9 @@ static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer, I2C_MUX_DEVICE *dev = NULL; dev = i2c_mux_ident_muxstring( (uchar *)CONFIG_I2C_ENV_EEPROM_BUS); - if (dev != NULL) { + if (dev != NULL) env_eeprom_bus = dev->busid; - } else + else printf ("error adding env eeprom bus.\n"); } if (old_bus != env_eeprom_bus) { @@ -67,6 +70,7 @@ static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer, #endif rcode = eeprom_read (dev_addr, offset, buffer, cnt); + #if defined(CONFIG_I2C_ENV_EEPROM_BUS) if (old_bus != env_eeprom_bus) i2c_set_bus_num(old_bus); @@ -74,8 +78,8 @@ static int eeprom_bus_read (unsigned dev_addr, unsigned offset, uchar *buffer, return rcode; } -static int eeprom_bus_write (unsigned dev_addr, unsigned offset, uchar *buffer, - unsigned cnt) +static int eeprom_bus_write(unsigned dev_addr, unsigned offset, + uchar *buffer, unsigned cnt) { int rcode; #if defined(CONFIG_I2C_ENV_EEPROM_BUS) @@ -83,7 +87,7 @@ static int eeprom_bus_write (unsigned dev_addr, unsigned offset, uchar *buffer, rcode = i2c_mux_ident_muxstring_f((uchar *)CONFIG_I2C_ENV_EEPROM_BUS); #endif - rcode = eeprom_write (dev_addr, offset, buffer, cnt); + rcode = eeprom_write(dev_addr, offset, buffer, cnt); #if defined(CONFIG_I2C_ENV_EEPROM_BUS) i2c_set_bus_num(old_bus); #endif @@ -95,12 +99,12 @@ uchar env_get_char_spec (int index) uchar c; unsigned int off; off = CONFIG_ENV_OFFSET; + #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == 2) off = CONFIG_ENV_OFFSET_REDUND; #endif - - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off + index + offsetof(env_t,data), &c, 1); @@ -109,40 +113,60 @@ uchar env_get_char_spec (int index) void env_relocate_spec (void) { + char buf[CONFIG_ENV_SIZE]; unsigned int off = CONFIG_ENV_OFFSET; + #ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == 2) off = CONFIG_ENV_OFFSET_REDUND; #endif - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off, - (uchar*)env_ptr, + (uchar *)buf, CONFIG_ENV_SIZE); + + env_import(buf, 1); } int saveenv(void) { + env_t env_new; + ssize_t len; + char *res; int rc; unsigned int off = CONFIG_ENV_OFFSET; #ifdef CONFIG_ENV_OFFSET_REDUND unsigned int off_red = CONFIG_ENV_OFFSET_REDUND; char flag_obsolete = OBSOLETE_FLAG; +#endif + + BUG_ON(env_ptr != NULL); + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + +#ifdef CONFIG_ENV_OFFSET_REDUND if (gd->env_valid == 1) { off = CONFIG_ENV_OFFSET_REDUND; off_red = CONFIG_ENV_OFFSET; } - env_ptr->flags = ACTIVE_FLAG; + env_new.flags = ACTIVE_FLAG; #endif - rc = eeprom_bus_write (CONFIG_SYS_DEF_EEPROM_ADDR, + rc = eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, off, - (uchar *)env_ptr, + (uchar *)&env_new, CONFIG_ENV_SIZE); #ifdef CONFIG_ENV_OFFSET_REDUND if (rc == 0) { - eeprom_bus_write (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_write(CONFIG_SYS_DEF_EEPROM_ADDR, off_red + offsetof(env_t,flags), (uchar *)&flag_obsolete, 1); @@ -157,10 +181,10 @@ int saveenv(void) return rc; } -/************************************************************************ +/* * Initialize Environment use * - * We are still running from ROM, so data use is limited + * We are still running from ROM, so data use is limited. * Use a (moderately small) buffer on the stack */ @@ -175,31 +199,31 @@ int env_init(void) unsigned char flags[2]; int i; - eeprom_init (); /* prepare for EEPROM read/write */ + eeprom_init(); /* prepare for EEPROM read/write */ off_env[0] = CONFIG_ENV_OFFSET; off_env[1] = CONFIG_ENV_OFFSET_REDUND; for (i = 0; i < 2; i++) { /* read CRC */ - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off_env[i] + offsetof(env_t,crc), (uchar *)&crc[i], sizeof(ulong)); /* read FLAGS */ - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off_env[i] + offsetof(env_t,flags), (uchar *)&flags[i], sizeof(uchar)); - crc_tmp= 0; + crc_tmp = 0; len = ENV_SIZE; off = off_env[i] + offsetof(env_t,data); while (len > 0) { int n = (len > sizeof(buf)) ? sizeof(buf) : len; - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, off, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, off, buf, n); - crc_tmp = crc32 (crc_tmp, buf, n); + crc_tmp = crc32(crc_tmp, buf, n); len -= n; off += n; } @@ -245,22 +269,23 @@ int env_init(void) unsigned off; uchar buf[64]; - eeprom_init (); /* prepare for EEPROM read/write */ + eeprom_init(); /* prepare for EEPROM read/write */ /* read old CRC */ - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET+offsetof(env_t,crc), (uchar *)&crc, sizeof(ulong)); new = 0; len = ENV_SIZE; off = offsetof(env_t,data); + while (len > 0) { int n = (len > sizeof(buf)) ? sizeof(buf) : len; - eeprom_bus_read (CONFIG_SYS_DEF_EEPROM_ADDR, + eeprom_bus_read(CONFIG_SYS_DEF_EEPROM_ADDR, CONFIG_ENV_OFFSET + off, buf, n); - new = crc32 (new, buf, n); + new = crc32(new, buf, n); len -= n; off += n; } diff --git a/common/env_flash.c b/common/env_flash.c index 925c5a0..1da78b7 100644 --- a/common/env_flash.c +++ b/common/env_flash.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -31,6 +31,8 @@ #include <environment.h> #include <linux/stddef.h> #include <malloc.h> +#include <search.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -51,36 +53,38 @@ char * env_name_spec = "Flash"; extern uchar environment[]; env_t *env_ptr = (env_t *)(&environment[0]); -#ifdef CMD_SAVEENV -/* static env_t *flash_addr = (env_t *)(&environment[0]);-broken on ARM-wd-*/ static env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; -#endif #else /* ! ENV_IS_EMBEDDED */ env_t *env_ptr = (env_t *)CONFIG_ENV_ADDR; -#ifdef CMD_SAVEENV static env_t *flash_addr = (env_t *)CONFIG_ENV_ADDR; -#endif #endif /* ENV_IS_EMBEDDED */ +#if defined(CMD_SAVEENV) || defined(CONFIG_ENV_ADDR_REDUND) +/* CONFIG_ENV_ADDR is supposed to be on sector boundary */ +static ulong end_addr = CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1; +#endif + #ifdef CONFIG_ENV_ADDR_REDUND static env_t *flash_addr_new = (env_t *)CONFIG_ENV_ADDR_REDUND; -/* CONFIG_ENV_ADDR is supposed to be on sector boundary */ -static ulong end_addr = CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE - 1; +/* CONFIG_ENV_ADDR_REDUND is supposed to be on sector boundary */ static ulong end_addr_new = CONFIG_ENV_ADDR_REDUND + CONFIG_ENV_SECT_SIZE - 1; #endif /* CONFIG_ENV_ADDR_REDUND */ extern uchar default_environment[]; -uchar env_get_char_spec (int index) +uchar env_get_char_spec(int index) { - return ( *((uchar *)(gd->env_addr + index)) ); + return (*((uchar *)(gd->env_addr + index))); } +#undef debug +#define debug printf + #ifdef CONFIG_ENV_ADDR_REDUND int env_init(void) @@ -123,91 +127,97 @@ int env_init(void) gd->env_valid = 2; } - return (0); + return 0; } #ifdef CMD_SAVEENV int saveenv(void) { - char *saved_data = NULL; - int rc = 1; - char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; + env_t env_new; + ssize_t len; + char *saved_data = NULL; + char *res; + int rc = 1; + char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE - ulong up_data = 0; + ulong up_data = 0; #endif - debug ("Protect off %08lX ... %08lX\n", + debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr, end_addr); - if (flash_sect_protect (0, (ulong)flash_addr, end_addr)) { - goto Done; + if (flash_sect_protect(0, (ulong)flash_addr, end_addr)) { + goto done; } - debug ("Protect off %08lX ... %08lX\n", + debug("Protect off %08lX ... %08lX\n", (ulong)flash_addr_new, end_addr_new); - if (flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new)) { - goto Done; + if (flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new)) { + goto done; + } + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + goto done; } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_new.flags = new_flag; #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE up_data = (end_addr_new + 1 - ((long)flash_addr_new + CONFIG_ENV_SIZE)); - debug ("Data to save 0x%x\n", up_data); + debug("Data to save 0x%lX\n", up_data); if (up_data) { if ((saved_data = malloc(up_data)) == NULL) { printf("Unable to save the rest of sector (%ld)\n", up_data); - goto Done; + goto done; } memcpy(saved_data, (void *)((long)flash_addr_new + CONFIG_ENV_SIZE), up_data); - debug ("Data (start 0x%x, len 0x%x) saved at 0x%x\n", - (long)flash_addr_new + CONFIG_ENV_SIZE, - up_data, saved_data); + debug("Data (start 0x%lX, len 0x%lX) saved at 0x%p\n", + (long)flash_addr_new + CONFIG_ENV_SIZE, + up_data, saved_data); } #endif - puts ("Erasing Flash..."); - debug (" %08lX ... %08lX ...", + puts("Erasing Flash..."); + debug(" %08lX ... %08lX ...", (ulong)flash_addr_new, end_addr_new); - if (flash_sect_erase ((ulong)flash_addr_new, end_addr_new)) { - goto Done; + if (flash_sect_erase((ulong)flash_addr_new, end_addr_new)) { + goto done; } - puts ("Writing to Flash... "); - debug (" %08lX ... %08lX ...", + puts("Writing to Flash... "); + debug(" %08lX ... %08lX ...", (ulong)&(flash_addr_new->data), sizeof(env_ptr->data)+(ulong)&(flash_addr_new->data)); - if ((rc = flash_write((char *)env_ptr->data, - (ulong)&(flash_addr_new->data), - sizeof(env_ptr->data))) || - (rc = flash_write((char *)&(env_ptr->crc), - (ulong)&(flash_addr_new->crc), - sizeof(env_ptr->crc))) || + if ((rc = flash_write((char *)&env_new, + (ulong)flash_addr_new, + sizeof(env_new))) || (rc = flash_write(&flag, (ulong)&(flash_addr->flags), - sizeof(flash_addr->flags))) || - (rc = flash_write(&new_flag, - (ulong)&(flash_addr_new->flags), - sizeof(flash_addr_new->flags)))) - { - flash_perror (rc); - goto Done; + sizeof(flash_addr->flags))) ) { + flash_perror(rc); + goto done; } - puts ("done\n"); #if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE if (up_data) { /* restore the rest of sector */ - debug ("Restoring the rest of data to 0x%x len 0x%x\n", - (long)flash_addr_new + CONFIG_ENV_SIZE, up_data); + debug("Restoring the rest of data to 0x%lX len 0x%lX\n", + (long)flash_addr_new + CONFIG_ENV_SIZE, up_data); if (flash_write(saved_data, (long)flash_addr_new + CONFIG_ENV_SIZE, up_data)) { flash_perror(rc); - goto Done; + goto done; } } #endif + puts("done\n"); + { env_t * etmp = flash_addr; ulong ltmp = end_addr; @@ -220,13 +230,12 @@ int saveenv(void) } rc = 0; -Done: - +done: if (saved_data) - free (saved_data); + free(saved_data); /* try to re-protect */ - (void) flash_sect_protect (1, (ulong)flash_addr, end_addr); - (void) flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new); + (void) flash_sect_protect(1, (ulong)flash_addr, end_addr); + (void) flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new); return rc; } @@ -244,83 +253,93 @@ int env_init(void) gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 0; - return (0); + return 0; } #ifdef CMD_SAVEENV int saveenv(void) { - int len, rc; - ulong end_addr; - ulong flash_sect_addr; -#if defined(CONFIG_ENV_SECT_SIZE) && (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) - ulong flash_offset; - uchar env_buffer[CONFIG_ENV_SECT_SIZE]; -#else - uchar *env_buffer = (uchar *)env_ptr; -#endif /* CONFIG_ENV_SECT_SIZE */ - int rcode = 0; - -#if defined(CONFIG_ENV_SECT_SIZE) && (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) - - flash_offset = ((ulong)flash_addr) & (CONFIG_ENV_SECT_SIZE-1); - flash_sect_addr = ((ulong)flash_addr) & ~(CONFIG_ENV_SECT_SIZE-1); - - debug ( "copy old content: " - "sect_addr: %08lX env_addr: %08lX offset: %08lX\n", - flash_sect_addr, (ulong)flash_addr, flash_offset); - - /* copy old contents to temporary buffer */ - memcpy (env_buffer, (void *)flash_sect_addr, CONFIG_ENV_SECT_SIZE); - - /* copy current environment to temporary buffer */ - memcpy ((uchar *)((unsigned long)env_buffer + flash_offset), - env_ptr, - CONFIG_ENV_SIZE); + env_t env_new; + ssize_t len; + int rc = 1; + char *res; + char *saved_data = NULL; +#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE + ulong up_data = 0; - len = CONFIG_ENV_SECT_SIZE; -#else - flash_sect_addr = (ulong)flash_addr; - len = CONFIG_ENV_SIZE; + up_data = (end_addr + 1 - ((long)flash_addr + CONFIG_ENV_SIZE)); + debug("Data to save 0x%lx\n", up_data); + if (up_data) { + if ((saved_data = malloc(up_data)) == NULL) { + printf("Unable to save the rest of sector (%ld)\n", + up_data); + goto done; + } + memcpy(saved_data, + (void *)((long)flash_addr + CONFIG_ENV_SIZE), up_data); + debug("Data (start 0x%lx, len 0x%lx) saved at 0x%lx\n", + (ulong)flash_addr + CONFIG_ENV_SIZE, + up_data, + (ulong)saved_data); + } #endif /* CONFIG_ENV_SECT_SIZE */ - end_addr = flash_sect_addr + len - 1; + debug("Protect off %08lX ... %08lX\n", + (ulong)flash_addr, end_addr); - debug ("Protect off %08lX ... %08lX\n", - (ulong)flash_sect_addr, end_addr); + if (flash_sect_protect(0, (long)flash_addr, end_addr)) + goto done; - if (flash_sect_protect (0, flash_sect_addr, end_addr)) - return 1; + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + goto done; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); - puts ("Erasing Flash..."); - if (flash_sect_erase (flash_sect_addr, end_addr)) - return 1; + puts("Erasing Flash..."); + if (flash_sect_erase((long)flash_addr, end_addr)) + goto done; - puts ("Writing to Flash... "); - rc = flash_write((char *)env_buffer, flash_sect_addr, len); + puts("Writing to Flash... "); + rc = flash_write((char *)&env_new, (long)flash_addr, CONFIG_ENV_SIZE); if (rc != 0) { - flash_perror (rc); - rcode = 1; - } else { - puts ("done\n"); + flash_perror(rc); + goto done; } - +#if CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE + if (up_data) { /* restore the rest of sector */ + debug("Restoring the rest of data to 0x%lx len 0x%lx\n", + (ulong)flash_addr + CONFIG_ENV_SIZE, up_data); + if (flash_write(saved_data, + (long)flash_addr + CONFIG_ENV_SIZE, + up_data)) { + flash_perror(rc); + goto done; + } + } +#endif + puts("done\n"); + rc = 0; +done: + if (saved_data) + free(saved_data); /* try to re-protect */ - (void) flash_sect_protect (1, flash_sect_addr, end_addr); - return rcode; + (void) flash_sect_protect(1, (long)flash_addr, end_addr); + return rc; } #endif /* CMD_SAVEENV */ #endif /* CONFIG_ENV_ADDR_REDUND */ -void env_relocate_spec (void) +void env_relocate_spec(void) { -#if !defined(ENV_IS_EMBEDDED) || defined(CONFIG_ENV_ADDR_REDUND) #ifdef CONFIG_ENV_ADDR_REDUND if (gd->env_addr != (ulong)&(flash_addr->data)) { - env_t * etmp = flash_addr; + env_t *etmp = flash_addr; ulong ltmp = end_addr; flash_addr = flash_addr_new; @@ -336,11 +355,11 @@ void env_relocate_spec (void) char flag = OBSOLETE_FLAG; gd->env_valid = 2; - flash_sect_protect (0, (ulong)flash_addr_new, end_addr_new); + flash_sect_protect(0, (ulong)flash_addr_new, end_addr_new); flash_write(&flag, (ulong)&(flash_addr_new->flags), sizeof(flash_addr_new->flags)); - flash_sect_protect (1, (ulong)flash_addr_new, end_addr_new); + flash_sect_protect(1, (ulong)flash_addr_new, end_addr_new); } if (flash_addr->flags != ACTIVE_FLAG && @@ -348,19 +367,17 @@ void env_relocate_spec (void) char flag = ACTIVE_FLAG; gd->env_valid = 2; - flash_sect_protect (0, (ulong)flash_addr, end_addr); + flash_sect_protect(0, (ulong)flash_addr, end_addr); flash_write(&flag, (ulong)&(flash_addr->flags), sizeof(flash_addr->flags)); - flash_sect_protect (1, (ulong)flash_addr, end_addr); + flash_sect_protect(1, (ulong)flash_addr, end_addr); } if (gd->env_valid == 2) puts ("*** Warning - some problems detected " "reading environment; recovered successfully\n\n"); #endif /* CONFIG_ENV_ADDR_REDUND */ -#ifdef CMD_SAVEENV - memcpy (env_ptr, (void*)flash_addr, CONFIG_ENV_SIZE); -#endif -#endif /* ! ENV_IS_EMBEDDED || CONFIG_ENV_ADDR_REDUND */ + + env_import((char *)flash_addr, 1); } diff --git a/common/env_mgdisk.c b/common/env_mgdisk.c index b9de1ed..a69923b 100644 --- a/common/env_mgdisk.c +++ b/common/env_mgdisk.c @@ -30,7 +30,7 @@ /* references to names in env_common.c */ extern uchar default_environment[]; -char * env_name_spec = "MG_DISK"; +char *env_name_spec = "MG_DISK"; env_t *env_ptr = 0; @@ -38,34 +38,27 @@ DECLARE_GLOBAL_DATA_PTR; uchar env_get_char_spec(int index) { - return (*((uchar *) (gd->env_addr + index))); + return (*((uchar *)(gd->env_addr + index))); } void env_relocate_spec(void) { - unsigned int err; + char buf[CONFIG_ENV_SIZE]; + unsigned int err, rc; err = mg_disk_init(); if (err) { - puts ("*** Warning - mg_disk_init error"); - goto OUT; - } - err = mg_disk_read(CONFIG_ENV_ADDR, (u_char *)env_ptr, CONFIG_ENV_SIZE); - if (err) { - puts ("*** Warning - mg_disk_read error"); - goto OUT; + set_default_env("!mg_disk_init error"); + return; } - if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) { - puts ("*** Warning - CRC error"); - goto OUT; + err = mg_disk_read(CONFIG_ENV_ADDR, buf, CONFIG_ENV_SIZE); + if (err) { + set_default_env("!mg_disk_read error"); + return; } - return; - -OUT: - printf (", using default environment\n\n"); - set_default_env(); + env_import(buf, 1); } int saveenv(void) @@ -76,7 +69,7 @@ int saveenv(void) err = mg_disk_write(CONFIG_ENV_ADDR, (u_char *)env_ptr, CONFIG_ENV_SIZE); if (err) - puts ("*** Warning - mg_disk_write error\n\n"); + puts("*** Warning - mg_disk_write error\n\n"); return err; } @@ -84,7 +77,7 @@ int saveenv(void) int env_init(void) { /* use default */ - gd->env_addr = (ulong) & default_environment[0]; + gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 1; return 0; diff --git a/common/env_nand.c b/common/env_nand.c index d38bcca..4e8307a 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -1,16 +1,16 @@ /* + * (C) Copyright 2000-2010 + * Wolfgang Denk, DENX Software Engineering, wd@denx.de. + * * (C) Copyright 2008 * Stuart Wood, Lab X Technologies <stuart.wood@labxtechnologies.com> * * (C) Copyright 2004 * Jian Zhang, Texas Instruments, jzhang@ti.com. - - * (C) Copyright 2000-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Andreas Heppel <aheppel@sysgo.de> - + * * See file CREDITS for list of people who contributed to this * project. * @@ -30,7 +30,7 @@ * MA 02111-1307 USA */ -/* #define DEBUG */ +#define DEBUG #include <common.h> #include <command.h> @@ -38,7 +38,8 @@ #include <linux/stddef.h> #include <malloc.h> #include <nand.h> -#include <asm/errno.h> +#include <search.h> +#include <errno.h> #if defined(CONFIG_CMD_SAVEENV) && defined(CONFIG_CMD_NAND) #define CMD_SAVEENV @@ -57,7 +58,7 @@ /* references to names in env_common.c */ extern uchar default_environment[]; -char * env_name_spec = "NAND"; +char *env_name_spec = "NAND"; #if defined(ENV_IS_EMBEDDED) @@ -69,12 +70,6 @@ env_t *env_ptr = (env_t *)CONFIG_NAND_ENV_DST; env_t *env_ptr = 0; #endif /* ENV_IS_EMBEDDED */ - -/* local functions */ -#if !defined(ENV_IS_EMBEDDED) -static void use_default(void); -#endif - DECLARE_GLOBAL_DATA_PTR; uchar env_get_char_spec (int index) @@ -82,17 +77,17 @@ uchar env_get_char_spec (int index) return ( *((uchar *)(gd->env_addr + index)) ); } - -/* this is called before nand_init() - * so we can't read Nand to validate env data. - * Mark it OK for now. env_relocate() in env_common.c - * will call our relocate function which does the real - * validation. +/* + * This is called before nand_init() so we can't read NAND to + * validate env data. + * + * Mark it OK for now. env_relocate() in env_common.c will call our + * relocate function which does the real validation. * * When using a NAND boot image (like sequoia_nand), the environment - * can be embedded or attached to the U-Boot image in NAND flash. This way - * the SPL loads not only the U-Boot image from NAND but also the - * environment. + * can be embedded or attached to the U-Boot image in NAND flash. + * This way the SPL loads not only the U-Boot image from NAND but + * also the environment. */ int env_init(void) { @@ -189,11 +184,12 @@ int writeenv(size_t offset, u_char *buf) #ifdef CONFIG_ENV_OFFSET_REDUND int saveenv(void) { - int ret = 0; + env_t env_new; + ssize_t len; + char *res; + int ret = 0; nand_erase_options_t nand_erase_options; - env_ptr->flags++; - nand_erase_options.length = CONFIG_ENV_RANGE; nand_erase_options.quiet = 0; nand_erase_options.jffs2 = 0; @@ -201,36 +197,53 @@ int saveenv(void) if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) return 1; + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_new.flags = ACTIVE_FLAG; + if(gd->env_valid == 1) { - puts ("Erasing redundant Nand...\n"); + puts("Erasing redundant NAND...\n"); nand_erase_options.offset = CONFIG_ENV_OFFSET_REDUND; if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; - puts ("Writing to redundant Nand... "); - ret = writeenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) env_ptr); + puts("Writing to redundant NAND... "); + ret = writeenv(CONFIG_ENV_OFFSET_REDUND, + (u_char *)&env_new); } else { - puts ("Erasing Nand...\n"); + puts("Erasing NAND...\n"); nand_erase_options.offset = CONFIG_ENV_OFFSET; if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; - puts ("Writing to Nand... "); - ret = writeenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr); + puts("Writing to NAND... "); + ret = writeenv(CONFIG_ENV_OFFSET, + (u_char *)&env_new); } if (ret) { puts("FAILED!\n"); return 1; } - puts ("done\n"); + puts("done\n"); + gd->env_valid = (gd->env_valid == 2 ? 1 : 2); + return ret; } #else /* ! CONFIG_ENV_OFFSET_REDUND */ int saveenv(void) { int ret = 0; + env_t env_new; + ssize_t len; + char *res; nand_erase_options_t nand_erase_options; nand_erase_options.length = CONFIG_ENV_RANGE; @@ -241,23 +254,32 @@ int saveenv(void) if (CONFIG_ENV_RANGE < CONFIG_ENV_SIZE) return 1; - puts ("Erasing Nand...\n"); + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + + puts("Erasing Nand...\n"); if (nand_erase_opts(&nand_info[0], &nand_erase_options)) return 1; - puts ("Writing to Nand... "); - if (writeenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr)) { + puts("Writing to Nand... "); + if (writeenv(CONFIG_ENV_OFFSET, (u_char *)&env_new)) { puts("FAILED!\n"); return 1; } - puts ("done\n"); + puts("done\n"); return ret; } #endif /* CONFIG_ENV_OFFSET_REDUND */ #endif /* CMD_SAVEENV */ -int readenv (size_t offset, u_char * buf) +int readenv(size_t offset, u_char * buf) { size_t end = offset + CONFIG_ENV_RANGE; size_t amount_loaded = 0; @@ -320,47 +342,50 @@ int get_nand_env_oob(nand_info_t *nand, unsigned long *result) #endif #ifdef CONFIG_ENV_OFFSET_REDUND -void env_relocate_spec (void) +void env_relocate_spec(void) { #if !defined(ENV_IS_EMBEDDED) int crc1_ok = 0, crc2_ok = 0; - env_t *tmp_env1, *tmp_env2; + env_t *ep, *tmp_env1, *tmp_env2; - tmp_env1 = (env_t *) malloc(CONFIG_ENV_SIZE); - tmp_env2 = (env_t *) malloc(CONFIG_ENV_SIZE); + tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE); + tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE); if ((tmp_env1 == NULL) || (tmp_env2 == NULL)) { puts("Can't allocate buffers for environment\n"); - free (tmp_env1); - free (tmp_env2); - return use_default(); + free(tmp_env1); + free(tmp_env2); + set_default_env("!malloc() failed"); + return; } if (readenv(CONFIG_ENV_OFFSET, (u_char *) tmp_env1)) - puts("No Valid Environment Area Found\n"); + puts("No Valid Environment Area found\n"); + if (readenv(CONFIG_ENV_OFFSET_REDUND, (u_char *) tmp_env2)) - puts("No Valid Reundant Environment Area Found\n"); + puts("No Valid Redundant Environment Area found\n"); crc1_ok = (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc); crc2_ok = (crc32(0, tmp_env2->data, ENV_SIZE) == tmp_env2->crc); - if(!crc1_ok && !crc2_ok) { + if (!crc1_ok && !crc2_ok) { free(tmp_env1); free(tmp_env2); - return use_default(); - } else if(crc1_ok && !crc2_ok) + set_default_env("!bad CRC"); + return; + } else if (crc1_ok && !crc2_ok) { gd->env_valid = 1; - else if(!crc1_ok && crc2_ok) + } else if (!crc1_ok && crc2_ok) { gd->env_valid = 2; - else { + } else { /* both ok - check serial */ - if(tmp_env1->flags == 255 && tmp_env2->flags == 0) + if (tmp_env1->flags == 255 && tmp_env2->flags == 0) gd->env_valid = 2; - else if(tmp_env2->flags == 255 && tmp_env1->flags == 0) + else if (tmp_env2->flags == 255 && tmp_env1->flags == 0) gd->env_valid = 1; - else if(tmp_env1->flags > tmp_env2->flags) + else if (tmp_env1->flags > tmp_env2->flags) gd->env_valid = 1; - else if(tmp_env2->flags > tmp_env1->flags) + else if (tmp_env2->flags > tmp_env1->flags) gd->env_valid = 2; else /* flags are equal - almost impossible */ gd->env_valid = 1; @@ -368,51 +393,52 @@ void env_relocate_spec (void) } free(env_ptr); - if(gd->env_valid == 1) { - env_ptr = tmp_env1; - free(tmp_env2); - } else { - env_ptr = tmp_env2; - free(tmp_env1); - } + + if (gd->env_valid == 1) + ep = tmp_env1; + else + ep = tmp_env2; + + env_import((char *)ep, 0); + + free(tmp_env1); + free(tmp_env2); #endif /* ! ENV_IS_EMBEDDED */ } #else /* ! CONFIG_ENV_OFFSET_REDUND */ /* - * The legacy NAND code saved the environment in the first NAND device i.e., - * nand_dev_desc + 0. This is also the behaviour using the new NAND code. + * The legacy NAND code saved the environment in the first NAND + * device i.e., nand_dev_desc + 0. This is also the behaviour using + * the new NAND code. */ void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) int ret; + char buf[CONFIG_ENV_SIZE]; #if defined(CONFIG_ENV_OFFSET_OOB) ret = get_nand_env_oob(&nand_info[0], &nand_env_oob_offset); - /* If unable to read environment offset from NAND OOB then fall through + /* + * If unable to read environment offset from NAND OOB then fall through * to the normal environment reading code below */ - if (!ret) + if (!ret) { printf("Found Environment offset in OOB..\n"); - else - return use_default(); + } else { + set_default_env("!no env offset in OOB"); + return; + } #endif - ret = readenv(CONFIG_ENV_OFFSET, (u_char *) env_ptr); - if (ret) - return use_default(); + ret = readenv(CONFIG_ENV_OFFSET, (u_char *)buf); + if (ret) { + set_default_env("!readenv() failed"); + return; + } - if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) - return use_default(); + env_import(buf, 1); #endif /* ! ENV_IS_EMBEDDED */ } #endif /* CONFIG_ENV_OFFSET_REDUND */ - -#if !defined(ENV_IS_EMBEDDED) -static void use_default() -{ - puts ("*** Warning - bad CRC or NAND, using default environment\n\n"); - set_default_env(); -} -#endif diff --git a/common/env_nowhere.c b/common/env_nowhere.c index ccc068b..75ef78d 100644 --- a/common/env_nowhere.c +++ b/common/env_nowhere.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -35,22 +35,21 @@ env_t *env_ptr = NULL; extern uchar default_environment[]; - -void env_relocate_spec (void) +void env_relocate_spec(void) { } -uchar env_get_char_spec (int index) +uchar env_get_char_spec(int index) { return ( *((uchar *)(gd->env_addr + index)) ); } -/************************************************************************ +/* * Initialize Environment use * * We are still running from ROM, so data use is limited */ -int env_init(void) +int env_init(void) { gd->env_addr = (ulong)&default_environment[0]; gd->env_valid = 0; diff --git a/common/env_nvram.c b/common/env_nvram.c index 7c7cf98..6e90f2b 100644 --- a/common/env_nvram.c +++ b/common/env_nvram.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -44,6 +44,8 @@ #include <command.h> #include <environment.h> #include <linux/stddef.h> +#include <search.h> +#include <errno.h> DECLARE_GLOBAL_DATA_PTR; @@ -59,7 +61,7 @@ char * env_name_spec = "NVRAM"; extern uchar default_environment[]; -uchar env_get_char_spec (int index) +uchar env_get_char_spec(int index) { #ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE uchar c; @@ -72,40 +74,56 @@ uchar env_get_char_spec (int index) #endif } -void env_relocate_spec (void) +void env_relocate_spec(void) { + char buf[CONFIG_ENV_SIZE]; + #if defined(CONFIG_SYS_NVRAM_ACCESS_ROUTINE) - nvram_read(env_ptr, CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); + nvram_read(buf, CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); #else - memcpy (env_ptr, (void*)CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); + memcpy(buf, (void*)CONFIG_ENV_ADDR, CONFIG_ENV_SIZE); #endif + env_import(buf, 1); } -int saveenv (void) +int saveenv(void) { - int rcode = 0; + env_t env_new; + ssize_t len; + char *res; + int rcode = 0; + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + #ifdef CONFIG_SYS_NVRAM_ACCESS_ROUTINE - nvram_write(CONFIG_ENV_ADDR, env_ptr, CONFIG_ENV_SIZE); + nvram_write(CONFIG_ENV_ADDR, &env_new, CONFIG_ENV_SIZE); #else - if (memcpy ((char *)CONFIG_ENV_ADDR, env_ptr, CONFIG_ENV_SIZE) == NULL) - rcode = 1 ; + if (memcpy((char *)CONFIG_ENV_ADDR, &env_new, CONFIG_ENV_SIZE) == NULL) + rcode = 1; #endif return rcode; } -/************************************************************************ +/* * Initialize Environment use * * We are still running from ROM, so data use is limited */ -int env_init (void) +int env_init(void) { #if defined(CONFIG_SYS_NVRAM_ACCESS_ROUTINE) ulong crc; uchar data[ENV_SIZE]; - nvram_read (&crc, CONFIG_ENV_ADDR, sizeof(ulong)); - nvram_read (data, CONFIG_ENV_ADDR+sizeof(ulong), ENV_SIZE); + + nvram_read(&crc, CONFIG_ENV_ADDR, sizeof(ulong)); + nvram_read(data, CONFIG_ENV_ADDR+sizeof(ulong), ENV_SIZE); if (crc32(0, data, ENV_SIZE) == crc) { gd->env_addr = (ulong)CONFIG_ENV_ADDR + sizeof(long); diff --git a/common/env_onenand.c b/common/env_onenand.c index cf997bf..02cb535 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -1,4 +1,7 @@ /* + * (C) Copyright 2010 DENX Software Engineering + * Wolfgang Denk <wd@denx.de> + * * (C) Copyright 2005-2009 Samsung Electronics * Kyungmin Park <kyungmin.park@samsung.com> * @@ -26,6 +29,8 @@ #include <environment.h> #include <linux/stddef.h> #include <malloc.h> +#include <search.h> +#include <errno.h> #include <linux/mtd/compat.h> #include <linux/mtd/mtd.h> @@ -44,17 +49,13 @@ char *env_name_spec = "OneNAND"; #ifdef ENV_IS_EMBEDDED extern uchar environment[]; -env_t *env_ptr = (env_t *) (&environment[0]); -#else /* ! ENV_IS_EMBEDDED */ -static unsigned char onenand_env[ONENAND_MAX_ENV_SIZE]; -env_t *env_ptr = (env_t *) onenand_env; #endif /* ENV_IS_EMBEDDED */ DECLARE_GLOBAL_DATA_PTR; uchar env_get_char_spec(int index) { - return (*((uchar *) (gd->env_addr + index))); + return (*((uchar *)(gd->env_addr + index))); } void env_relocate_spec(void) @@ -63,48 +64,57 @@ void env_relocate_spec(void) #ifdef CONFIG_ENV_ADDR_FLEX struct onenand_chip *this = &onenand_chip; #endif - loff_t env_addr; - int use_default = 0; + int rc; size_t retlen; +#ifdef ENV_IS_EMBEDDED + char *buf = (char *)&environment[0]; +#else + loff_t env_addr = CONFIG_ENV_ADDR; + char onenand_env[ONENAND_MAX_ENV_SIZE]; + char *buf = (char *)&onenand_env[0]; +#endif /* ENV_IS_EMBEDDED */ - env_addr = CONFIG_ENV_ADDR; -#ifdef CONFIG_ENV_ADDR_FLEX +#ifndef ENV_IS_EMBEDDED +# ifdef CONFIG_ENV_ADDR_FLEX if (FLEXONENAND(this)) env_addr = CONFIG_ENV_ADDR_FLEX; -#endif +# endif /* Check OneNAND exist */ if (mtd->writesize) /* Ignore read fail */ mtd->read(mtd, env_addr, ONENAND_MAX_ENV_SIZE, - &retlen, (u_char *) env_ptr); + &retlen, (u_char *)buf); else mtd->writesize = MAX_ONENAND_PAGESIZE; +#endif /* !ENV_IS_EMBEDDED */ - if (crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd)) != env_ptr->crc) - use_default = 1; - - if (use_default) { - memcpy(env_ptr->data, default_environment, - ONENAND_ENV_SIZE(mtd)); - env_ptr->crc = - crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd)); - } - - gd->env_addr = (ulong) & env_ptr->data; - gd->env_valid = 1; + rc = env_import(buf, 1); + if (rc) + gd->env_valid = 1; } int saveenv(void) { + env_t env_new; + ssize_t len; + char *res; struct mtd_info *mtd = &onenand_mtd; #ifdef CONFIG_ENV_ADDR_FLEX struct onenand_chip *this = &onenand_chip; #endif - loff_t env_addr = CONFIG_ENV_ADDR; + loff_t env_addr = CONFIG_ENV_ADDR; + size_t retlen; struct erase_info instr = { .callback = NULL, }; - size_t retlen; + + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); instr.len = CONFIG_ENV_SIZE; #ifdef CONFIG_ENV_ADDR_FLEX @@ -122,11 +132,8 @@ int saveenv(void) return 1; } - /* update crc */ - env_ptr->crc = crc32(0, env_ptr->data, ONENAND_ENV_SIZE(mtd)); - if (mtd->write(mtd, env_addr, ONENAND_MAX_ENV_SIZE, &retlen, - (u_char *) env_ptr)) { + (u_char *)&env_new)) { printf("OneNAND: write failed at 0x%llx\n", instr.addr); return 2; } diff --git a/common/env_sf.c b/common/env_sf.c index 4391d61..fb0c39b 100644 --- a/common/env_sf.c +++ b/common/env_sf.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2002 + * (C) Copyright 2000-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com> @@ -29,6 +29,8 @@ #include <environment.h> #include <malloc.h> #include <spi_flash.h> +#include <search.h> +#include <errno.h> #ifndef CONFIG_ENV_SPI_BUS # define CONFIG_ENV_SPI_BUS 0 @@ -77,17 +79,29 @@ void swap_env(void) int saveenv(void) { - u32 saved_size, saved_offset; - char *saved_buffer = NULL; - u32 sector = 1; - int ret; - char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; + env_t env_new; + ssize_t len; + char *res; + u32 saved_size, saved_offset; + char *saved_buffer = NULL; + u32 sector = 1; + int ret; + char flag = OBSOLETE_FLAG, new_flag = ACTIVE_FLAG; if (!env_flash) { puts("Environment SPI flash not initialized\n"); return 1; } + res = (char *)&env_new.data; + len = hexport('\0', &res, ENV_SIZE); + if (len < 0) { + error("Cannot export environment: errno = %d\n", errno); + return 1; + } + env_new.crc = crc32(0, env_new.data, ENV_SIZE); + env_new.flags = ACTIVE_FLAG; + /* Is the sector larger than the env (i.e. embedded) */ if (CONFIG_ENV_SECT_SIZE > CONFIG_ENV_SIZE) { saved_size = CONFIG_ENV_SECT_SIZE - CONFIG_ENV_SIZE; @@ -118,25 +132,25 @@ int saveenv(void) puts("Writing to SPI flash..."); ret = spi_flash_write(env_flash, env_new_offset + offsetof(env_t, data), - sizeof(env_ptr->data), env_ptr->data); + sizeof(env_new.data), env_new.data); if (ret) goto done; ret = spi_flash_write(env_flash, env_new_offset + offsetof(env_t, crc), - sizeof(env_ptr->crc), &env_ptr->crc); + sizeof(env_new.crc), &env_new.crc); if (ret) goto done; ret = spi_flash_write(env_flash, env_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &flag); + sizeof(env_new.flags), &flag); if (ret) goto done; ret = spi_flash_write(env_flash, env_new_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &new_flag); + sizeof(env_new.flags), &new_flag); if (ret) goto done; @@ -164,33 +178,34 @@ void env_relocate_spec(void) int crc1_ok = 0, crc2_ok = 0; env_t *tmp_env1 = NULL; env_t *tmp_env2 = NULL; + env_t ep; uchar flag1, flag2; /* current_env is set only in case both areas are valid! */ int current_env = 0; tmp_env1 = (env_t *)malloc(CONFIG_ENV_SIZE); - if (!tmp_env1) { - puts("*** Warning: could not init environment," - " using defaults\n\n"); - goto out; - } - tmp_env2 = (env_t *)malloc(CONFIG_ENV_SIZE); - if (!tmp_env2) { - puts("*** Warning: could not init environment," - " using defaults\n\n"); - goto out; + + if (!tmp_env1 || !tmp_env2) { + free(tmp_env1); + free(tmp_env2); + set_default_env("!malloc() failed"); + return; } env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!env_flash) - goto err_probe; + if (!env_flash) { + set_default_env("!spi_flash_probe() failed"); + return; + } ret = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, tmp_env1); - if (ret) + if (ret) { + set_default_env("!spi_flash_read() failed"); goto err_read; + } if (crc32(0, tmp_env1->data, ENV_SIZE) == tmp_env1->crc) crc1_ok = 1; @@ -208,25 +223,25 @@ void env_relocate_spec(void) goto err_crc; else if (crc1_ok && !crc2_ok) { gd->env_valid = 1; - memcpy(env_ptr, tmp_env1, CONFIG_ENV_SIZE); + ep = tmp_env1; } else if (!crc1_ok && crc2_ok) { gd->env_valid = 1; - memcpy(env_ptr, tmp_env2, CONFIG_ENV_SIZE); + ep = tmp_env2; swap_env(); } else if (flag1 == ACTIVE_FLAG && flag2 == OBSOLETE_FLAG) { gd->env_valid = 1; - memcpy(env_ptr, tmp_env1, CONFIG_ENV_SIZE); + ep = tmp_env1; } else if (flag1 == OBSOLETE_FLAG && flag2 == ACTIVE_FLAG) { gd->env_valid = 1; - memcpy(env_ptr, tmp_env2, CONFIG_ENV_SIZE); + ep = tmp_env2; swap_env(); } else if (flag1 == flag2) { gd->env_valid = 2; - memcpy(env_ptr, tmp_env1, CONFIG_ENV_SIZE); + ep = tmp_env1; current_env = 1; } else if (flag1 == 0xFF) { gd->env_valid = 2; - memcpy(env_ptr, tmp_env1, CONFIG_ENV_SIZE); + ep = tmp_env1; current_env = 1; } else { /* @@ -234,35 +249,42 @@ void env_relocate_spec(void) * default path is desirable. */ gd->env_valid = 2; - memcpy(env_ptr, tmp_env2, CONFIG_ENV_SIZE); + ep = tmp_env2; swap_env(); current_env = 2; } + + rc = env_import((char *)ep, 0); + if (!rc) { + error("Cannot import environment: errno = %d\n", errno); + goto out; + } + if (current_env == 1) { if (flag2 != OBSOLETE_FLAG) { flag2 = OBSOLETE_FLAG; spi_flash_write(env_flash, env_new_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &flag2); + sizeof(env_new.flags), &flag2); } if (flag1 != ACTIVE_FLAG) { flag1 = ACTIVE_FLAG; spi_flash_write(env_flash, env_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &flag1); + sizeof(env_new.flags), &flag1); } } else if (current_env == 2) { if (flag1 != OBSOLETE_FLAG) { flag1 = OBSOLETE_FLAG; spi_flash_write(env_flash, env_new_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &flag1); + sizeof(env_new.flags), &flag1); } if (flag2 != ACTIVE_FLAG) { flag2 = ACTIVE_FLAG; spi_flash_write(env_flash, env_offset + offsetof(env_t, flags), - sizeof(env_ptr->flags), &flag2); + sizeof(env_new.flags), &flag2); } } if (gd->env_valid == 2) { @@ -278,15 +300,9 @@ void env_relocate_spec(void) err_read: spi_flash_free(env_flash); env_flash = NULL; -err_probe: -err_crc: - puts("*** Warning - bad CRC, using default environment\n\n"); out: - if (tmp_env1) - free(tmp_env1); - if (tmp_env2) - free(tmp_env2); - set_default_env(); + free(tmp_env1); + free(tmp_env2); } #else int saveenv(void) @@ -348,32 +364,30 @@ int saveenv(void) void env_relocate_spec(void) { + char buf[CONFIG_ENV_SIZE]; int ret; env_flash = spi_flash_probe(CONFIG_ENV_SPI_BUS, CONFIG_ENV_SPI_CS, CONFIG_ENV_SPI_MAX_HZ, CONFIG_ENV_SPI_MODE); - if (!env_flash) - goto err_probe; - - ret = spi_flash_read(env_flash, CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, env_ptr); - if (ret) - goto err_read; - - if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) - goto err_crc; + if (!env_flash) { + set_default_env("!spi_flash_probe() failed"); + return; + } - gd->env_valid = 1; + ret = spi_flash_read(env_flash, + CONFIG_ENV_OFFSET, CONFIG_ENV_SIZE, buf); + if (ret) { + set_default_env("!spi_flash_read() failed"); + goto out; + } - return; + ret = env_import(buf, 1); -err_read: + if (ret) + gd->env_valid = 1; +out: spi_flash_free(env_flash); env_flash = NULL; -err_probe: -err_crc: - puts("*** Warning - bad CRC, using default environment\n\n"); - - set_default_env(); } #endif diff --git a/common/exports.c b/common/exports.c index ceee73a..3dff735 100644 --- a/common/exports.c +++ b/common/exports.c @@ -34,9 +34,6 @@ unsigned long get_version(void) # define spi_release_bus dummy # define spi_xfer dummy #endif -#ifndef CONFIG_HAS_UID -# define forceenv dummy -#endif void jumptable_init(void) { diff --git a/common/flash.c b/common/flash.c index 683978e..781cb9c 100644 --- a/common/flash.c +++ b/common/flash.c @@ -27,6 +27,7 @@ #include <flash.h> #if !defined(CONFIG_SYS_NO_FLASH) +#include <mtd/cfi_flash.h> extern flash_info_t flash_info[]; /* info for FLASH chips */ diff --git a/common/image.c b/common/image.c index fcb938b..3a2f25e 100644 --- a/common/image.c +++ b/common/image.c @@ -103,6 +103,7 @@ static table_entry_t uimage_os[] = { { IH_OS_LYNXOS, "lynxos", "LynxOS", }, #endif { IH_OS_NETBSD, "netbsd", "NetBSD", }, + { IH_OS_OSE, "ose", "Enea OSE", }, { IH_OS_RTEMS, "rtems", "RTEMS", }, { IH_OS_U_BOOT, "u-boot", "U-Boot", }, #if defined(CONFIG_CMD_ELF) || defined(USE_HOSTCC) diff --git a/common/serial.c b/common/serial.c index 1345c08..25b235a 100644 --- a/common/serial.c +++ b/common/serial.c @@ -38,8 +38,7 @@ struct serial_device *__default_serial_console (void) #elif defined(CONFIG_8xx_CONS_SCC1) || defined(CONFIG_8xx_CONS_SCC2) \ || defined(CONFIG_8xx_CONS_SCC3) || defined(CONFIG_8xx_CONS_SCC4) return &serial_scc_device; -#elif defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ +#elif defined(CONFIG_4xx) \ || defined(CONFIG_MB86R0x) || defined(CONFIG_MPC5xxx) \ || defined(CONFIG_MPC83xx) || defined(CONFIG_MPC85xx) \ || defined(CONFIG_MPC86xx) || defined(CONFIG_SYS_SC520) @@ -55,10 +54,7 @@ struct serial_device *__default_serial_console (void) #else #error "Bad CONFIG_CONS_INDEX." #endif -#elif defined(CONFIG_UART1_CONSOLE) - return &serial1_device; -#else - return &serial0_device; + return &serial0_device; #endif #elif defined(CONFIG_MPC512X) #if (CONFIG_PSC_CONSOLE == 3) @@ -127,13 +123,6 @@ void serial_initialize (void) serial_register (&serial_scc_device); #endif -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_440) \ - || defined(CONFIG_405EP) || defined(CONFIG_405EZ) || defined(CONFIG_405EX) \ - || defined(CONFIG_MPC5xxx) - serial_register(&serial0_device); - serial_register(&serial1_device); -#endif - #if defined(CONFIG_SYS_NS16550_SERIAL) #if defined(CONFIG_SYS_NS16550_COM1) serial_register(&eserial1_device); diff --git a/common/stdio.c b/common/stdio.c index 870ddfd..2501369 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -76,18 +76,10 @@ static void drv_system_init (void) strcpy (dev.name, "serial"); dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT | DEV_FLAGS_SYSTEM; -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO - dev.putc = serial_buffered_putc; - dev.puts = serial_buffered_puts; - dev.getc = serial_buffered_getc; - dev.tstc = serial_buffered_tstc; -#else dev.putc = serial_putc; dev.puts = serial_puts; dev.getc = serial_getc; dev.tstc = serial_tstc; -#endif - stdio_register (&dev); #ifdef CONFIG_SYS_DEVICE_NULLDEV diff --git a/disk/part.c b/disk/part.c index 1806fe6..2b63db6 100644 --- a/disk/part.c +++ b/disk/part.c @@ -78,13 +78,20 @@ block_dev_desc_t *get_dev(char* ifname, int dev) { const struct block_drvr *drvr = block_drvr; block_dev_desc_t* (*reloc_get_dev)(int dev); + char *name; - while (drvr->name) { + name = drvr->name; +#ifndef CONFIG_RELOC_FIXUP_WORKS + name += gd->reloc_off; +#endif + while (name) { + name = drvr->name; reloc_get_dev = drvr->get_dev; #ifndef CONFIG_RELOC_FIXUP_WORKS + name += gd->reloc_off; reloc_get_dev += gd->reloc_off; #endif - if (strncmp(ifname, drvr->name, strlen(drvr->name)) == 0) + if (strncmp(ifname, name, strlen(name)) == 0) return reloc_get_dev(dev); drvr++; } diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation new file mode 100644 index 0000000..e3ed60e --- /dev/null +++ b/doc/README.arm-relocation @@ -0,0 +1,344 @@ +To make relocation on arm working, the following changes are done: + +Add new compilerflag: + +-fPIC + + -> compiler generates position independent code + +changes in board code: + +- dram_init: + - bd pointer is now at this point not accessible, so only + detect the real dramsize, and store it in gd->ram_size. + best detected with get_ram_size(); + ToDo: move there also the dram initialization on boards where + it is possible. + - setup the bd_t dram bank info in the new function + dram_init_banksize(). + +- board.c code is adapted from ppc code + +- undef CONFIG_RELOC_FIXUP_WORKS + + -> cmdtabl, and subcommand table must be handled from "hand" + collected in section "__datarellocal_start". + + - How To fixup the sections: + + __datarel_start, __datarelrolocal_start, __datarellocal_start and + __datarelro_start + + automatically? Then it should be possible to define again + CONFIG_RELOC_FIXUP_WORKS + +- irq stack setup is now not longer on a fix position, instead it is + calculated in board_init_f, and stored in gd->irq_sp + +------------------------------------------------------------------------------------- + +To compile a board without relocation, define CONFIG_SYS_ARM_WITHOUT_RELOC +This possibility will removed!! So please fix your board to compile without +CONFIG_SYS_ARM_WITHOUT_RELOC defined!!! + +------------------------------------------------------------------------------------- + +For boards which boot from nand_spl, it is possible to save a copy +if TEXT_BASE == relocation address! This prevents that uboot code +is copied again in relocate_code(). + +example for the tx25 board: + +a) cpu starts +b) it copies the first page in nand to internal ram + (nand_spl_code) +c) end executes this code +d) this initialize CPU, RAM, ... and copy itself to RAM + (this bin must fit in one page, so board_init_f() + don;t fit in it ... ) +e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and + starts this image @ CONFIG_SYS_NAND_U_BOOT_START +f) u-boot code steps through board_init_f() and calculates + the relocation address and copy itself to it + +If TEXT_BASE == relocation address, the copying of u-boot +in f) could be saved. + +------------------------------------------------------------------------------------- + +ToDo: + +- fill in bd_t infos (check) +- adapt all boards + +- maybe adapt TEXT_BASE (this must be checked from board maintainers) + This *must* be done for boards, which boot from NOR flash + + on other boards if TEXT_BASE = relocation baseaddr, this saves + one copying from u-boot code. + +- new function dram_init_banksize() is actual board specific. Maybe + we make a weak default function in arch/arm/lib/board.c ? + +------------------------------------------------------------------------------------- + +Relocation with NAND_SPL (example for the tx25): + +- cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE) + and start with code execution on this address. + +- The First page contains u-boot code from u-boot:nand_spl/nand_boot_fsl_nfc.c + which inits the dram, cpu registers, reloacte itself to TEXT_BASE and loads + the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution + @CONFIG_SYS_NAND_U_BOOT_START + +- This u-boot does no ram int, nor cpu register setup. Just looks + where it have to relocate and relocate itself to this address. + If relocate address = TEXT_BASE(not the same, as the TEXT_BASE + from the nand_spl code), no need to copy, just go on with bss clear + and jump to board_init_r. + +------------------------------------------------------------------------------------- + +Relocation: +How to translate flash addresses in GOT to ram addresses. +This is automagically done from code, but this example +shows, how this magic code works ;-) +(example on the qong board) + +Find a variable: + +a) search it in System.map +(for example flash_info) + +a005b4c0 B BootpID +a005b4c4 B BootpTry +a005b4c8 b slave +a005b4cc B flash_info +^^^^^^^^ +a005c908 b saved_sector.4002 +a005c910 b cfi_mtd_info +a005c9c0 b cfi_mtd_names +a005c9d0 B mtd_table + +--------------------------------------- + +b) create hexdump from u-boot code: + +hexdump -C u-boot > gnlmpfhex + +--------------------------------------- + +c) search the variables address in the hexdump + + +* +0005fc80 00 00 00 00 00 00 00 00 2c 06 01 a0 18 cd 05 a0 |........,.......| +0005fc90 9c d4 05 a0 bc b4 05 a0 1c 7f 05 a0 f0 05 01 a0 |................| +0005fca0 08 5a 04 a0 1c ab 05 a0 ec a4 05 a0 98 c3 01 a0 |.Z..............| +0005fcb0 a0 d6 05 a0 04 71 05 a0 c0 f9 00 a0 3c cd 05 a0 |.....q......<...| +0005fcc0 cc b4 05 a0 f0 fa 00 a0 f0 d6 05 a0 10 86 05 a0 |................| + ^^^^^^^^^^^ +0005fcd0 a4 16 06 a0 dc 64 05 a0 18 86 05 a0 52 48 05 a0 |.....d......RH..| +0005fce0 c0 86 05 a0 24 6e 02 a0 b4 6c 05 a0 b0 94 01 a0 |....$n...l......| +0005fcf0 1c 86 05 a0 50 85 05 a0 d4 0c 06 a0 bc 0b 06 a0 |....P...........| + + +-> 0005fcc0 + +---------------------------------------- + +d) know we calculate this address in RAM + + + 8ff08000 (new address of code in RAM *1) + ++ 0005fcc0 + +- 00008000 (offset of text *2) + +---------- + + 8ff5fcc0 -> Addr GOT in RAM + +*1: +activate debug and look for the line: +Now running in RAM - U-Boot at: 8ff08000 + ^^^^^^^^ + new address of u-boot code in RAM + +*2: +Section Headers: + [Nr] Name Type Addr Off Size ES Flg Lk Inf Al + [ 0] NULL 00000000 000000 000000 00 0 0 0 + [ 1] .text PROGBITS a0000000 008000 04599c 00 AX 0 0 32 + ^^^^^^ + Offset of text + +---------------------------------------- + +e) now we look in 8ff5fcc0 (RAM) + + +QongEVB>md 0x8ff5fcc0 +8ff5fcc0 : a005b4cc a000faf0 a005d6f0 a0058610 ................ + ^^^^^^^^ + Bingo, here we have the old flash address (when relocation + is working, here is the fixed ram address. see @ f, how + it gets calculated) + + +---------------------------------------- + +f) now translate it in the new RAM address + + a005b4cc + +- a0000000 TextBase + ++ 8ff08000 new address of u-boot in ram +---------- + 8ff634cc + +QongEVB>mm 0x8ff5fcc0 0x8ff634cc 1 +QongEVB>md 0x8ff5fcc0 +8ff5fcc0 : 8ff634cc a000faf0 a005d6f0 a0058610 .4.............. +8ff5fcd0 : a00616a4 a00564dc a0058618 a0054852 .....d......RH.. + +As this must be done for all address in the GOT, the u-boot +code did this automagically ... :-) + +---------------------------------------------- + +g) check if the new address is really in the bss section: + +bss start: +8ff6054c (8ff08000 + 0005854C monitorlen) + +bss end: +8ff698ac (8ff08000 + 618AC) + +8ff634cc is in bss :-) + +---------------------------------------------- + +h) u-boot prints: + +important addresses: + +U-Boot code: A0000000 -> A005854C BSS: -> A00618AC TextBase 0xa0000000 +Now running in RAM - U-Boot at: 8ff08000 relocBase 0x8ff08000 + + +--------- + +U-Boot 2010.06-rc2-00002-gf8fbb25-dirty (Jun 18 2010 - 17:07:19) + +U-Boot code: A0000000 -> A005854C BSS: -> A00618AC +CPU: Freescale i.MX31 at 398 MHz +Board: DAVE/DENX Qong +mon: FFFFFFFF gd->monLen: 000618AC +Top of RAM usable for U-Boot at: 90000000 +LCD panel info: 640 x 480, 16 bit/pix +Reserving 600k for LCD Framebuffer at: 8ff6a000 +Reserving 390k for U-Boot at: 8ff08000 +Reserving 1280k for malloc() at: 8fdc8000 +Reserving 28 Bytes for Board Info at: 8fdc7fe4 +Reserving 48 Bytes for Global Data at: 8fdc7fb4 +New Stack Pointer is: 8fdc7fb0 +RAM Configuration: +Bank #0: 80000000 256 MiB +mon: 0005854C gd->monLen: 000618AC +Now running in RAM - U-Boot at: 8ff08000 + +------------------------------------------------------------------------------------- + +Debugging u-boot in RAM: +(example on the qong board) + +a) add in config.mk: + +PLATFORM_CPPFLAGS += -DDEBUG + +----------------- + +b) start debugger + +arm-linux-gdb u-boot + +[hs@pollux u-boot]$ arm-linux-gdb u-boot +GNU gdb Red Hat Linux (6.7-2rh) +Copyright (C) 2007 Free Software Foundation, Inc. +License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> +This is free software: you are free to change and redistribute it. +There is NO WARRANTY, to the extent permitted by law. Type "show copying" +and "show warranty" for details. +This GDB was configured as "--host=i686-pc-linux-gnu --target=arm-linux". +The target architecture is set automatically (currently arm) +.. +(gdb) + +----------------- + +c) connect to target + +target remote bdi10:2001 + +(gdb) target remote bdi10:2001 +Remote debugging using bdi10:2001 +0x8ff17f10 in ?? () +(gdb) + +----------------- + +d) discard symbol-file + +(gdb) symbol-file +Discard symbol table from `/home/hs/celf/u-boot/u-boot'? (y or n) y +No symbol file now. +(gdb) + +----------------- + +e) load new symbol table: + +(gdb) add-symbol-file u-boot 0x8ff08000 +add symbol table from file "u-boot" at + .text_addr = 0x8ff08000 +(y or n) y +Reading symbols from /home/hs/celf/u-boot/u-boot...done. +(gdb) c +Continuing. +^C +Program received signal SIGSTOP, Stopped (signal). +0x8ff17f18 in serial_getc () at serial_mxc.c:192 +192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY); +(gdb) + +add-symbol-file u-boot 0x8ff08000 + ^^^^^^^^^^ + get this address from u-boot debug printfs + +U-Boot 2010.06-rc2-00009-gf77b8b8-dirty (Jun 22 2010 - 09:43:46) + +U-Boot code: A0000000 -> A0058BAC BSS: -> A0061F10 +CPU: Freescale i.MX31 at 398 MHz +Board: DAVE/DENX Qong +mon: FFFFFFFF gd->monLen: 00061F10 +Top of RAM usable for U-Boot at: 90000000 +LCD panel info: 640 x 480, 16 bit/pix +Reserving 600k for LCD Framebuffer at: 8ff6a000 +Reserving 391k for U-Boot at: 8ff08000 + ^^^^^^^^ +Reserving 1280k for malloc() at: 8fdc8000 +Reserving 24 Bytes for Board Info at: 8fdc7fe8 +Reserving 52 Bytes for Global Data at: 8fdc7fb4 +New Stack Pointer is: 8fdc7fb0 +RAM Configuration: +Bank #0: 80000000 256 MiB +relocation Offset is: eff08000 +mon: 00058BAC gd->monLen: 00061F10 +Now running in RAM - U-Boot at: 8ff08000 + ^^^^^^^^ + +Now you can use gdb as usual :-) diff --git a/doc/README.ppc440 b/doc/README.ppc440 index 1b96458..dd8ccaa 100644 --- a/doc/README.ppc440 +++ b/doc/README.ppc440 @@ -77,12 +77,6 @@ This is controlled with the CONFIG_SYS_EXT_SERIAL_CLOCK flag. When using internal clocking, the "ideal baud rate" settings in the 440GP user manual are automatically calculated. -CONFIG_SERIAL_SOFTWARE_FIFO enables interrupt-driven serial operation. -But the last time I checked, interrupts were initialized after the -serial port causing the interrupt handler to be removed from the -handler table. This will probably be fixed soon ... or fix it -yourself and submit a patch :-) - I2C ================= diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index a7c4e69..3febd1f 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -40,6 +40,7 @@ static unsigned int current_bus; void i2c_init (int speed, int slaveadd) { + DECLARE_GLOBAL_DATA_PTR; int psc, fsscll, fssclh; int hsscll = 0, hssclh = 0; u32 scll, sclh; @@ -139,7 +140,8 @@ void i2c_init (int speed, int slaveadd) writew (0xFFFF, &i2c_base->stat); writew (0, &i2c_base->cnt); - bus_initialized[current_bus] = 1; + if (gd->flags & GD_FLG_RELOC) + bus_initialized[current_bus] = 1; } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) diff --git a/drivers/i2c/ppc4xx_i2c.c b/drivers/i2c/ppc4xx_i2c.c index e9548f1..c1cbe55 100644 --- a/drivers/i2c/ppc4xx_i2c.c +++ b/drivers/i2c/ppc4xx_i2c.c @@ -27,8 +27,8 @@ */ #include <common.h> -#include <ppc4xx.h> -#include <4xx_i2c.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-i2c.h> #include <i2c.h> #include <asm/io.h> diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 8d0b6d6..a655a16 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -46,8 +46,7 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 6 #endif -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else #if CONFIG_PS2SERIAL == 1 #define COM_BASE (CONFIG_SYS_CCSRBAR+0x4500) @@ -57,17 +56,12 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 2 #endif -#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ +#endif /* CONFIG_MPC5xxx / other */ static int ps2ser_getc_hw(void); static void ps2ser_interrupt(void *dev_id); extern struct serial_state rs_table[]; /* in serial.c */ -#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \ - !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \ - !defined(CONFIG_MPC8555) -static struct serial_state *state; -#endif static u_char ps2buf[PS2BUF_SIZE]; static atomic_t ps2buf_cnt; @@ -111,8 +105,8 @@ int ps2ser_init(void) return (0); } -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else + int ps2ser_init(void) { NS16550_t com_port = (NS16550_t)COM_BASE; @@ -128,76 +122,24 @@ int ps2ser_init(void) return (0); } -#else /* !CONFIG_MPC5xxx && !CONFIG_MPC8540 / other */ - -static inline unsigned int ps2ser_in(int offset) -{ - return readb((unsigned long) state->iomem_base + offset); -} - -static inline void ps2ser_out(int offset, int value) -{ - writeb(value, (unsigned long) state->iomem_base + offset); -} - -int ps2ser_init(void) -{ - int quot; - unsigned cval; - - state = rs_table + CONFIG_PS2SERIAL; - - quot = state->baud_base / PS2SER_BAUD; - cval = 0x3; /* 8N1 - 8 data bits, no parity bits, 1 stop bit */ - - /* Set speed, enable interrupts, enable FIFO - */ - ps2ser_out(UART_LCR, cval | UART_LCR_DLAB); - ps2ser_out(UART_DLL, quot & 0xff); - ps2ser_out(UART_DLM, quot >> 8); - ps2ser_out(UART_LCR, cval); - ps2ser_out(UART_IER, UART_IER_RDI); - ps2ser_out(UART_MCR, UART_MCR_OUT2 | UART_MCR_DTR | UART_MCR_RTS); - ps2ser_out(UART_FCR, - UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT); - - /* If we read 0xff from the LSR, there is no UART here - */ - if (ps2ser_in(UART_LSR) == 0xff) { - printf ("ps2ser.c: no UART found\n"); - return -1; - } - - irq_install_handler(state->irq, ps2ser_interrupt, NULL); - - return 0; -} -#endif /* CONFIG_MPC5xxx / CONFIG_MPC8540 / other */ +#endif /* CONFIG_MPC5xxx / other */ void ps2ser_putc(int chr) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else NS16550_t com_port = (NS16550_t)COM_BASE; #endif -#ifdef DEBUG - printf(">>>> 0x%02x\n", chr); -#endif + debug(">>>> 0x%02x\n", chr); #ifdef CONFIG_MPC5xxx while (!(psc->psc_status & PSC_SR_TXRDY)); psc->psc_buffer_8 = chr; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else while ((com_port->lsr & UART_LSR_THRE) == 0); com_port->thr = chr; -#else - while (!(ps2ser_in(UART_LSR) & UART_LSR_THRE)); - - ps2ser_out(UART_TX, chr); #endif } @@ -205,8 +147,7 @@ static int ps2ser_getc_hw(void) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else NS16550_t com_port = (NS16550_t)COM_BASE; #endif int res = -1; @@ -215,15 +156,10 @@ static int ps2ser_getc_hw(void) if (psc->psc_status & PSC_SR_RXRDY) { res = (psc->psc_buffer_8); } -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else if (com_port->lsr & UART_LSR_DR) { res = com_port->rbr; } -#else - if (ps2ser_in(UART_LSR) & UART_LSR_DR) { - res = (ps2ser_in(UART_RX)); - } #endif return res; @@ -234,9 +170,7 @@ int ps2ser_getc(void) volatile int chr; int flags; -#ifdef DEBUG - printf("<< "); -#endif + debug("<< "); flags = disable_interrupts(); @@ -251,11 +185,10 @@ int ps2ser_getc(void) } while (chr < 0); - if (flags) enable_interrupts(); + if (flags) + enable_interrupts(); -#ifdef DEBUG - printf("0x%02x\n", chr); -#endif + debug("0x%02x\n", chr); return chr; } @@ -275,8 +208,7 @@ static void ps2ser_interrupt(void *dev_id) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) +#else NS16550_t com_port = (NS16550_t)COM_BASE; #endif int chr; @@ -286,11 +218,8 @@ static void ps2ser_interrupt(void *dev_id) chr = ps2ser_getc_hw(); #ifdef CONFIG_MPC5xxx status = psc->psc_status; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) - status = com_port->lsr; #else - status = ps2ser_in(UART_IIR); + status = com_port->lsr; #endif if (chr < 0) continue; @@ -303,13 +232,9 @@ static void ps2ser_interrupt(void *dev_id) } #ifdef CONFIG_MPC5xxx } while (status & PSC_SR_RXRDY); -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ - defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) - } while (status & UART_LSR_DR); #else - } while (status & UART_IIR_RDI); + } while (status & UART_LSR_DR); #endif - if (atomic_read(&ps2buf_cnt)) { ps2mult_callback(atomic_read(&ps2buf_cnt)); } diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 44ebb9d..02dd27f 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -62,20 +62,9 @@ * reading and writing ... (yes there is such a Hardware). */ -#ifndef CONFIG_SYS_FLASH_BANKS_LIST -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#endif - static uint flash_offset_cfi[2] = { FLASH_OFFSET_CFI, FLASH_OFFSET_CFI_ALT }; static uint flash_verbose = 1; -/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */ -#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT -# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT -#else -# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS -#endif - flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ /* @@ -85,6 +74,17 @@ flash_info_t flash_info[CFI_MAX_FLASH_BANKS]; /* FLASH chips info */ #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT #endif +#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) +int cfi_flash_num_flash_banks = CONFIG_SYS_MAX_FLASH_BANKS_DETECT; +#endif + +static phys_addr_t __cfi_flash_bank_addr(int i) +{ + return ((phys_addr_t [])CONFIG_SYS_FLASH_BANKS_LIST)[i]; +} +phys_addr_t cfi_flash_bank_addr(int i) + __attribute__((weak, alias("__cfi_flash_bank_addr"))); + static void __flash_write8(u8 value, void *addr) { __raw_writeb(value, addr); @@ -153,7 +153,7 @@ u64 flash_read64(void *addr)__attribute__((weak, alias("__flash_read64"))); flash_info_t *flash_get_info(ulong base) { int i; - flash_info_t * info = 0; + flash_info_t *info = NULL; for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { info = & flash_info[i]; @@ -162,7 +162,7 @@ flash_info_t *flash_get_info(ulong base) break; } - return i == CONFIG_SYS_MAX_FLASH_BANKS ? 0 : info; + return info; } #endif @@ -2021,14 +2021,12 @@ unsigned long flash_init (void) getenv_f("unlock", s, sizeof(s)); #endif -#define BANK_BASE(i) (((phys_addr_t [CFI_MAX_FLASH_BANKS])CONFIG_SYS_FLASH_BANKS_LIST)[i]) - /* Init: no FLASHes known */ for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; ++i) { flash_info[i].flash_id = FLASH_UNKNOWN; - if (!flash_detect_legacy (BANK_BASE(i), i)) - flash_get_size (BANK_BASE(i), i); + if (!flash_detect_legacy(cfi_flash_bank_addr(i), i)) + flash_get_size(cfi_flash_bank_addr(i), i); size += flash_info[i].size; if (flash_info[i].flash_id == FLASH_UNKNOWN) { #ifndef CONFIG_SYS_FLASH_QUIET_TEST diff --git a/drivers/mtd/cfi_mtd.c b/drivers/mtd/cfi_mtd.c index 6a0cab3..cbcc165 100644 --- a/drivers/mtd/cfi_mtd.c +++ b/drivers/mtd/cfi_mtd.c @@ -30,15 +30,7 @@ #include <asm/errno.h> #include <linux/mtd/mtd.h> #include <linux/mtd/concat.h> - -/* use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined */ -#ifdef CONFIG_SYS_MAX_FLASH_BANKS_DETECT -# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT -#else -# define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS -#endif - -extern flash_info_t flash_info[]; +#include <mtd/cfi_flash.h> static struct mtd_info cfi_mtd_info[CFI_MAX_FLASH_BANKS]; static char cfi_mtd_names[CFI_MAX_FLASH_BANKS][16]; diff --git a/drivers/mtd/nand/ndfc.c b/drivers/mtd/nand/ndfc.c index 0dd6789..3ca13a9 100644 --- a/drivers/mtd/nand/ndfc.c +++ b/drivers/mtd/nand/ndfc.c @@ -35,7 +35,7 @@ #include <linux/mtd/nand_ecc.h> #include <asm/processor.h> #include <asm/io.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> /* * We need to store the info, which chip-select (CS) is used for the diff --git a/drivers/net/4xx_enet.c b/drivers/net/4xx_enet.c index d9487ad..45ff4f3 100644 --- a/drivers/net/4xx_enet.c +++ b/drivers/net/4xx_enet.c @@ -87,9 +87,9 @@ #include <asm/cache.h> #include <asm/mmu.h> #include <commproc.h> -#include <ppc4xx.h> -#include <ppc4xx_enet.h> -#include <405_mal.h> +#include <asm/ppc4xx.h> +#include <asm/ppc4xx-emac.h> +#include <asm/ppc4xx-mal.h> #include <miiphy.h> #include <malloc.h> @@ -1494,8 +1494,7 @@ get_speed: /* set speed */ if (speed == _1000BASET) { -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) unsigned long pfc1; mfsdr (SDR0_PFC1, pfc1); diff --git a/drivers/pcmcia/mpc8xx_pcmcia.c b/drivers/pcmcia/mpc8xx_pcmcia.c index 7030574..74a50f1 100644 --- a/drivers/pcmcia/mpc8xx_pcmcia.c +++ b/drivers/pcmcia/mpc8xx_pcmcia.c @@ -57,12 +57,6 @@ static const u_int m8xx_size_to_gray[M8XX_SIZES_NO] = /* -------------------------------------------------------------------- */ -#ifdef CONFIG_HMI10 -#define HMI10_FRAM_TIMING ( PCMCIA_SHT(2) \ - | PCMCIA_SST(2) \ - | PCMCIA_SL(4)) -#endif - #if defined(CONFIG_LWMON) || defined(CONFIG_NSCU) #define CONFIG_SYS_PCMCIA_TIMING ( PCMCIA_SHT(9) \ | PCMCIA_SST(3) \ @@ -106,17 +100,6 @@ int pcmcia_on (void) switch (i) { #ifdef CONFIG_IDE_8xx_PCCARD case 4: -#ifdef CONFIG_HMI10 - { /* map FRAM area */ - win->or = ( PCMCIA_BSIZE_256K - | PCMCIA_PPS_8 - | PCMCIA_PRS_ATTR - | slotbit - | PCMCIA_PV - | HMI10_FRAM_TIMING ); - break; - } -#endif case 0: { /* map attribute memory */ win->or = ( PCMCIA_BSIZE_64M | PCMCIA_PPS_8 @@ -147,18 +130,6 @@ int pcmcia_on (void) break; } #endif /* CONFIG_IDE_8xx_PCCARD */ -#ifdef CONFIG_HMI10 - case 3: { /* map I/O window for 4xUART data/ctrl */ - win->br += 0x40000; - win->or = ( PCMCIA_BSIZE_256K - | PCMCIA_PPS_8 - | PCMCIA_PRS_IO - | slotbit - | PCMCIA_PV - | CONFIG_SYS_PCMCIA_TIMING ); - break; - } -#endif /* CONFIG_HMI10 */ default: /* set to not valid */ win->or = 0; break; diff --git a/drivers/pcmcia/tqm8xx_pcmcia.c b/drivers/pcmcia/tqm8xx_pcmcia.c index 6ba8b5c..ca1a9fe 100644 --- a/drivers/pcmcia/tqm8xx_pcmcia.c +++ b/drivers/pcmcia/tqm8xx_pcmcia.c @@ -36,39 +36,6 @@ #define power_on_5_0(slot) do {} while (0) #define power_on_3_3(slot) do {} while (0) -#elif defined(CONFIG_HMI10) - -static inline void power_config(int slot) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - /* - * Configure Port B pins for - * 5 Volts Enable and 3 Volts enable - */ - immap->im_cpm.cp_pbpar &= ~(0x00000300); -} - -static inline void power_off(int slot) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - /* remove all power */ - immap->im_cpm.cp_pbdat |= 0x00000300; -} - -static inline void power_on_5_0(int slot) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - immap->im_cpm.cp_pbdat &= ~(0x0000100); - immap->im_cpm.cp_pbdir |= 0x00000300; -} - -static inline void power_on_3_3(int slot) -{ - volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; - immap->im_cpm.cp_pbdat &= ~(0x0000200); - immap->im_cpm.cp_pbdir |= 0x00000300; -} - #elif defined(CONFIG_VIRTLAB2) #define power_config(slot) do {} while (0) @@ -128,21 +95,12 @@ static inline void power_on_3_3(int slot) #endif -#ifdef CONFIG_HMI10 -static inline int check_card_is_absent(int slot) -{ - volatile pcmconf8xx_t *pcmp = - (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); - return pcmp->pcmc_pipr & (0x10000000 >> (slot << 4)); -} -#else static inline int check_card_is_absent(int slot) { volatile pcmconf8xx_t *pcmp = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia)); return pcmp->pcmc_pipr & (0x18000000 >> (slot << 4)); } -#endif #ifdef NSCU_OE_INV #define NSCU_GCRX_CXOE 0 diff --git a/drivers/serial/serial_netarm.c b/drivers/serial/serial_netarm.c index 2eb5393..d04790d 100644 --- a/drivers/serial/serial_netarm.c +++ b/drivers/serial/serial_netarm.c @@ -51,13 +51,8 @@ DECLARE_GLOBAL_DATA_PTR; } -#ifndef CONFIG_UART1_CONSOLE volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(0); volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(1); -#else -volatile netarm_serial_channel_t *serial_reg_ch1 = get_serial_channel(1); -volatile netarm_serial_channel_t *serial_reg_ch2 = get_serial_channel(0); -#endif extern void _netarm_led_FAIL1(void); diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile index 1d7362d..8e6b26e 100644 --- a/drivers/usb/gadget/Makefile +++ b/drivers/usb/gadget/Makefile @@ -25,6 +25,11 @@ include $(TOPDIR)/config.mk LIB := $(obj)libusb_gadget.a +# new USB gadget layer dependencies +ifdef CONFIG_USB_ETHER +COBJS-y += ether.o epautoconf.o config.o usbstring.o +else +# Devices not related to the new gadget layer depend on CONFIG_USB_DEVICE ifdef CONFIG_USB_DEVICE COBJS-y += core.o COBJS-y += ep0.o @@ -34,6 +39,7 @@ COBJS-$(CONFIG_MPC885_FAMILY) += mpc8xx_udc.o COBJS-$(CONFIG_PXA27X) += pxa27x_udc.o COBJS-$(CONFIG_SPEARUDC) += spr_udc.o endif +endif COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/usb/gadget/config.c b/drivers/usb/gadget/config.c new file mode 100644 index 0000000..cf22629 --- /dev/null +++ b/drivers/usb/gadget/config.c @@ -0,0 +1,119 @@ +/* + * usb/gadget/config.c -- simplify building config descriptors + * + * Copyright (C) 2003 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + +#include <common.h> +#include <asm/errno.h> +#include <linux/list.h> +#include <linux/string.h> + +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> + + +/** + * usb_descriptor_fillbuf - fill buffer with descriptors + * @buf: Buffer to be filled + * @buflen: Size of buf + * @src: Array of descriptor pointers, terminated by null pointer. + * + * Copies descriptors into the buffer, returning the length or a + * negative error code if they can't all be copied. Useful when + * assembling descriptors for an associated set of interfaces used + * as part of configuring a composite device; or in other cases where + * sets of descriptors need to be marshaled. + */ +int +usb_descriptor_fillbuf(void *buf, unsigned buflen, + const struct usb_descriptor_header **src) +{ + u8 *dest = buf; + + if (!src) + return -EINVAL; + + /* fill buffer from src[] until null descriptor ptr */ + for (; NULL != *src; src++) { + unsigned len = (*src)->bLength; + + if (len > buflen) + return -EINVAL; + memcpy(dest, *src, len); + buflen -= len; + dest += len; + } + return dest - (u8 *)buf; +} + + +/** + * usb_gadget_config_buf - builts a complete configuration descriptor + * @config: Header for the descriptor, including characteristics such + * as power requirements and number of interfaces. + * @desc: Null-terminated vector of pointers to the descriptors (interface, + * endpoint, etc) defining all functions in this device configuration. + * @buf: Buffer for the resulting configuration descriptor. + * @length: Length of buffer. If this is not big enough to hold the + * entire configuration descriptor, an error code will be returned. + * + * This copies descriptors into the response buffer, building a descriptor + * for that configuration. It returns the buffer length or a negative + * status code. The config.wTotalLength field is set to match the length + * of the result, but other descriptor fields (including power usage and + * interface count) must be set by the caller. + * + * Gadget drivers could use this when constructing a config descriptor + * in response to USB_REQ_GET_DESCRIPTOR. They will need to patch the + * resulting bDescriptorType value if USB_DT_OTHER_SPEED_CONFIG is needed. + */ +int usb_gadget_config_buf( + const struct usb_config_descriptor *config, + void *buf, + unsigned length, + const struct usb_descriptor_header **desc +) +{ + struct usb_config_descriptor *cp = buf; + int len; + + /* config descriptor first */ + if (length < USB_DT_CONFIG_SIZE || !desc) + return -EINVAL; + *cp = *config; + + /* then interface/endpoint/class/vendor/... */ + len = usb_descriptor_fillbuf(USB_DT_CONFIG_SIZE + (u8 *)buf, + length - USB_DT_CONFIG_SIZE, desc); + if (len < 0) + return len; + len += USB_DT_CONFIG_SIZE; + if (len > 0xffff) + return -EINVAL; + + /* patch up the config descriptor */ + cp->bLength = USB_DT_CONFIG_SIZE; + cp->bDescriptorType = USB_DT_CONFIG; + cp->wTotalLength = cpu_to_le16(len); + cp->bmAttributes |= USB_CONFIG_ATT_ONE; + return len; +} + diff --git a/drivers/usb/gadget/epautoconf.c b/drivers/usb/gadget/epautoconf.c new file mode 100644 index 0000000..7cf3c67 --- /dev/null +++ b/drivers/usb/gadget/epautoconf.c @@ -0,0 +1,305 @@ +/* + * epautoconf.c -- endpoint autoconfiguration for usb gadget drivers + * + * Copyright (C) 2004 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + +#include <common.h> +#include <linux/usb/ch9.h> +#include <asm/errno.h> +#include <linux/usb/gadget.h> +#include "gadget_chips.h" + +#define isdigit(c) ('0' <= (c) && (c) <= '9') + +/* we must assign addresses for configurable endpoints (like net2280) */ +static unsigned epnum; + +/* #define MANY_ENDPOINTS */ +#ifdef MANY_ENDPOINTS +/* more than 15 configurable endpoints */ +static unsigned in_epnum; +#endif + + +/* + * This should work with endpoints from controller drivers sharing the + * same endpoint naming convention. By example: + * + * - ep1, ep2, ... address is fixed, not direction or type + * - ep1in, ep2out, ... address and direction are fixed, not type + * - ep1-bulk, ep2-bulk, ... address and type are fixed, not direction + * - ep1in-bulk, ep2out-iso, ... all three are fixed + * - ep-* ... no functionality restrictions + * + * Type suffixes are "-bulk", "-iso", or "-int". Numbers are decimal. + * Less common restrictions are implied by gadget_is_*(). + * + * NOTE: each endpoint is unidirectional, as specified by its USB + * descriptor; and isn't specific to a configuration or altsetting. + */ +static int ep_matches( + struct usb_gadget *gadget, + struct usb_ep *ep, + struct usb_endpoint_descriptor *desc +) +{ + u8 type; + const char *tmp; + u16 max; + + /* endpoint already claimed? */ + if (NULL != ep->driver_data) + return 0; + + /* only support ep0 for portable CONTROL traffic */ + type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; + if (USB_ENDPOINT_XFER_CONTROL == type) + return 0; + + /* some other naming convention */ + if ('e' != ep->name[0]) + return 0; + + /* type-restriction: "-iso", "-bulk", or "-int". + * direction-restriction: "in", "out". + */ + if ('-' != ep->name[2]) { + tmp = strrchr(ep->name, '-'); + if (tmp) { + switch (type) { + case USB_ENDPOINT_XFER_INT: + /* bulk endpoints handle interrupt transfers, + * except the toggle-quirky iso-synch kind + */ + if ('s' == tmp[2]) /* == "-iso" */ + return 0; + /* for now, avoid PXA "interrupt-in"; + * it's documented as never using DATA1. + */ + if (gadget_is_pxa(gadget) + && 'i' == tmp[1]) + return 0; + break; + case USB_ENDPOINT_XFER_BULK: + if ('b' != tmp[1]) /* != "-bulk" */ + return 0; + break; + case USB_ENDPOINT_XFER_ISOC: + if ('s' != tmp[2]) /* != "-iso" */ + return 0; + } + } else { + tmp = ep->name + strlen(ep->name); + } + + /* direction-restriction: "..in-..", "out-.." */ + tmp--; + if (!isdigit(*tmp)) { + if (desc->bEndpointAddress & USB_DIR_IN) { + if ('n' != *tmp) + return 0; + } else { + if ('t' != *tmp) + return 0; + } + } + } + + /* endpoint maxpacket size is an input parameter, except for bulk + * where it's an output parameter representing the full speed limit. + * the usb spec fixes high speed bulk maxpacket at 512 bytes. + */ + max = 0x7ff & le16_to_cpu(desc->wMaxPacketSize); + switch (type) { + case USB_ENDPOINT_XFER_INT: + /* INT: limit 64 bytes full speed, 1024 high speed */ + if (!gadget->is_dualspeed && max > 64) + return 0; + /* FALLTHROUGH */ + + case USB_ENDPOINT_XFER_ISOC: + /* ISO: limit 1023 bytes full speed, 1024 high speed */ + if (ep->maxpacket < max) + return 0; + if (!gadget->is_dualspeed && max > 1023) + return 0; + + /* BOTH: "high bandwidth" works only at high speed */ + if ((desc->wMaxPacketSize & __constant_cpu_to_le16(3<<11))) { + if (!gadget->is_dualspeed) + return 0; + /* configure your hardware with enough buffering!! */ + } + break; + } + + /* MATCH!! */ + + /* report address */ + if (isdigit(ep->name[2])) { + u8 num = simple_strtoul(&ep->name[2], NULL, 10); + desc->bEndpointAddress |= num; +#ifdef MANY_ENDPOINTS + } else if (desc->bEndpointAddress & USB_DIR_IN) { + if (++in_epnum > 15) + return 0; + desc->bEndpointAddress = USB_DIR_IN | in_epnum; +#endif + } else { + if (++epnum > 15) + return 0; + desc->bEndpointAddress |= epnum; + } + + /* report (variable) full speed bulk maxpacket */ + if (USB_ENDPOINT_XFER_BULK == type) { + int size = ep->maxpacket; + + /* min() doesn't work on bitfields with gcc-3.5 */ + if (size > 64) + size = 64; + desc->wMaxPacketSize = cpu_to_le16(size); + } + return 1; +} + +static struct usb_ep * +find_ep(struct usb_gadget *gadget, const char *name) +{ + struct usb_ep *ep; + + list_for_each_entry(ep, &gadget->ep_list, ep_list) { + if (0 == strcmp(ep->name, name)) + return ep; + } + return NULL; +} + +/** + * usb_ep_autoconfig - choose an endpoint matching the descriptor + * @gadget: The device to which the endpoint must belong. + * @desc: Endpoint descriptor, with endpoint direction and transfer mode + * initialized. For periodic transfers, the maximum packet + * size must also be initialized. This is modified on success. + * + * By choosing an endpoint to use with the specified descriptor, this + * routine simplifies writing gadget drivers that work with multiple + * USB device controllers. The endpoint would be passed later to + * usb_ep_enable(), along with some descriptor. + * + * That second descriptor won't always be the same as the first one. + * For example, isochronous endpoints can be autoconfigured for high + * bandwidth, and then used in several lower bandwidth altsettings. + * Also, high and full speed descriptors will be different. + * + * Be sure to examine and test the results of autoconfiguration on your + * hardware. This code may not make the best choices about how to use the + * USB controller, and it can't know all the restrictions that may apply. + * Some combinations of driver and hardware won't be able to autoconfigure. + * + * On success, this returns an un-claimed usb_ep, and modifies the endpoint + * descriptor bEndpointAddress. For bulk endpoints, the wMaxPacket value + * is initialized as if the endpoint were used at full speed. To prevent + * the endpoint from being returned by a later autoconfig call, claim it + * by assigning ep->driver_data to some non-null value. + * + * On failure, this returns a null endpoint descriptor. + */ +struct usb_ep *usb_ep_autoconfig( + struct usb_gadget *gadget, + struct usb_endpoint_descriptor *desc +) +{ + struct usb_ep *ep; + u8 type; + + type = desc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK; + + /* First, apply chip-specific "best usage" knowledge. + * This might make a good usb_gadget_ops hook ... + */ + if (gadget_is_net2280(gadget) && type == USB_ENDPOINT_XFER_INT) { + /* ep-e, ep-f are PIO with only 64 byte fifos */ + ep = find_ep(gadget, "ep-e"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + ep = find_ep(gadget, "ep-f"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + + } else if (gadget_is_goku(gadget)) { + if (USB_ENDPOINT_XFER_INT == type) { + /* single buffering is enough */ + ep = find_ep(gadget, "ep3-bulk"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + } else if (USB_ENDPOINT_XFER_BULK == type + && (USB_DIR_IN & desc->bEndpointAddress)) { + /* DMA may be available */ + ep = find_ep(gadget, "ep2-bulk"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + } + + } else if (gadget_is_sh(gadget) && USB_ENDPOINT_XFER_INT == type) { + /* single buffering is enough; maybe 8 byte fifo is too */ + ep = find_ep(gadget, "ep3in-bulk"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + + } else if (gadget_is_mq11xx(gadget) && USB_ENDPOINT_XFER_INT == type) { + ep = find_ep(gadget, "ep1-bulk"); + if (ep && ep_matches(gadget, ep, desc)) + return ep; + } + + /* Second, look at endpoints until an unclaimed one looks usable */ + list_for_each_entry(ep, &gadget->ep_list, ep_list) { + if (ep_matches(gadget, ep, desc)) + return ep; + } + + /* Fail */ + return NULL; +} + +/** + * usb_ep_autoconfig_reset - reset endpoint autoconfig state + * @gadget: device for which autoconfig state will be reset + * + * Use this for devices where one configuration may need to assign + * endpoint resources very differently from the next one. It clears + * state such as ep->driver_data and the record of assigned endpoints + * used by usb_ep_autoconfig(). + */ +void usb_ep_autoconfig_reset(struct usb_gadget *gadget) +{ + struct usb_ep *ep; + + list_for_each_entry(ep, &gadget->ep_list, ep_list) { + ep->driver_data = NULL; + } +#ifdef MANY_ENDPOINTS + in_epnum = 0; +#endif + epnum = 0; +} + diff --git a/drivers/usb/gadget/ether.c b/drivers/usb/gadget/ether.c new file mode 100644 index 0000000..bc6480c --- /dev/null +++ b/drivers/usb/gadget/ether.c @@ -0,0 +1,1976 @@ +/* + * ether.c -- Ethernet gadget driver, with CDC and non-CDC options + * + * Copyright (C) 2003-2005,2008 David Brownell + * Copyright (C) 2003-2004 Robert Schwebel, Benedikt Spranger + * Copyright (C) 2008 Nokia Corporation + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/cdc.h> +#include <linux/usb/gadget.h> +#include <net.h> +#include <linux/ctype.h> + +#include "gadget_chips.h" + +#define USB_NET_NAME "usb0" + +#define atomic_read +extern struct platform_data brd; +#define spin_lock(x) +#define spin_unlock(x) + + +unsigned packet_received, packet_sent; + +#define DEV_CONFIG_CDC 1 +#define GFP_ATOMIC ((gfp_t) 0) +#define GFP_KERNEL ((gfp_t) 0) + +/* + * Ethernet gadget driver -- with CDC and non-CDC options + * Builds on hardware support for a full duplex link. + * + * CDC Ethernet is the standard USB solution for sending Ethernet frames + * using USB. Real hardware tends to use the same framing protocol but look + * different for control features. This driver strongly prefers to use + * this USB-IF standard as its open-systems interoperability solution; + * most host side USB stacks (except from Microsoft) support it. + * + * This is sometimes called "CDC ECM" (Ethernet Control Model) to support + * TLA-soup. "CDC ACM" (Abstract Control Model) is for modems, and a new + * "CDC EEM" (Ethernet Emulation Model) is starting to spread. + * + * There's some hardware that can't talk CDC ECM. We make that hardware + * implement a "minimalist" vendor-agnostic CDC core: same framing, but + * link-level setup only requires activating the configuration. Only the + * endpoint descriptors, and product/vendor IDs, are relevant; no control + * operations are available. Linux supports it, but other host operating + * systems may not. (This is a subset of CDC Ethernet.) + * + * It turns out that if you add a few descriptors to that "CDC Subset", + * (Windows) host side drivers from MCCI can treat it as one submode of + * a proprietary scheme called "SAFE" ... without needing to know about + * specific product/vendor IDs. So we do that, making it easier to use + * those MS-Windows drivers. Those added descriptors make it resemble a + * CDC MDLM device, but they don't change device behavior at all. (See + * MCCI Engineering report 950198 "SAFE Networking Functions".) + * + * A third option is also in use. Rather than CDC Ethernet, or something + * simpler, Microsoft pushes their own approach: RNDIS. The published + * RNDIS specs are ambiguous and appear to be incomplete, and are also + * needlessly complex. They borrow more from CDC ACM than CDC ECM. + */ +#define ETH_ALEN 6 /* Octets in one ethernet addr */ +#define ETH_HLEN 14 /* Total octets in header. */ +#define ETH_ZLEN 60 /* Min. octets in frame sans FCS */ +#define ETH_DATA_LEN 1500 /* Max. octets in payload */ +#define ETH_FRAME_LEN PKTSIZE_ALIGN /* Max. octets in frame sans FCS */ +#define ETH_FCS_LEN 4 /* Octets in the FCS */ + +#define DRIVER_DESC "Ethernet Gadget" +/* Based on linux 2.6.27 version */ +#define DRIVER_VERSION "May Day 2005" + +static const char shortname[] = "ether"; +static const char driver_desc[] = DRIVER_DESC; + +#define RX_EXTRA 20 /* guard against rx overflows */ + +/* CDC support the same host-chosen outgoing packet filters. */ +#define DEFAULT_FILTER (USB_CDC_PACKET_TYPE_BROADCAST \ + |USB_CDC_PACKET_TYPE_ALL_MULTICAST \ + |USB_CDC_PACKET_TYPE_PROMISCUOUS \ + |USB_CDC_PACKET_TYPE_DIRECTED) + +#define USB_CONNECT_TIMEOUT (3 * CONFIG_SYS_HZ) + +/*-------------------------------------------------------------------------*/ +static struct eth_dev l_ethdev; +static struct eth_device l_netdev; +static struct usb_gadget_driver eth_driver; + +/*-------------------------------------------------------------------------*/ + +/* "main" config is either CDC, or its simple subset */ +static inline int is_cdc(struct eth_dev *dev) +{ +#if !defined(DEV_CONFIG_SUBSET) + return 1; /* only cdc possible */ +#elif !defined(DEV_CONFIG_CDC) + return 0; /* only subset possible */ +#else + return dev->cdc; /* depends on what hardware we found */ +#endif +} + +#define subset_active(dev) (!is_cdc(dev)) +#define cdc_active(dev) (is_cdc(dev)) + +#define DEFAULT_QLEN 2 /* double buffering by default */ + +/* peak bulk transfer bits-per-second */ +#define HS_BPS (13 * 512 * 8 * 1000 * 8) +#define FS_BPS (19 * 64 * 1 * 1000 * 8) + +#ifdef CONFIG_USB_GADGET_DUALSPEED +#define DEVSPEED USB_SPEED_HIGH + +#ifdef CONFIG_USB_ETH_QMULT +#define qmult CONFIG_USB_ETH_QMULT +#else +#define qmult 5 +#endif + +/* for dual-speed hardware, use deeper queues at highspeed */ +#define qlen(gadget) \ + (DEFAULT_QLEN*((gadget->speed == USB_SPEED_HIGH) ? qmult : 1)) + +static inline int BITRATE(struct usb_gadget *g) +{ + return (g->speed == USB_SPEED_HIGH) ? HS_BPS : FS_BPS; +} + +#else /* full speed (low speed doesn't do bulk) */ + +#define qmult 1 + +#define DEVSPEED USB_SPEED_FULL + +#define qlen(gadget) DEFAULT_QLEN + +static inline int BITRATE(struct usb_gadget *g) +{ + return FS_BPS; +} +#endif + +struct eth_dev { + struct usb_gadget *gadget; + struct usb_request *req; /* for control responses */ + struct usb_request *stat_req; /* for cdc status */ + + u8 config; + struct usb_ep *in_ep, *out_ep, *status_ep; + const struct usb_endpoint_descriptor + *in, *out, *status; + + struct usb_request *tx_req, *rx_req; + + struct eth_device *net; + unsigned int tx_qlen; + + unsigned zlp:1; + unsigned cdc:1; + unsigned suspended:1; + unsigned network_started:1; + u16 cdc_filter; + unsigned long todo; + int mtu; +#define WORK_RX_MEMORY 0 + u8 host_mac[ETH_ALEN]; +}; + +/* + * This version autoconfigures as much as possible at run-time. + * + * It also ASSUMES a self-powered device, without remote wakeup, + * although remote wakeup support would make sense. + */ + +/*-------------------------------------------------------------------------*/ + +/* + * DO NOT REUSE THESE IDs with a protocol-incompatible driver!! Ever!! + * Instead: allocate your own, using normal USB-IF procedures. + */ + +/* + * Thanks to NetChip Technologies for donating this product ID. + * It's for devices with only CDC Ethernet configurations. + */ +#define CDC_VENDOR_NUM 0x0525 /* NetChip */ +#define CDC_PRODUCT_NUM 0xa4a1 /* Linux-USB Ethernet Gadget */ + +/* + * For hardware that can't talk CDC, we use the same vendor ID that + * ARM Linux has used for ethernet-over-usb, both with sa1100 and + * with pxa250. We're protocol-compatible, if the host-side drivers + * use the endpoint descriptors. bcdDevice (version) is nonzero, so + * drivers that need to hard-wire endpoint numbers have a hook. + * + * The protocol is a minimal subset of CDC Ether, which works on any bulk + * hardware that's not deeply broken ... even on hardware that can't talk + * RNDIS (like SA-1100, with no interrupt endpoint, or anything that + * doesn't handle control-OUT). + */ +#define SIMPLE_VENDOR_NUM 0x049f +#define SIMPLE_PRODUCT_NUM 0x505a + +/* + * Some systems will want different product identifers published in the + * device descriptor, either numbers or strings or both. These string + * parameters are in UTF-8 (superset of ASCII's 7 bit characters). + */ + +static ushort bcdDevice; +#if defined(CONFIG_USBNET_MANUFACTURER) +static char *iManufacturer = CONFIG_USBNET_MANUFACTURER; +#else +static char *iManufacturer = "U-boot"; +#endif +static char *iProduct; +static char *iSerialNumber; +static char dev_addr[18]; +static char host_addr[18]; + +/*-------------------------------------------------------------------------*/ + +/* + * USB DRIVER HOOKUP (to the hardware driver, below us), mostly + * ep0 implementation: descriptors, config management, setup(). + * also optional class-specific notification interrupt transfer. + */ + +/* + * DESCRIPTORS ... most are static, but strings and (full) configuration + * descriptors are built on demand. For now we do either full CDC, or + * our simple subset. + */ + +#define STRING_MANUFACTURER 1 +#define STRING_PRODUCT 2 +#define STRING_ETHADDR 3 +#define STRING_DATA 4 +#define STRING_CONTROL 5 +#define STRING_CDC 7 +#define STRING_SUBSET 8 +#define STRING_SERIALNUMBER 10 + +/* holds our biggest descriptor */ +#define USB_BUFSIZ 256 + +/* + * This device advertises one configuration, eth_config, + * on hardware supporting at least two configs. + * + * FIXME define some higher-powered configurations to make it easier + * to recharge batteries ... + */ + +#define DEV_CONFIG_VALUE 1 /* cdc or subset */ + +static struct usb_device_descriptor +device_desc = { + .bLength = sizeof device_desc, + .bDescriptorType = USB_DT_DEVICE, + + .bcdUSB = __constant_cpu_to_le16(0x0200), + + .bDeviceClass = USB_CLASS_COMM, + .bDeviceSubClass = 0, + .bDeviceProtocol = 0, + + .idVendor = __constant_cpu_to_le16(CDC_VENDOR_NUM), + .idProduct = __constant_cpu_to_le16(CDC_PRODUCT_NUM), + .iManufacturer = STRING_MANUFACTURER, + .iProduct = STRING_PRODUCT, + .bNumConfigurations = 1, +}; + +static struct usb_otg_descriptor +otg_descriptor = { + .bLength = sizeof otg_descriptor, + .bDescriptorType = USB_DT_OTG, + + .bmAttributes = USB_OTG_SRP, +}; + +static struct usb_config_descriptor +eth_config = { + .bLength = sizeof eth_config, + .bDescriptorType = USB_DT_CONFIG, + + /* compute wTotalLength on the fly */ + .bNumInterfaces = 2, + .bConfigurationValue = DEV_CONFIG_VALUE, + .iConfiguration = STRING_CDC, + .bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER, + .bMaxPower = 1, +}; + +/* + * Compared to the simple CDC subset, the full CDC Ethernet model adds + * three class descriptors, two interface descriptors, optional status + * endpoint. Both have a "data" interface and two bulk endpoints. + * There are also differences in how control requests are handled. + */ + +#ifdef DEV_CONFIG_CDC +static struct usb_interface_descriptor +control_intf = { + .bLength = sizeof control_intf, + .bDescriptorType = USB_DT_INTERFACE, + + .bInterfaceNumber = 0, + /* status endpoint is optional; this may be patched later */ + .bNumEndpoints = 1, + .bInterfaceClass = USB_CLASS_COMM, + .bInterfaceSubClass = USB_CDC_SUBCLASS_ETHERNET, + .bInterfaceProtocol = USB_CDC_PROTO_NONE, + .iInterface = STRING_CONTROL, +}; +#endif + +static const struct usb_cdc_header_desc header_desc = { + .bLength = sizeof header_desc, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubType = USB_CDC_HEADER_TYPE, + + .bcdCDC = __constant_cpu_to_le16(0x0110), +}; + +#if defined(DEV_CONFIG_CDC) + +static const struct usb_cdc_union_desc union_desc = { + .bLength = sizeof union_desc, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubType = USB_CDC_UNION_TYPE, + + .bMasterInterface0 = 0, /* index of control interface */ + .bSlaveInterface0 = 1, /* index of DATA interface */ +}; + +#endif /* CDC */ + +#ifndef DEV_CONFIG_CDC + +/* + * "SAFE" loosely follows CDC WMC MDLM, violating the spec in various + * ways: data endpoints live in the control interface, there's no data + * interface, and it's not used to talk to a cell phone radio. + */ + +static const struct usb_cdc_mdlm_desc mdlm_desc = { + .bLength = sizeof mdlm_desc, + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubType = USB_CDC_MDLM_TYPE, + + .bcdVersion = __constant_cpu_to_le16(0x0100), + .bGUID = { + 0x5d, 0x34, 0xcf, 0x66, 0x11, 0x18, 0x11, 0xd6, + 0xa2, 0x1a, 0x00, 0x01, 0x02, 0xca, 0x9a, 0x7f, + }, +}; + +/* + * since "usb_cdc_mdlm_detail_desc" is a variable length structure, we + * can't really use its struct. All we do here is say that we're using + * the submode of "SAFE" which directly matches the CDC Subset. + */ +static const u8 mdlm_detail_desc[] = { + 6, + USB_DT_CS_INTERFACE, + USB_CDC_MDLM_DETAIL_TYPE, + + 0, /* "SAFE" */ + 0, /* network control capabilities (none) */ + 0, /* network data capabilities ("raw" encapsulation) */ +}; + +#endif + +static const struct usb_cdc_ether_desc ether_desc = { + .bLength = sizeof(ether_desc), + .bDescriptorType = USB_DT_CS_INTERFACE, + .bDescriptorSubType = USB_CDC_ETHERNET_TYPE, + + /* this descriptor actually adds value, surprise! */ + .iMACAddress = STRING_ETHADDR, + .bmEthernetStatistics = __constant_cpu_to_le32(0), /* no statistics */ + .wMaxSegmentSize = __constant_cpu_to_le16(ETH_FRAME_LEN), + .wNumberMCFilters = __constant_cpu_to_le16(0), + .bNumberPowerFilters = 0, +}; + +#if defined(DEV_CONFIG_CDC) + +/* + * include the status endpoint if we can, even where it's optional. + * use wMaxPacketSize big enough to fit CDC_NOTIFY_SPEED_CHANGE in one + * packet, to simplify cancellation; and a big transfer interval, to + * waste less bandwidth. + * + * some drivers (like Linux 2.4 cdc-ether!) "need" it to exist even + * if they ignore the connect/disconnect notifications that real aether + * can provide. more advanced cdc configurations might want to support + * encapsulated commands (vendor-specific, using control-OUT). + */ + +#define LOG2_STATUS_INTERVAL_MSEC 5 /* 1 << 5 == 32 msec */ +#define STATUS_BYTECOUNT 16 /* 8 byte header + data */ + +static struct usb_endpoint_descriptor +fs_status_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = __constant_cpu_to_le16(STATUS_BYTECOUNT), + .bInterval = 1 << LOG2_STATUS_INTERVAL_MSEC, +}; +#endif + +#ifdef DEV_CONFIG_CDC + +/* the default data interface has no endpoints ... */ + +static const struct usb_interface_descriptor +data_nop_intf = { + .bLength = sizeof data_nop_intf, + .bDescriptorType = USB_DT_INTERFACE, + + .bInterfaceNumber = 1, + .bAlternateSetting = 0, + .bNumEndpoints = 0, + .bInterfaceClass = USB_CLASS_CDC_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, +}; + +/* ... but the "real" data interface has two bulk endpoints */ + +static const struct usb_interface_descriptor +data_intf = { + .bLength = sizeof data_intf, + .bDescriptorType = USB_DT_INTERFACE, + + .bInterfaceNumber = 1, + .bAlternateSetting = 1, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_CDC_DATA, + .bInterfaceSubClass = 0, + .bInterfaceProtocol = 0, + .iInterface = STRING_DATA, +}; + +#endif + +#ifdef DEV_CONFIG_SUBSET + +/* + * "Simple" CDC-subset option is a simple vendor-neutral model that most + * full speed controllers can handle: one interface, two bulk endpoints. + * + * To assist host side drivers, we fancy it up a bit, and add descriptors + * so some host side drivers will understand it as a "SAFE" variant. + */ + +static const struct usb_interface_descriptor +subset_data_intf = { + .bLength = sizeof subset_data_intf, + .bDescriptorType = USB_DT_INTERFACE, + + .bInterfaceNumber = 0, + .bAlternateSetting = 0, + .bNumEndpoints = 2, + .bInterfaceClass = USB_CLASS_COMM, + .bInterfaceSubClass = USB_CDC_SUBCLASS_MDLM, + .bInterfaceProtocol = 0, + .iInterface = STRING_DATA, +}; + +#endif /* SUBSET */ + +static struct usb_endpoint_descriptor +fs_source_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_IN, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +static struct usb_endpoint_descriptor +fs_sink_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bEndpointAddress = USB_DIR_OUT, + .bmAttributes = USB_ENDPOINT_XFER_BULK, +}; + +static const struct usb_descriptor_header *fs_eth_function[11] = { + (struct usb_descriptor_header *) &otg_descriptor, +#ifdef DEV_CONFIG_CDC + /* "cdc" mode descriptors */ + (struct usb_descriptor_header *) &control_intf, + (struct usb_descriptor_header *) &header_desc, + (struct usb_descriptor_header *) &union_desc, + (struct usb_descriptor_header *) ðer_desc, + /* NOTE: status endpoint may need to be removed */ + (struct usb_descriptor_header *) &fs_status_desc, + /* data interface, with altsetting */ + (struct usb_descriptor_header *) &data_nop_intf, + (struct usb_descriptor_header *) &data_intf, + (struct usb_descriptor_header *) &fs_source_desc, + (struct usb_descriptor_header *) &fs_sink_desc, + NULL, +#endif /* DEV_CONFIG_CDC */ +}; + +static inline void fs_subset_descriptors(void) +{ +#ifdef DEV_CONFIG_SUBSET + /* behavior is "CDC Subset"; extra descriptors say "SAFE" */ + fs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf; + fs_eth_function[2] = (struct usb_descriptor_header *) &header_desc; + fs_eth_function[3] = (struct usb_descriptor_header *) &mdlm_desc; + fs_eth_function[4] = (struct usb_descriptor_header *) &mdlm_detail_desc; + fs_eth_function[5] = (struct usb_descriptor_header *) ðer_desc; + fs_eth_function[6] = (struct usb_descriptor_header *) &fs_source_desc; + fs_eth_function[7] = (struct usb_descriptor_header *) &fs_sink_desc; + fs_eth_function[8] = NULL; +#else + fs_eth_function[1] = NULL; +#endif +} + +/* + * usb 2.0 devices need to expose both high speed and full speed + * descriptors, unless they only run at full speed. + */ + +#if defined(DEV_CONFIG_CDC) +static struct usb_endpoint_descriptor +hs_status_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_INT, + .wMaxPacketSize = __constant_cpu_to_le16(STATUS_BYTECOUNT), + .bInterval = LOG2_STATUS_INTERVAL_MSEC + 4, +}; +#endif /* DEV_CONFIG_CDC */ + +static struct usb_endpoint_descriptor +hs_source_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_endpoint_descriptor +hs_sink_desc = { + .bLength = USB_DT_ENDPOINT_SIZE, + .bDescriptorType = USB_DT_ENDPOINT, + + .bmAttributes = USB_ENDPOINT_XFER_BULK, + .wMaxPacketSize = __constant_cpu_to_le16(512), +}; + +static struct usb_qualifier_descriptor +dev_qualifier = { + .bLength = sizeof dev_qualifier, + .bDescriptorType = USB_DT_DEVICE_QUALIFIER, + + .bcdUSB = __constant_cpu_to_le16(0x0200), + .bDeviceClass = USB_CLASS_COMM, + + .bNumConfigurations = 1, +}; + +static const struct usb_descriptor_header *hs_eth_function[11] = { + (struct usb_descriptor_header *) &otg_descriptor, +#ifdef DEV_CONFIG_CDC + /* "cdc" mode descriptors */ + (struct usb_descriptor_header *) &control_intf, + (struct usb_descriptor_header *) &header_desc, + (struct usb_descriptor_header *) &union_desc, + (struct usb_descriptor_header *) ðer_desc, + /* NOTE: status endpoint may need to be removed */ + (struct usb_descriptor_header *) &hs_status_desc, + /* data interface, with altsetting */ + (struct usb_descriptor_header *) &data_nop_intf, + (struct usb_descriptor_header *) &data_intf, + (struct usb_descriptor_header *) &hs_source_desc, + (struct usb_descriptor_header *) &hs_sink_desc, + NULL, +#endif /* DEV_CONFIG_CDC */ +}; + +static inline void hs_subset_descriptors(void) +{ +#ifdef DEV_CONFIG_SUBSET + /* behavior is "CDC Subset"; extra descriptors say "SAFE" */ + hs_eth_function[1] = (struct usb_descriptor_header *) &subset_data_intf; + hs_eth_function[2] = (struct usb_descriptor_header *) &header_desc; + hs_eth_function[3] = (struct usb_descriptor_header *) &mdlm_desc; + hs_eth_function[4] = (struct usb_descriptor_header *) &mdlm_detail_desc; + hs_eth_function[5] = (struct usb_descriptor_header *) ðer_desc; + hs_eth_function[6] = (struct usb_descriptor_header *) &hs_source_desc; + hs_eth_function[7] = (struct usb_descriptor_header *) &hs_sink_desc; + hs_eth_function[8] = NULL; +#else + hs_eth_function[1] = NULL; +#endif +} + +/* maxpacket and other transfer characteristics vary by speed. */ +static inline struct usb_endpoint_descriptor * +ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *hs, + struct usb_endpoint_descriptor *fs) +{ + if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH) + return hs; + return fs; +} + +/*-------------------------------------------------------------------------*/ + +/* descriptors that are built on-demand */ + +static char manufacturer[50]; +static char product_desc[40] = DRIVER_DESC; +static char serial_number[20]; + +/* address that the host will use ... usually assigned at random */ +static char ethaddr[2 * ETH_ALEN + 1]; + +/* static strings, in UTF-8 */ +static struct usb_string strings[] = { + { STRING_MANUFACTURER, manufacturer, }, + { STRING_PRODUCT, product_desc, }, + { STRING_SERIALNUMBER, serial_number, }, + { STRING_DATA, "Ethernet Data", }, + { STRING_ETHADDR, ethaddr, }, +#ifdef DEV_CONFIG_CDC + { STRING_CDC, "CDC Ethernet", }, + { STRING_CONTROL, "CDC Communications Control", }, +#endif +#ifdef DEV_CONFIG_SUBSET + { STRING_SUBSET, "CDC Ethernet Subset", }, +#endif + { } /* end of list */ +}; + +static struct usb_gadget_strings stringtab = { + .language = 0x0409, /* en-us */ + .strings = strings, +}; + +/*============================================================================*/ +static u8 control_req[USB_BUFSIZ]; +static u8 status_req[STATUS_BYTECOUNT] __attribute__ ((aligned(4))); + + +/** + * strlcpy - Copy a %NUL terminated string into a sized buffer + * @dest: Where to copy the string to + * @src: Where to copy the string from + * @size: size of destination buffer + * + * Compatible with *BSD: the result is always a valid + * NUL-terminated string that fits in the buffer (unless, + * of course, the buffer size is zero). It does not pad + * out the result like strncpy() does. + */ +size_t strlcpy(char *dest, const char *src, size_t size) +{ + size_t ret = strlen(src); + + if (size) { + size_t len = (ret >= size) ? size - 1 : ret; + memcpy(dest, src, len); + dest[len] = '\0'; + } + return ret; +} + +/*============================================================================*/ + +/* + * one config, two interfaces: control, data. + * complications: class descriptors, and an altsetting. + */ +static int +config_buf(struct usb_gadget *g, u8 *buf, u8 type, unsigned index, int is_otg) +{ + int len; + const struct usb_config_descriptor *config; + const struct usb_descriptor_header **function; + int hs = 0; + + if (gadget_is_dualspeed(g)) { + hs = (g->speed == USB_SPEED_HIGH); + if (type == USB_DT_OTHER_SPEED_CONFIG) + hs = !hs; + } +#define which_fn(t) (hs ? hs_ ## t ## _function : fs_ ## t ## _function) + + if (index >= device_desc.bNumConfigurations) + return -EINVAL; + + config = ð_config; + function = which_fn(eth); + + /* for now, don't advertise srp-only devices */ + if (!is_otg) + function++; + + len = usb_gadget_config_buf(config, buf, USB_BUFSIZ, function); + if (len < 0) + return len; + ((struct usb_config_descriptor *) buf)->bDescriptorType = type; + return len; +} + +/*-------------------------------------------------------------------------*/ + +static int alloc_requests(struct eth_dev *dev, unsigned n, gfp_t gfp_flags); + +static int +set_ether_config(struct eth_dev *dev, gfp_t gfp_flags) +{ + int result = 0; + struct usb_gadget *gadget = dev->gadget; + +#if defined(DEV_CONFIG_CDC) + /* status endpoint used for (optionally) CDC */ + if (!subset_active(dev) && dev->status_ep) { + dev->status = ep_desc(gadget, &hs_status_desc, + &fs_status_desc); + dev->status_ep->driver_data = dev; + + result = usb_ep_enable(dev->status_ep, dev->status); + if (result != 0) { + debug("enable %s --> %d\n", + dev->status_ep->name, result); + goto done; + } + } +#endif + + dev->in = ep_desc(gadget, &hs_source_desc, &fs_source_desc); + dev->in_ep->driver_data = dev; + + dev->out = ep_desc(gadget, &hs_sink_desc, &fs_sink_desc); + dev->out_ep->driver_data = dev; + + /* + * With CDC, the host isn't allowed to use these two data + * endpoints in the default altsetting for the interface. + * so we don't activate them yet. Reset from SET_INTERFACE. + */ + if (!cdc_active(dev)) { + result = usb_ep_enable(dev->in_ep, dev->in); + if (result != 0) { + debug("enable %s --> %d\n", + dev->in_ep->name, result); + goto done; + } + + result = usb_ep_enable(dev->out_ep, dev->out); + if (result != 0) { + debug("enable %s --> %d\n", + dev->out_ep->name, result); + goto done; + } + } + +done: + if (result == 0) + result = alloc_requests(dev, qlen(gadget), gfp_flags); + + /* on error, disable any endpoints */ + if (result < 0) { + if (!subset_active(dev) && dev->status_ep) + (void) usb_ep_disable(dev->status_ep); + dev->status = NULL; + (void) usb_ep_disable(dev->in_ep); + (void) usb_ep_disable(dev->out_ep); + dev->in = NULL; + dev->out = NULL; + } + + /* caller is responsible for cleanup on error */ + return result; +} + +static void eth_reset_config(struct eth_dev *dev) +{ + if (dev->config == 0) + return; + + debug("%s\n", __func__); + + /* + * disable endpoints, forcing (synchronous) completion of + * pending i/o. then free the requests. + */ + + if (dev->in) { + usb_ep_disable(dev->in_ep); + if (dev->tx_req) { + usb_ep_free_request(dev->in_ep, dev->tx_req); + dev->tx_req = NULL; + } + } + if (dev->out) { + usb_ep_disable(dev->out_ep); + if (dev->rx_req) { + usb_ep_free_request(dev->out_ep, dev->rx_req); + dev->rx_req = NULL; + } + } + if (dev->status) + usb_ep_disable(dev->status_ep); + + dev->cdc_filter = 0; + dev->config = 0; +} + +/* + * change our operational config. must agree with the code + * that returns config descriptors, and altsetting code. + */ +static int eth_set_config(struct eth_dev *dev, unsigned number, + gfp_t gfp_flags) +{ + int result = 0; + struct usb_gadget *gadget = dev->gadget; + + if (gadget_is_sa1100(gadget) + && dev->config + && dev->tx_qlen != 0) { + /* tx fifo is full, but we can't clear it...*/ + error("can't change configurations"); + return -ESPIPE; + } + eth_reset_config(dev); + + switch (number) { + case DEV_CONFIG_VALUE: + result = set_ether_config(dev, gfp_flags); + break; + default: + result = -EINVAL; + /* FALL THROUGH */ + case 0: + break; + } + + if (result) { + if (number) + eth_reset_config(dev); + usb_gadget_vbus_draw(dev->gadget, + gadget_is_otg(dev->gadget) ? 8 : 100); + } else { + char *speed; + unsigned power; + + power = 2 * eth_config.bMaxPower; + usb_gadget_vbus_draw(dev->gadget, power); + + switch (gadget->speed) { + case USB_SPEED_FULL: + speed = "full"; break; +#ifdef CONFIG_USB_GADGET_DUALSPEED + case USB_SPEED_HIGH: + speed = "high"; break; +#endif + default: + speed = "?"; break; + } + + dev->config = number; + printf("%s speed config #%d: %d mA, %s, using %s\n", + speed, number, power, driver_desc, + (cdc_active(dev) ? "CDC Ethernet" + : "CDC Ethernet Subset")); + } + return result; +} + +/*-------------------------------------------------------------------------*/ + +#ifdef DEV_CONFIG_CDC + +/* + * The interrupt endpoint is used in CDC networking models (Ethernet, ATM) + * only to notify the host about link status changes (which we support) or + * report completion of some encapsulated command. Since + * we want this CDC Ethernet code to be vendor-neutral, we don't use that + * command mechanism; and only one status request is ever queued. + */ +static void eth_status_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct usb_cdc_notification *event = req->buf; + int value = req->status; + struct eth_dev *dev = ep->driver_data; + + /* issue the second notification if host reads the first */ + if (event->bNotificationType == USB_CDC_NOTIFY_NETWORK_CONNECTION + && value == 0) { + __le32 *data = req->buf + sizeof *event; + + event->bmRequestType = 0xA1; + event->bNotificationType = USB_CDC_NOTIFY_SPEED_CHANGE; + event->wValue = __constant_cpu_to_le16(0); + event->wIndex = __constant_cpu_to_le16(1); + event->wLength = __constant_cpu_to_le16(8); + + /* SPEED_CHANGE data is up/down speeds in bits/sec */ + data[0] = data[1] = cpu_to_le32(BITRATE(dev->gadget)); + + req->length = STATUS_BYTECOUNT; + value = usb_ep_queue(ep, req, GFP_ATOMIC); + debug("send SPEED_CHANGE --> %d\n", value); + if (value == 0) + return; + } else if (value != -ECONNRESET) { + debug("event %02x --> %d\n", + event->bNotificationType, value); + if (event->bNotificationType == + USB_CDC_NOTIFY_SPEED_CHANGE) { + l_ethdev.network_started = 1; + printf("USB network up!\n"); + } + } + req->context = NULL; +} + +static void issue_start_status(struct eth_dev *dev) +{ + struct usb_request *req = dev->stat_req; + struct usb_cdc_notification *event; + int value; + + /* + * flush old status + * + * FIXME ugly idiom, maybe we'd be better with just + * a "cancel the whole queue" primitive since any + * unlink-one primitive has way too many error modes. + * here, we "know" toggle is already clear... + * + * FIXME iff req->context != null just dequeue it + */ + usb_ep_disable(dev->status_ep); + usb_ep_enable(dev->status_ep, dev->status); + + /* + * 3.8.1 says to issue first NETWORK_CONNECTION, then + * a SPEED_CHANGE. could be useful in some configs. + */ + event = req->buf; + event->bmRequestType = 0xA1; + event->bNotificationType = USB_CDC_NOTIFY_NETWORK_CONNECTION; + event->wValue = __constant_cpu_to_le16(1); /* connected */ + event->wIndex = __constant_cpu_to_le16(1); + event->wLength = 0; + + req->length = sizeof *event; + req->complete = eth_status_complete; + req->context = dev; + + value = usb_ep_queue(dev->status_ep, req, GFP_ATOMIC); + if (value < 0) + debug("status buf queue --> %d\n", value); +} + +#endif + +/*-------------------------------------------------------------------------*/ + +static void eth_setup_complete(struct usb_ep *ep, struct usb_request *req) +{ + if (req->status || req->actual != req->length) + debug("setup complete --> %d, %d/%d\n", + req->status, req->actual, req->length); +} + +/* + * The setup() callback implements all the ep0 functionality that's not + * handled lower down. CDC has a number of less-common features: + * + * - two interfaces: control, and ethernet data + * - Ethernet data interface has two altsettings: default, and active + * - class-specific descriptors for the control interface + * - class-specific control requests + */ +static int +eth_setup(struct usb_gadget *gadget, const struct usb_ctrlrequest *ctrl) +{ + struct eth_dev *dev = get_gadget_data(gadget); + struct usb_request *req = dev->req; + int value = -EOPNOTSUPP; + u16 wIndex = le16_to_cpu(ctrl->wIndex); + u16 wValue = le16_to_cpu(ctrl->wValue); + u16 wLength = le16_to_cpu(ctrl->wLength); + + /* + * descriptors just go into the pre-allocated ep0 buffer, + * while config change events may enable network traffic. + */ + + debug("%s\n", __func__); + + req->complete = eth_setup_complete; + switch (ctrl->bRequest) { + + case USB_REQ_GET_DESCRIPTOR: + if (ctrl->bRequestType != USB_DIR_IN) + break; + switch (wValue >> 8) { + + case USB_DT_DEVICE: + value = min(wLength, (u16) sizeof device_desc); + memcpy(req->buf, &device_desc, value); + break; + case USB_DT_DEVICE_QUALIFIER: + if (!gadget_is_dualspeed(gadget)) + break; + value = min(wLength, (u16) sizeof dev_qualifier); + memcpy(req->buf, &dev_qualifier, value); + break; + + case USB_DT_OTHER_SPEED_CONFIG: + if (!gadget_is_dualspeed(gadget)) + break; + /* FALLTHROUGH */ + case USB_DT_CONFIG: + value = config_buf(gadget, req->buf, + wValue >> 8, + wValue & 0xff, + gadget_is_otg(gadget)); + if (value >= 0) + value = min(wLength, (u16) value); + break; + + case USB_DT_STRING: + value = usb_gadget_get_string(&stringtab, + wValue & 0xff, req->buf); + + if (value >= 0) + value = min(wLength, (u16) value); + + break; + } + break; + + case USB_REQ_SET_CONFIGURATION: + if (ctrl->bRequestType != 0) + break; + if (gadget->a_hnp_support) + debug("HNP available\n"); + else if (gadget->a_alt_hnp_support) + debug("HNP needs a different root port\n"); + value = eth_set_config(dev, wValue, GFP_ATOMIC); + break; + case USB_REQ_GET_CONFIGURATION: + if (ctrl->bRequestType != USB_DIR_IN) + break; + *(u8 *)req->buf = dev->config; + value = min(wLength, (u16) 1); + break; + + case USB_REQ_SET_INTERFACE: + if (ctrl->bRequestType != USB_RECIP_INTERFACE + || !dev->config + || wIndex > 1) + break; + if (!cdc_active(dev) && wIndex != 0) + break; + + /* + * PXA hardware partially handles SET_INTERFACE; + * we need to kluge around that interference. + */ + if (gadget_is_pxa(gadget)) { + value = eth_set_config(dev, DEV_CONFIG_VALUE, + GFP_ATOMIC); + goto done_set_intf; + } + +#ifdef DEV_CONFIG_CDC + switch (wIndex) { + case 0: /* control/master intf */ + if (wValue != 0) + break; + if (dev->status) { + usb_ep_disable(dev->status_ep); + usb_ep_enable(dev->status_ep, dev->status); + } + value = 0; + break; + case 1: /* data intf */ + if (wValue > 1) + break; + usb_ep_disable(dev->in_ep); + usb_ep_disable(dev->out_ep); + + /* + * CDC requires the data transfers not be done from + * the default interface setting ... also, setting + * the non-default interface resets filters etc. + */ + if (wValue == 1) { + if (!cdc_active(dev)) + break; + usb_ep_enable(dev->in_ep, dev->in); + usb_ep_enable(dev->out_ep, dev->out); + dev->cdc_filter = DEFAULT_FILTER; + if (dev->status) + issue_start_status(dev); + } + + value = 0; + break; + } +#else + /* + * FIXME this is wrong, as is the assumption that + * all non-PXA hardware talks real CDC ... + */ + debug("set_interface ignored!\n"); +#endif /* DEV_CONFIG_CDC */ + +done_set_intf: + break; + case USB_REQ_GET_INTERFACE: + if (ctrl->bRequestType != (USB_DIR_IN|USB_RECIP_INTERFACE) + || !dev->config + || wIndex > 1) + break; + if (!(cdc_active(dev)) && wIndex != 0) + break; + + /* for CDC, iff carrier is on, data interface is active. */ + if (wIndex != 1) + *(u8 *)req->buf = 0; + else { + /* *(u8 *)req->buf = netif_carrier_ok (dev->net) ? 1 : 0; */ + /* carrier always ok ...*/ + *(u8 *)req->buf = 1 ; + } + value = min(wLength, (u16) 1); + break; + +#ifdef DEV_CONFIG_CDC + case USB_CDC_SET_ETHERNET_PACKET_FILTER: + /* + * see 6.2.30: no data, wIndex = interface, + * wValue = packet filter bitmap + */ + if (ctrl->bRequestType != (USB_TYPE_CLASS|USB_RECIP_INTERFACE) + || !cdc_active(dev) + || wLength != 0 + || wIndex > 1) + break; + debug("packet filter %02x\n", wValue); + dev->cdc_filter = wValue; + value = 0; + break; + + /* + * and potentially: + * case USB_CDC_SET_ETHERNET_MULTICAST_FILTERS: + * case USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER: + * case USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER: + * case USB_CDC_GET_ETHERNET_STATISTIC: + */ + +#endif /* DEV_CONFIG_CDC */ + + default: + debug("unknown control req%02x.%02x v%04x i%04x l%d\n", + ctrl->bRequestType, ctrl->bRequest, + wValue, wIndex, wLength); + } + + /* respond with data transfer before status phase? */ + if (value >= 0) { + debug("respond with data transfer before status phase\n"); + req->length = value; + req->zero = value < wLength + && (value % gadget->ep0->maxpacket) == 0; + value = usb_ep_queue(gadget->ep0, req, GFP_ATOMIC); + if (value < 0) { + debug("ep_queue --> %d\n", value); + req->status = 0; + eth_setup_complete(gadget->ep0, req); + } + } + + /* host either stalls (value < 0) or reports success */ + return value; +} + +/*-------------------------------------------------------------------------*/ + +static void rx_complete(struct usb_ep *ep, struct usb_request *req); + +static int rx_submit(struct eth_dev *dev, struct usb_request *req, + gfp_t gfp_flags) +{ + int retval = -ENOMEM; + size_t size; + + /* + * Padding up to RX_EXTRA handles minor disagreements with host. + * Normally we use the USB "terminate on short read" convention; + * so allow up to (N*maxpacket), since that memory is normally + * already allocated. Some hardware doesn't deal well with short + * reads (e.g. DMA must be N*maxpacket), so for now don't trim a + * byte off the end (to force hardware errors on overflow). + */ + + debug("%s\n", __func__); + + size = (ETHER_HDR_SIZE + dev->mtu + RX_EXTRA); + size += dev->out_ep->maxpacket - 1; + size -= size % dev->out_ep->maxpacket; + + /* + * Some platforms perform better when IP packets are aligned, + * but on at least one, checksumming fails otherwise. + */ + + req->buf = (u8 *) NetRxPackets[0]; + req->length = size; + req->complete = rx_complete; + + retval = usb_ep_queue(dev->out_ep, req, gfp_flags); + + if (retval) + error("rx submit --> %d", retval); + + return retval; +} + +static void rx_complete(struct usb_ep *ep, struct usb_request *req) +{ + struct eth_dev *dev = ep->driver_data; + + debug("%s: status %d\n", __func__, req->status); + + packet_received = 1; + + if (req) + dev->rx_req = req; +} + +static int alloc_requests(struct eth_dev *dev, unsigned n, gfp_t gfp_flags) +{ + + dev->tx_req = usb_ep_alloc_request(dev->in_ep, 0); + + if (!dev->tx_req) + goto fail; + + dev->rx_req = usb_ep_alloc_request(dev->out_ep, 0); + + if (!dev->rx_req) + goto fail; + + return 0; + +fail: + error("can't alloc requests"); + return -1; +} + +static void tx_complete(struct usb_ep *ep, struct usb_request *req) +{ + debug("%s: status %s\n", __func__, (req->status) ? "failed" : "ok"); + packet_sent = 1; +} + +static inline int eth_is_promisc(struct eth_dev *dev) +{ + /* no filters for the CDC subset; always promisc */ + if (subset_active(dev)) + return 1; + return dev->cdc_filter & USB_CDC_PACKET_TYPE_PROMISCUOUS; +} + +#if 0 +static int eth_start_xmit (struct sk_buff *skb, struct net_device *net) +{ + struct eth_dev *dev = netdev_priv(net); + int length = skb->len; + int retval; + struct usb_request *req = NULL; + unsigned long flags; + + /* apply outgoing CDC or RNDIS filters */ + if (!eth_is_promisc (dev)) { + u8 *dest = skb->data; + + if (is_multicast_ether_addr(dest)) { + u16 type; + + /* ignores USB_CDC_PACKET_TYPE_MULTICAST and host + * SET_ETHERNET_MULTICAST_FILTERS requests + */ + if (is_broadcast_ether_addr(dest)) + type = USB_CDC_PACKET_TYPE_BROADCAST; + else + type = USB_CDC_PACKET_TYPE_ALL_MULTICAST; + if (!(dev->cdc_filter & type)) { + dev_kfree_skb_any (skb); + return 0; + } + } + /* ignores USB_CDC_PACKET_TYPE_DIRECTED */ + } + + spin_lock_irqsave(&dev->req_lock, flags); + /* + * this freelist can be empty if an interrupt triggered disconnect() + * and reconfigured the gadget (shutting down this queue) after the + * network stack decided to xmit but before we got the spinlock. + */ + if (list_empty(&dev->tx_reqs)) { + spin_unlock_irqrestore(&dev->req_lock, flags); + return 1; + } + + req = container_of (dev->tx_reqs.next, struct usb_request, list); + list_del (&req->list); + + /* temporarily stop TX queue when the freelist empties */ + if (list_empty (&dev->tx_reqs)) + netif_stop_queue (net); + spin_unlock_irqrestore(&dev->req_lock, flags); + + /* no buffer copies needed, unless the network stack did it + * or the hardware can't use skb buffers. + * or there's not enough space for any RNDIS headers we need + */ + if (rndis_active(dev)) { + struct sk_buff *skb_rndis; + + skb_rndis = skb_realloc_headroom (skb, + sizeof (struct rndis_packet_msg_type)); + if (!skb_rndis) + goto drop; + + dev_kfree_skb_any (skb); + skb = skb_rndis; + rndis_add_hdr (skb); + length = skb->len; + } + req->buf = skb->data; + req->context = skb; + req->complete = tx_complete; + + /* use zlp framing on tx for strict CDC-Ether conformance, + * though any robust network rx path ignores extra padding. + * and some hardware doesn't like to write zlps. + */ + req->zero = 1; + if (!dev->zlp && (length % dev->in_ep->maxpacket) == 0) + length++; + + req->length = length; + + /* throttle highspeed IRQ rate back slightly */ + if (gadget_is_dualspeed(dev->gadget)) + req->no_interrupt = (dev->gadget->speed == USB_SPEED_HIGH) + ? ((atomic_read(&dev->tx_qlen) % qmult) != 0) + : 0; + + retval = usb_ep_queue (dev->in_ep, req, GFP_ATOMIC); + switch (retval) { + default: + DEBUG (dev, "tx queue err %d\n", retval); + break; + case 0: + net->trans_start = jiffies; + atomic_inc (&dev->tx_qlen); + } + + if (retval) { +drop: + dev->stats.tx_dropped++; + dev_kfree_skb_any (skb); + spin_lock_irqsave(&dev->req_lock, flags); + if (list_empty (&dev->tx_reqs)) + netif_start_queue (net); + list_add (&req->list, &dev->tx_reqs); + spin_unlock_irqrestore(&dev->req_lock, flags); + } + return 0; +} + +/*-------------------------------------------------------------------------*/ +#endif + +static void eth_unbind(struct usb_gadget *gadget) +{ + struct eth_dev *dev = get_gadget_data(gadget); + + debug("%s...\n", __func__); + + /* we've already been disconnected ... no i/o is active */ + if (dev->req) { + usb_ep_free_request(gadget->ep0, dev->req); + dev->req = NULL; + } + if (dev->stat_req) { + usb_ep_free_request(dev->status_ep, dev->stat_req); + dev->stat_req = NULL; + } + + if (dev->tx_req) { + usb_ep_free_request(dev->in_ep, dev->tx_req); + dev->tx_req = NULL; + } + + if (dev->rx_req) { + usb_ep_free_request(dev->out_ep, dev->rx_req); + dev->rx_req = NULL; + } + +/* unregister_netdev (dev->net);*/ +/* free_netdev(dev->net);*/ + + set_gadget_data(gadget, NULL); +} + +static void eth_disconnect(struct usb_gadget *gadget) +{ + eth_reset_config(get_gadget_data(gadget)); +} + +static void eth_suspend(struct usb_gadget *gadget) +{ + /* Not used */ +} + +static void eth_resume(struct usb_gadget *gadget) +{ + /* Not used */ +} + +/*-------------------------------------------------------------------------*/ + +static int is_eth_addr_valid(char *str) +{ + if (strlen(str) == 17) { + int i; + char *p, *q; + uchar ea[6]; + + /* see if it looks like an ethernet address */ + + p = str; + + for (i = 0; i < 6; i++) { + char term = (i == 5 ? '\0' : ':'); + + ea[i] = simple_strtol(p, &q, 16); + + if ((q - p) != 2 || *q++ != term) + break; + + p = q; + } + + if (i == 6) /* it looks ok */ + return 1; + } + return 0; +} + +static u8 nibble(unsigned char c) +{ + if (likely(isdigit(c))) + return c - '0'; + c = toupper(c); + if (likely(isxdigit(c))) + return 10 + c - 'A'; + return 0; +} + +static int get_ether_addr(const char *str, u8 *dev_addr) +{ + if (str) { + unsigned i; + + for (i = 0; i < 6; i++) { + unsigned char num; + + if ((*str == '.') || (*str == ':')) + str++; + num = nibble(*str++) << 4; + num |= (nibble(*str++)); + dev_addr[i] = num; + } + if (is_valid_ether_addr(dev_addr)) + return 0; + } + return 1; +} + +static int eth_bind(struct usb_gadget *gadget) +{ + struct eth_dev *dev = &l_ethdev; + u8 cdc = 1, zlp = 1; + struct usb_ep *in_ep, *out_ep, *status_ep = NULL; + int gcnum; + u8 tmp[7]; + + /* these flags are only ever cleared; compiler take note */ +#ifndef DEV_CONFIG_CDC + cdc = 0; +#endif + /* + * Because most host side USB stacks handle CDC Ethernet, that + * standard protocol is _strongly_ preferred for interop purposes. + * (By everyone except Microsoft.) + */ + if (gadget_is_pxa(gadget)) { + /* pxa doesn't support altsettings */ + cdc = 0; + } else if (gadget_is_musbhdrc(gadget)) { + /* reduce tx dma overhead by avoiding special cases */ + zlp = 0; + } else if (gadget_is_sh(gadget)) { + /* sh doesn't support multiple interfaces or configs */ + cdc = 0; + } else if (gadget_is_sa1100(gadget)) { + /* hardware can't write zlps */ + zlp = 0; + /* + * sa1100 CAN do CDC, without status endpoint ... we use + * non-CDC to be compatible with ARM Linux-2.4 "usb-eth". + */ + cdc = 0; + } + + gcnum = usb_gadget_controller_number(gadget); + if (gcnum >= 0) + device_desc.bcdDevice = cpu_to_le16(0x0300 + gcnum); + else { + /* + * can't assume CDC works. don't want to default to + * anything less functional on CDC-capable hardware, + * so we fail in this case. + */ + error("controller '%s' not recognized", + gadget->name); + return -ENODEV; + } + + /* + * CDC subset ... recognized by Linux since 2.4.10, but Windows + * drivers aren't widely available. (That may be improved by + * supporting one submode of the "SAFE" variant of MDLM.) + */ + if (!cdc) { + device_desc.idVendor = + __constant_cpu_to_le16(SIMPLE_VENDOR_NUM); + device_desc.idProduct = + __constant_cpu_to_le16(SIMPLE_PRODUCT_NUM); + } + + /* support optional vendor/distro customization */ +#if defined(CONFIG_USB_CDC_VENDOR_ID) && defined(CONFIG_USB_CDC_PRODUCT_ID) + device_desc.idVendor = cpu_to_le16(CONFIG_USB_CDC_VENDOR_ID); + device_desc.idProduct = cpu_to_le16(CONFIG_USB_CDC_PRODUCT_ID); +#endif + if (bcdDevice) + device_desc.bcdDevice = cpu_to_le16(bcdDevice); + if (iManufacturer) + strlcpy(manufacturer, iManufacturer, sizeof manufacturer); + if (iProduct) + strlcpy(product_desc, iProduct, sizeof product_desc); + if (iSerialNumber) { + device_desc.iSerialNumber = STRING_SERIALNUMBER, + strlcpy(serial_number, iSerialNumber, sizeof serial_number); + } + + /* all we really need is bulk IN/OUT */ + usb_ep_autoconfig_reset(gadget); + in_ep = usb_ep_autoconfig(gadget, &fs_source_desc); + if (!in_ep) { +autoconf_fail: + error("can't autoconfigure on %s\n", + gadget->name); + return -ENODEV; + } + in_ep->driver_data = in_ep; /* claim */ + + out_ep = usb_ep_autoconfig(gadget, &fs_sink_desc); + if (!out_ep) + goto autoconf_fail; + out_ep->driver_data = out_ep; /* claim */ + +#if defined(DEV_CONFIG_CDC) + /* + * CDC Ethernet control interface doesn't require a status endpoint. + * Since some hosts expect one, try to allocate one anyway. + */ + if (cdc) { + status_ep = usb_ep_autoconfig(gadget, &fs_status_desc); + if (status_ep) { + status_ep->driver_data = status_ep; /* claim */ + } else if (cdc) { + control_intf.bNumEndpoints = 0; + /* FIXME remove endpoint from descriptor list */ + } + } +#endif + + /* one config: cdc, else minimal subset */ + if (!cdc) { + eth_config.bNumInterfaces = 1; + eth_config.iConfiguration = STRING_SUBSET; + + /* + * use functions to set these up, in case we're built to work + * with multiple controllers and must override CDC Ethernet. + */ + fs_subset_descriptors(); + hs_subset_descriptors(); + } + + device_desc.bMaxPacketSize0 = gadget->ep0->maxpacket; + usb_gadget_set_selfpowered(gadget); + + if (gadget_is_dualspeed(gadget)) { + if (!cdc) + dev_qualifier.bDeviceClass = USB_CLASS_VENDOR_SPEC; + + /* assumes ep0 uses the same value for both speeds ... */ + dev_qualifier.bMaxPacketSize0 = device_desc.bMaxPacketSize0; + + /* and that all endpoints are dual-speed */ + hs_source_desc.bEndpointAddress = + fs_source_desc.bEndpointAddress; + hs_sink_desc.bEndpointAddress = + fs_sink_desc.bEndpointAddress; +#if defined(DEV_CONFIG_CDC) + if (status_ep) + hs_status_desc.bEndpointAddress = + fs_status_desc.bEndpointAddress; +#endif + } + + if (gadget_is_otg(gadget)) { + otg_descriptor.bmAttributes |= USB_OTG_HNP, + eth_config.bmAttributes |= USB_CONFIG_ATT_WAKEUP; + eth_config.bMaxPower = 4; + } + + dev->net = &l_netdev; + strcpy(dev->net->name, USB_NET_NAME); + + dev->cdc = cdc; + dev->zlp = zlp; + + dev->in_ep = in_ep; + dev->out_ep = out_ep; + dev->status_ep = status_ep; + + /* + * Module params for these addresses should come from ID proms. + * The host side address is used with CDC, and commonly + * ends up in a persistent config database. It's not clear if + * host side code for the SAFE thing cares -- its original BLAN + * thing didn't, Sharp never assigned those addresses on Zaurii. + */ + get_ether_addr(dev_addr, dev->net->enetaddr); + + memset(tmp, 0, sizeof(tmp)); + memcpy(tmp, dev->net->enetaddr, sizeof(dev->net->enetaddr)); + + get_ether_addr(host_addr, dev->host_mac); + + sprintf(ethaddr, "%02X%02X%02X%02X%02X%02X", + dev->host_mac[0], dev->host_mac[1], + dev->host_mac[2], dev->host_mac[3], + dev->host_mac[4], dev->host_mac[5]); + + printf("using %s, OUT %s IN %s%s%s\n", gadget->name, + out_ep->name, in_ep->name, + status_ep ? " STATUS " : "", + status_ep ? status_ep->name : "" + ); + printf("MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->net->enetaddr[0], dev->net->enetaddr[1], + dev->net->enetaddr[2], dev->net->enetaddr[3], + dev->net->enetaddr[4], dev->net->enetaddr[5]); + + if (cdc) { + printf("HOST MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->host_mac[0], dev->host_mac[1], + dev->host_mac[2], dev->host_mac[3], + dev->host_mac[4], dev->host_mac[5]); + } + + /* + * use PKTSIZE (or aligned... from u-boot) and set + * wMaxSegmentSize accordingly + */ + dev->mtu = PKTSIZE_ALIGN; /* RNDIS does not like this, only 1514, TODO*/ + + /* preallocate control message data and buffer */ + dev->req = usb_ep_alloc_request(gadget->ep0, GFP_KERNEL); + if (!dev->req) + goto fail; + dev->req->buf = control_req; + dev->req->complete = eth_setup_complete; + + /* ... and maybe likewise for status transfer */ +#if defined(DEV_CONFIG_CDC) + if (dev->status_ep) { + dev->stat_req = usb_ep_alloc_request(dev->status_ep, + GFP_KERNEL); + if (!dev->stat_req) { + usb_ep_free_request(dev->status_ep, dev->req); + + goto fail; + } + dev->stat_req->buf = status_req; + dev->stat_req->context = NULL; + } +#endif + + /* finish hookup to lower layer ... */ + dev->gadget = gadget; + set_gadget_data(gadget, dev); + gadget->ep0->driver_data = dev; + + /* + * two kinds of host-initiated state changes: + * - iff DATA transfer is active, carrier is "on" + * - tx queueing enabled if open *and* carrier is "on" + */ + return 0; + +fail: + error("%s failed", __func__); + eth_unbind(gadget); + return -ENOMEM; +} + +static int usb_eth_init(struct eth_device *netdev, bd_t *bd) +{ + struct eth_dev *dev = &l_ethdev; + struct usb_gadget *gadget; + unsigned long ts; + unsigned long timeout = USB_CONNECT_TIMEOUT; + + if (!netdev) { + error("received NULL ptr"); + goto fail; + } + + dev->network_started = 0; + dev->tx_req = NULL; + dev->rx_req = NULL; + + packet_received = 0; + packet_sent = 0; + + gadget = dev->gadget; + usb_gadget_connect(gadget); + + if (getenv("cdc_connect_timeout")) + timeout = simple_strtoul(getenv("cdc_connect_timeout"), + NULL, 10) * CONFIG_SYS_HZ; + ts = get_timer(0); + while (!l_ethdev.network_started) { + /* Handle control-c and timeouts */ + if (ctrlc() || (get_timer(ts) > timeout)) { + error("The remote end did not respond in time."); + goto fail; + } + usb_gadget_handle_interrupts(); + } + + rx_submit(dev, dev->rx_req, 0); + return 0; +fail: + return -1; +} + +static int usb_eth_send(struct eth_device *netdev, + volatile void *packet, int length) +{ + int retval; + struct usb_request *req = NULL; + struct eth_dev *dev = &l_ethdev; + unsigned long ts; + unsigned long timeout = USB_CONNECT_TIMEOUT; + + debug("%s:...\n", __func__); + + req = dev->tx_req; + + req->buf = (void *)packet; + req->context = NULL; + req->complete = tx_complete; + + /* + * use zlp framing on tx for strict CDC-Ether conformance, + * though any robust network rx path ignores extra padding. + * and some hardware doesn't like to write zlps. + */ + req->zero = 1; + if (!dev->zlp && (length % dev->in_ep->maxpacket) == 0) + length++; + + req->length = length; +#if 0 + /* throttle highspeed IRQ rate back slightly */ + if (gadget_is_dualspeed(dev->gadget)) + req->no_interrupt = (dev->gadget->speed == USB_SPEED_HIGH) + ? ((dev->tx_qlen % qmult) != 0) : 0; +#endif + dev->tx_qlen = 1; + ts = get_timer(0); + packet_sent = 0; + + retval = usb_ep_queue(dev->in_ep, req, GFP_ATOMIC); + + if (!retval) + debug("%s: packet queued\n", __func__); + while (!packet_sent) { + if (get_timer(ts) > timeout) { + printf("timeout sending packets to usb ethernet\n"); + return -1; + } + usb_gadget_handle_interrupts(); + } + + return 0; +} + +static int usb_eth_recv(struct eth_device *netdev) +{ + struct eth_dev *dev = &l_ethdev; + + usb_gadget_handle_interrupts(); + + if (packet_received) { + debug("%s: packet received\n", __func__); + if (dev->rx_req) { + NetReceive(NetRxPackets[0], dev->rx_req->length); + packet_received = 0; + + if (dev->rx_req) + rx_submit(dev, dev->rx_req, 0); + } else + error("dev->rx_req invalid"); + } + return 0; +} + +void usb_eth_halt(struct eth_device *netdev) +{ + struct eth_dev *dev = &l_ethdev; + + if (!netdev) { + error("received NULL ptr"); + return; + } + + usb_gadget_disconnect(dev->gadget); +} + +static struct usb_gadget_driver eth_driver = { + .speed = DEVSPEED, + + .bind = eth_bind, + .unbind = eth_unbind, + + .setup = eth_setup, + .disconnect = eth_disconnect, + + .suspend = eth_suspend, + .resume = eth_resume, +}; + +int usb_eth_initialize(bd_t *bi) +{ + int status = 0; + struct eth_device *netdev = &l_netdev; + + sprintf(netdev->name, "usb_ether"); + + netdev->init = usb_eth_init; + netdev->send = usb_eth_send; + netdev->recv = usb_eth_recv; + netdev->halt = usb_eth_halt; + +#ifdef CONFIG_MCAST_TFTP + #error not supported +#endif + /* Configure default mac-addresses for the USB ethernet device */ +#ifdef CONFIG_USBNET_DEV_ADDR + strncpy(dev_addr, CONFIG_USBNET_DEV_ADDR, sizeof(dev_addr)); +#endif +#ifdef CONFIG_USBNET_HOST_ADDR + strncpy(host_addr, CONFIG_USBNET_HOST_ADDR, sizeof(host_addr)); +#endif + /* Check if the user overruled the MAC addresses */ + if (getenv("usbnet_devaddr")) + strncpy(dev_addr, getenv("usbnet_devaddr"), + sizeof(dev_addr)); + + if (getenv("usbnet_hostaddr")) + strncpy(host_addr, getenv("usbnet_hostaddr"), + sizeof(host_addr)); + + /* Make sure both strings are terminated */ + dev_addr[sizeof(dev_addr)-1] = '\0'; + host_addr[sizeof(host_addr)-1] = '\0'; + + if (!is_eth_addr_valid(dev_addr)) { + error("Need valid 'usbnet_devaddr' to be set"); + status = -1; + } + if (!is_eth_addr_valid(host_addr)) { + error("Need valid 'usbnet_hostaddr' to be set"); + status = -1; + } + if (status) + goto fail; + + status = usb_gadget_register_driver(ð_driver); + if (status < 0) + goto fail; + + eth_register(netdev); + return 0; + +fail: + error("%s failed. error = %d", __func__, status); + return status; +} + diff --git a/drivers/usb/gadget/gadget_chips.h b/drivers/usb/gadget/gadget_chips.h new file mode 100644 index 0000000..9bb7e2e --- /dev/null +++ b/drivers/usb/gadget/gadget_chips.h @@ -0,0 +1,220 @@ +/* + * USB device controllers have lots of quirks. Use these macros in + * gadget drivers or other code that needs to deal with them, and which + * autoconfigures instead of using early binding to the hardware. + * + * This SHOULD eventually work like the ARM mach_is_*() stuff, driven by + * some config file that gets updated as new hardware is supported. + * (And avoiding all runtime comparisons in typical one-choice configs!) + * + * NOTE: some of these controller drivers may not be available yet. + * Some are available on 2.4 kernels; several are available, but not + * yet pushed in the 2.6 mainline tree. + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ +#ifdef CONFIG_USB_GADGET_NET2280 +#define gadget_is_net2280(g) (!strcmp("net2280", (g)->name)) +#else +#define gadget_is_net2280(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_AMD5536UDC +#define gadget_is_amd5536udc(g) (!strcmp("amd5536udc", (g)->name)) +#else +#define gadget_is_amd5536udc(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_DUMMY_HCD +#define gadget_is_dummy(g) (!strcmp("dummy_udc", (g)->name)) +#else +#define gadget_is_dummy(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_PXA2XX +#define gadget_is_pxa(g) (!strcmp("pxa2xx_udc", (g)->name)) +#else +#define gadget_is_pxa(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_GOKU +#define gadget_is_goku(g) (!strcmp("goku_udc", (g)->name)) +#else +#define gadget_is_goku(g) 0 +#endif + +/* SH3 UDC -- not yet ported 2.4 --> 2.6 */ +#ifdef CONFIG_USB_GADGET_SUPERH +#define gadget_is_sh(g) (!strcmp("sh_udc", (g)->name)) +#else +#define gadget_is_sh(g) 0 +#endif + +/* not yet stable on 2.6 (would help "original Zaurus") */ +#ifdef CONFIG_USB_GADGET_SA1100 +#define gadget_is_sa1100(g) (!strcmp("sa1100_udc", (g)->name)) +#else +#define gadget_is_sa1100(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_LH7A40X +#define gadget_is_lh7a40x(g) (!strcmp("lh7a40x_udc", (g)->name)) +#else +#define gadget_is_lh7a40x(g) 0 +#endif + +/* handhelds.org tree (?) */ +#ifdef CONFIG_USB_GADGET_MQ11XX +#define gadget_is_mq11xx(g) (!strcmp("mq11xx_udc", (g)->name)) +#else +#define gadget_is_mq11xx(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_OMAP +#define gadget_is_omap(g) (!strcmp("omap_udc", (g)->name)) +#else +#define gadget_is_omap(g) 0 +#endif + +/* not yet ported 2.4 --> 2.6 */ +#ifdef CONFIG_USB_GADGET_N9604 +#define gadget_is_n9604(g) (!strcmp("n9604_udc", (g)->name)) +#else +#define gadget_is_n9604(g) 0 +#endif + +/* various unstable versions available */ +#ifdef CONFIG_USB_GADGET_PXA27X +#define gadget_is_pxa27x(g) (!strcmp("pxa27x_udc", (g)->name)) +#else +#define gadget_is_pxa27x(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_ATMEL_USBA +#define gadget_is_atmel_usba(g) (!strcmp("atmel_usba_udc", (g)->name)) +#else +#define gadget_is_atmel_usba(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_S3C2410 +#define gadget_is_s3c2410(g) (!strcmp("s3c2410_udc", (g)->name)) +#else +#define gadget_is_s3c2410(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_AT91 +#define gadget_is_at91(g) (!strcmp("at91_udc", (g)->name)) +#else +#define gadget_is_at91(g) 0 +#endif + +/* status unclear */ +#ifdef CONFIG_USB_GADGET_IMX +#define gadget_is_imx(g) (!strcmp("imx_udc", (g)->name)) +#else +#define gadget_is_imx(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_FSL_USB2 +#define gadget_is_fsl_usb2(g) (!strcmp("fsl-usb2-udc", (g)->name)) +#else +#define gadget_is_fsl_usb2(g) 0 +#endif + +/* Mentor high speed function controller */ +/* from Montavista kernel (?) */ +#ifdef CONFIG_USB_GADGET_MUSBHSFC +#define gadget_is_musbhsfc(g) (!strcmp("musbhsfc_udc", (g)->name)) +#else +#define gadget_is_musbhsfc(g) 0 +#endif + +/* Mentor high speed "dual role" controller, in peripheral role */ +#ifdef CONFIG_USB_GADGET_MUSB_HDRC +#define gadget_is_musbhdrc(g) (!strcmp("musb_hdrc", (g)->name)) +#else +#define gadget_is_musbhdrc(g) 0 +#endif + +/* from Montavista kernel (?) */ +#ifdef CONFIG_USB_GADGET_MPC8272 +#define gadget_is_mpc8272(g) (!strcmp("mpc8272_udc", (g)->name)) +#else +#define gadget_is_mpc8272(g) 0 +#endif + +#ifdef CONFIG_USB_GADGET_M66592 +#define gadget_is_m66592(g) (!strcmp("m66592_udc", (g)->name)) +#else +#define gadget_is_m66592(g) 0 +#endif + + +/* + * CONFIG_USB_GADGET_SX2 + * CONFIG_USB_GADGET_AU1X00 + * ... + */ + +/** + * usb_gadget_controller_number - support bcdDevice id convention + * @gadget: the controller being driven + * + * Return a 2-digit BCD value associated with the peripheral controller, + * suitable for use as part of a bcdDevice value, or a negative error code. + * + * NOTE: this convention is purely optional, and has no meaning in terms of + * any USB specification. If you want to use a different convention in your + * gadget driver firmware -- maybe a more formal revision ID -- feel free. + * + * Hosts see these bcdDevice numbers, and are allowed (but not encouraged!) + * to change their behavior accordingly. For example it might help avoiding + * some chip bug. + */ +static inline int usb_gadget_controller_number(struct usb_gadget *gadget) +{ + if (gadget_is_net2280(gadget)) + return 0x01; + else if (gadget_is_dummy(gadget)) + return 0x02; + else if (gadget_is_pxa(gadget)) + return 0x03; + else if (gadget_is_sh(gadget)) + return 0x04; + else if (gadget_is_sa1100(gadget)) + return 0x05; + else if (gadget_is_goku(gadget)) + return 0x06; + else if (gadget_is_mq11xx(gadget)) + return 0x07; + else if (gadget_is_omap(gadget)) + return 0x08; + else if (gadget_is_lh7a40x(gadget)) + return 0x09; + else if (gadget_is_n9604(gadget)) + return 0x10; + else if (gadget_is_pxa27x(gadget)) + return 0x11; + else if (gadget_is_s3c2410(gadget)) + return 0x12; + else if (gadget_is_at91(gadget)) + return 0x13; + else if (gadget_is_imx(gadget)) + return 0x14; + else if (gadget_is_musbhsfc(gadget)) + return 0x15; + else if (gadget_is_musbhdrc(gadget)) + return 0x16; + else if (gadget_is_mpc8272(gadget)) + return 0x17; + else if (gadget_is_atmel_usba(gadget)) + return 0x18; + else if (gadget_is_fsl_usb2(gadget)) + return 0x19; + else if (gadget_is_amd5536udc(gadget)) + return 0x20; + else if (gadget_is_m66592(gadget)) + return 0x21; + return -ENOENT; +} diff --git a/drivers/usb/gadget/usbstring.c b/drivers/usb/gadget/usbstring.c new file mode 100644 index 0000000..6e9d1bf --- /dev/null +++ b/drivers/usb/gadget/usbstring.c @@ -0,0 +1,140 @@ +/* + * Copyright (C) 2003 David Brownell + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License as published + * by the Free Software Foundation; either version 2.1 of the License, or + * (at your option) any later version. + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + +#include <common.h> +#include <asm/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> + +#include <asm/unaligned.h> + + +static int utf8_to_utf16le(const char *s, __le16 *cp, unsigned len) +{ + int count = 0; + u8 c; + u16 uchar; + + /* + * this insists on correct encodings, though not minimal ones. + * BUT it currently rejects legit 4-byte UTF-8 code points, + * which need surrogate pairs. (Unicode 3.1 can use them.) + */ + while (len != 0 && (c = (u8) *s++) != 0) { + if ((c & 0x80)) { + /* + * 2-byte sequence: + * 00000yyyyyxxxxxx = 110yyyyy 10xxxxxx + */ + if ((c & 0xe0) == 0xc0) { + uchar = (c & 0x1f) << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; + + /* + * 3-byte sequence (most CJKV characters): + * zzzzyyyyyyxxxxxx = 1110zzzz 10yyyyyy 10xxxxxx + */ + } else if ((c & 0xf0) == 0xe0) { + uchar = (c & 0x0f) << 12; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c << 6; + + c = (u8) *s++; + if ((c & 0xc0) != 0x80) + goto fail; + c &= 0x3f; + uchar |= c; + + /* no bogus surrogates */ + if (0xd800 <= uchar && uchar <= 0xdfff) + goto fail; + + /* + * 4-byte sequence (surrogate pairs, currently rare): + * 11101110wwwwzzzzyy + 110111yyyyxxxxxx + * = 11110uuu 10uuzzzz 10yyyyyy 10xxxxxx + * (uuuuu = wwww + 1) + * FIXME accept the surrogate code points (only) + */ + } else + goto fail; + } else + uchar = c; + put_unaligned_le16(uchar, cp++); + count++; + len--; + } + return count; +fail: + return -1; +} + + +/** + * usb_gadget_get_string - fill out a string descriptor + * @table: of c strings encoded using UTF-8 + * @id: string id, from low byte of wValue in get string descriptor + * @buf: at least 256 bytes + * + * Finds the UTF-8 string matching the ID, and converts it into a + * string descriptor in utf16-le. + * Returns length of descriptor (always even) or negative errno + * + * If your driver needs stings in multiple languages, you'll probably + * "switch (wIndex) { ... }" in your ep0 string descriptor logic, + * using this routine after choosing which set of UTF-8 strings to use. + * Note that US-ASCII is a strict subset of UTF-8; any string bytes with + * the eighth bit set will be multibyte UTF-8 characters, not ISO-8859/1 + * characters (which are also widely used in C strings). + */ +int +usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf) +{ + struct usb_string *s; + int len; + + /* descriptor 0 has the language id */ + if (id == 0) { + buf[0] = 4; + buf[1] = USB_DT_STRING; + buf[2] = (u8) table->language; + buf[3] = (u8) (table->language >> 8); + return 4; + } + for (s = table->strings; s && s->s; s++) + if (s->id == id) + break; + + /* unrecognized: stall. */ + if (!s || !s->s) + return -EINVAL; + + /* string descriptors have length, tag, then UTF16-LE text */ + len = min((size_t) 126, strlen(s->s)); + memset(buf + 2, 0, 2 * len); /* zero all the bytes */ + len = utf8_to_utf16le(s->s, (__le16 *)&buf[2], len); + if (len < 0) + return -EINVAL; + buf[0] = (len + 1) * 2; + buf[1] = USB_DT_STRING; + return buf[0]; +} + diff --git a/drivers/usb/musb/musb_core.h b/drivers/usb/musb/musb_core.h index 4771876..8f73876 100644 --- a/drivers/usb/musb/musb_core.h +++ b/drivers/usb/musb/musb_core.h @@ -369,6 +369,8 @@ extern void read_fifo(u8 ep, u32 length, void *fifo_data); # define readb(addr) (u8)bfin_read16(addr) # undef writeb # define writeb(b, addr) bfin_write16(addr, b) +# undef MUSB_TXCSR_MODE /* not supported */ +# define MUSB_TXCSR_MODE 0 /* * The USB PHY on current Blackfin processors is a UTMI+ level 2 PHY. * However, it has no ULPI support - so there are no registers at all. diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index 3d047f2..dd849c2 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -1118,8 +1118,44 @@ int video_display_bitmap (ulong bmp_image, int x, int y) } #endif - /* We handle only 8bpp or 24 bpp bitmap */ + /* We handle only 4, 8, or 24 bpp bitmaps */ switch (le16_to_cpu (bmp->header.bit_count)) { + case 4: + padded_line -= width / 2; + ycount = height; + + switch (VIDEO_DATA_FORMAT) { + case GDF_32BIT_X888RGB: + while (ycount--) { + WATCHDOG_RESET (); + /* + * Don't assume that 'width' is an + * even number + */ + for (xcount = 0; xcount < width; xcount++) { + uchar idx; + + if (xcount & 1) { + idx = *bmap & 0xF; + bmap++; + } else + idx = *bmap >> 4; + cte = bmp->color_table[idx]; + FILL_32BIT_X888RGB(cte.red, cte.green, + cte.blue); + } + bmap += padded_line; + fb -= (VIDEO_VISIBLE_COLS + width) * + VIDEO_PIXEL_SIZE; + } + break; + default: + puts("4bpp bitmap unsupported with current " + "video mode\n"); + break; + } + break; + case 8: padded_line -= width; if (VIDEO_DATA_FORMAT == GDF__8BIT_INDEX) { diff --git a/include/405_dimm.h b/include/405_dimm.h deleted file mode 100644 index 103a349..0000000 --- a/include/405_dimm.h +++ /dev/null @@ -1,4 +0,0 @@ -#ifndef _405_dimm_h_ -#define _405_dimm_h_ -long int walnut_dimm(void); -#endif diff --git a/include/_exports.h b/include/_exports.h index f3df568..d89b65b 100644 --- a/include/_exports.h +++ b/include/_exports.h @@ -18,7 +18,6 @@ EXPORT_FUNC(vprintf) EXPORT_FUNC(do_reset) EXPORT_FUNC(getenv) EXPORT_FUNC(setenv) -EXPORT_FUNC(forceenv) EXPORT_FUNC(simple_strtoul) EXPORT_FUNC(simple_strtol) EXPORT_FUNC(strcmp) diff --git a/include/command.h b/include/command.h index 9144d69..5c14616 100644 --- a/include/command.h +++ b/include/command.h @@ -125,4 +125,7 @@ cmd_tbl_t __u_boot_cmd_##name Struct_Section = {#name, maxargs, rep, cmd, usage} #endif /* CONFIG_SYS_LONGHELP */ +#if !defined(CONFIG_RELOC_FIXUP_WORKS) +void fixup_cmdtable(cmd_tbl_t *cmdtp, int size); +#endif #endif /* __COMMAND_H */ diff --git a/include/common.h b/include/common.h index b7193e6..0686a17 100644 --- a/include/common.h +++ b/include/common.h @@ -96,7 +96,7 @@ typedef volatile unsigned char vu_char; #include <asm/immap_83xx.h> #endif #ifdef CONFIG_4xx -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #endif #ifdef CONFIG_HYMOD #include <board/hymod/hymod.h> @@ -189,6 +189,15 @@ typedef void (interrupt_handler_t)(void *); #define MIN(x, y) min(x, y) #define MAX(x, y) max(x, y) +#if defined(CONFIG_ENV_IS_EMBEDDED) +#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN +#elif ( ((CONFIG_ENV_ADDR+CONFIG_ENV_SIZE) < CONFIG_SYS_MONITOR_BASE) || \ + (CONFIG_ENV_ADDR >= (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)) ) || \ + defined(CONFIG_ENV_IS_IN_NVRAM) +#define TOTAL_MALLOC_LEN (CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE) +#else +#define TOTAL_MALLOC_LEN CONFIG_SYS_MALLOC_LEN +#endif /** * container_of - cast a member of a structure out to the containing structure @@ -205,14 +214,6 @@ typedef void (interrupt_handler_t)(void *); * Function Prototypes */ -#ifdef CONFIG_SERIAL_SOFTWARE_FIFO -void serial_buffered_init (void); -void serial_buffered_putc (const char); -void serial_buffered_puts (const char *); -int serial_buffered_getc (void); -int serial_buffered_tstc (void); -#endif /* CONFIG_SERIAL_SOFTWARE_FIFO */ - void hang (void) __attribute__ ((noreturn)); /* */ @@ -262,9 +263,6 @@ int saveenv (void); int inline setenv (char *, char *); #else int setenv (char *, char *); -#ifdef CONFIG_HAS_UID -void forceenv (char *, char *); -#endif #endif /* CONFIG_PPC */ #ifdef CONFIG_ARM # include <asm/mach-types.h> @@ -529,6 +527,7 @@ ulong get_PERCLK2(void); ulong get_PERCLK3(void); #endif ulong get_bus_freq (ulong); +int get_serial_clock(void); #if defined(CONFIG_MPC85xx) typedef MPC85xx_SYS_INFO sys_info_t; @@ -629,6 +628,10 @@ static inline IPaddr_t getenv_IPaddr (char *var) return (string_to_ip(getenv(var))); } +/* lib/qsort.c */ +void qsort(void *base, size_t nmemb, size_t size, + int(*compar)(const void *, const void *)); + /* lib/time.c */ void udelay (unsigned long); diff --git a/include/config_defaults.h b/include/config_defaults.h index 0337163..abdf3be 100644 --- a/include/config_defaults.h +++ b/include/config_defaults.h @@ -12,6 +12,7 @@ /* Support bootm-ing different OSes */ #define CONFIG_BOOTM_LINUX 1 #define CONFIG_BOOTM_NETBSD 1 +#define CONFIG_BOOTM_OSE 1 #define CONFIG_BOOTM_RTEMS 1 #define CONFIG_GZIP 1 diff --git a/include/configs/AP1000.h b/include/configs/AP1000.h index ae0a873..e707075 100644 --- a/include/configs/AP1000.h +++ b/include/configs/AP1000.h @@ -52,12 +52,6 @@ #define CONFIG_BOOTCOMMAND "" /* autoboot command */ -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_BOOTARGS "console=ttyS0,57600" #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ diff --git a/include/configs/APC405.h b/include/configs/APC405.h index a7724ad..cb3f80b 100644 --- a/include/configs/APC405.h +++ b/include/configs/APC405.h @@ -176,6 +176,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ @@ -264,16 +270,10 @@ /* * FLASH organization */ -#ifndef __ASSEMBLY__ -extern int flash_banks; -#endif - #define CONFIG_SYS_FLASH_BASE 0xFE000000 #define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ #define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max num of sects on one chip */ -#define CONFIG_SYS_MAX_FLASH_BANKS flash_banks /* max num of flash banks */ - /* updated in board_early_init_r */ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 #define CONFIG_SYS_FLASH_QUIET_TEST 1 #define CONFIG_SYS_FLASH_INCREMENT 0x01000000 diff --git a/include/configs/AR405.h b/include/configs/AR405.h index 45c64c2..568ce15 100644 --- a/include/configs/AR405.h +++ b/include/configs/AR405.h @@ -127,6 +127,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/ASH405.h b/include/configs/ASH405.h index 4cb8052..789f750 100644 --- a/include/configs/ASH405.h +++ b/include/configs/ASH405.h @@ -124,9 +124,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -335,12 +340,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c133033..58f0c1f 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -200,7 +200,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/CANBT.h b/include/configs/CANBT.h index 115a6f9..ad075b8 100644 --- a/include/configs/CANBT.h +++ b/include/configs/CANBT.h @@ -100,6 +100,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14745600 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/CATcenter.h b/include/configs/CATcenter.h index 002435e..764f71b 100644 --- a/include/configs/CATcenter.h +++ b/include/configs/CATcenter.h @@ -86,7 +86,11 @@ # error "* External frequency (SysClk) not defined! *" #endif -#define CONFIG_UART1_CONSOLE 1 /* Use second UART */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_BAUDRATE 115200 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ @@ -527,13 +531,13 @@ * GPIO0[30] - EMAC0 input * GPIO0[31] - EMAC1 reject packet as output */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1L 0x15555444 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ +#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index 2b6786b..9c57acb 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -122,9 +122,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -301,12 +306,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ diff --git a/include/configs/CPC45.h b/include/configs/CPC45.h index 91d262a..668cfa2 100644 --- a/include/configs/CPC45.h +++ b/include/configs/CPC45.h @@ -347,13 +347,12 @@ #define BOOTFLAG_WARM 0x02 /* Software reboot */ -#define SRAM_BASE 0x80000000 /* SRAM base address */ -#define SRAM_END 0x801FFFFF /*----------------------------------------------------------------------*/ /* CPC45 Memory Map */ /*----------------------------------------------------------------------*/ #define SRAM_BASE 0x80000000 /* SRAM base address */ +#define SRAM_END 0x801FFFFF #define ST16552_A_BASE 0x80200000 /* ST16552 channel A */ #define ST16552_B_BASE 0x80400000 /* ST16552 channel A */ #define BCSR_BASE 0x80600000 /* board control / status registers */ @@ -361,6 +360,8 @@ #define PCMCIA_MEM_BASE 0x83000000 /* PCMCIA memory window base */ #define PCMCIA_IO_BASE 0xFE000000 /* PCMCIA IO window base */ +#define CONFIG_SYS_SRAM_BASE SRAM_BASE +#define CONFIG_SYS_SRAM_SIZE (SRAM_END - SRAM_BASE + 1) /*---------------------------------------------------------------------*/ /* CPC45 Control/Status Registers */ diff --git a/include/configs/CPCI2DP.h b/include/configs/CPCI2DP.h index 9221211..c6882fd 100644 --- a/include/configs/CPCI2DP.h +++ b/include/configs/CPCI2DP.h @@ -111,9 +111,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/CPCI405.h b/include/configs/CPCI405.h index 3e7020d..da57b04 100644 --- a/include/configs/CPCI405.h +++ b/include/configs/CPCI405.h @@ -125,6 +125,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d3000f6..d682d37 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -134,6 +134,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h index d376344..1c521f2 100644 --- a/include/configs/CPCI405AB.h +++ b/include/configs/CPCI405AB.h @@ -133,6 +133,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h index 07acab0..c7b7931 100644 --- a/include/configs/CPCI405DT.h +++ b/include/configs/CPCI405DT.h @@ -135,6 +135,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/CPCIISER4.h b/include/configs/CPCIISER4.h index 5b50bcf..f114290 100644 --- a/include/configs/CPCIISER4.h +++ b/include/configs/CPCIISER4.h @@ -110,6 +110,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 1843200 /* use external serial clock */ /* The following table includes the supported baudrates */ diff --git a/include/configs/CRAYL1.h b/include/configs/CRAYL1.h index 9ab30ec..f6cd760 100644 --- a/include/configs/CRAYL1.h +++ b/include/configs/CRAYL1.h @@ -47,6 +47,12 @@ #define CONFIG_MISC_INIT_R 1 /* so that a misc_init_r() is called */ #define CONFIG_NET_MULTI +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + /* set PRAM to keep U-Boot out, mem= to keep linux out, and initrd_hi to * keep possible initrd ramdisk decompression out. This is in k (1024 bytes) #define CONFIG_PRAM 16 diff --git a/include/configs/DP405.h b/include/configs/DP405.h index 4423f2a..5311dfb 100644 --- a/include/configs/DP405.h +++ b/include/configs/DP405.h @@ -97,9 +97,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -243,12 +248,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000540 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000540 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xB7FE0014 /* 0 ... 31 */ /* diff --git a/include/configs/DU405.h b/include/configs/DU405.h index 8f1fc78..6ba9f13 100644 --- a/include/configs/DU405.h +++ b/include/configs/DU405.h @@ -73,6 +73,11 @@ #include <config_cmd_default.h> #undef CONFIG_CMD_NFS +#undef CONFIG_CMD_EDITENV +#undef CONFIG_CMD_IMLS +#undef CONFIG_CMD_CONSOLE +#undef CONFIG_CMD_LOADB +#undef CONFIG_CMD_LOADS #define CONFIG_CMD_IDE #define CONFIG_CMD_ELF #define CONFIG_CMD_MII @@ -109,6 +114,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external serial clock */ /* The following table includes the supported baudrates */ @@ -126,32 +137,6 @@ #define CONFIG_SYS_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ /*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */ -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_PCI_BOOTDELAY 0 /* enable pci bootdelay variable*/ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0404 /* PCI Device ID: CPCI-ISER4 */ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xff000001 /* 16MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffe00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffe00001 /* 2MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - -/*----------------------------------------------------------------------- * IDE/ATA stuff *----------------------------------------------------------------------- */ diff --git a/include/configs/DU440.h b/include/configs/DU440.h index 830466f..9c34994 100644 --- a/include/configs/DU440.h +++ b/include/configs/DU440.h @@ -64,9 +64,6 @@ #define CONFIG_SYS_PCI_SUBSYS_VENDORID PCI_VENDOR_ID_ESDGMBH #define CONFIG_SYS_PCI_SUBSYS_ID 0x0444 /* device ID for DU440 */ -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -86,10 +83,14 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/ERIC.h b/include/configs/ERIC.h index e07f9a1..da3b4ae 100644 --- a/include/configs/ERIC.h +++ b/include/configs/ERIC.h @@ -139,6 +139,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 14318180 /* The following table includes the supported baudrates */ diff --git a/include/configs/G2000.h b/include/configs/G2000.h index d2883eb..e2e6cb2 100644 --- a/include/configs/G2000.h +++ b/include/configs/G2000.h @@ -151,9 +151,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -367,12 +372,12 @@ * * following GPIO setting changed for G20000, 080304 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40005555 -#define CONFIG_SYS_GPIO0_OSRL 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40005555 +#define CONFIG_SYS_GPIO0_OSRH 0x40000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* diff --git a/include/configs/HH405.h b/include/configs/HH405.h index 01e0bc6..0db9298 100644 --- a/include/configs/HH405.h +++ b/include/configs/HH405.h @@ -176,9 +176,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -461,12 +466,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555440 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0017 #define CONFIG_SYS_LCD_ENDIAN (0x80000000 >> 7) diff --git a/include/configs/HMI10.h b/include/configs/HMI10.h deleted file mode 100644 index 2747d8c..0000000 --- a/include/configs/HMI10.h +++ /dev/null @@ -1,504 +0,0 @@ -/* - * (C) Copyright 2000-2008 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -/* - * board/config.h - configuration options, board specific - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_HMI10 -#define CONFIG_MPC823 1 /* This is a MPC823 CPU */ -#define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ - -#define CONFIG_LCD -#define CONFIG_NEC_NL6448BC33_54 /* NEC NL6448BC33_54 display */ - -#ifdef CONFIG_LCD /* with LCD controller ? */ -#define CONFIG_SPLASH_SCREEN /* ... with splashscreen support*/ -#endif - -#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ -#define CONFIG_SYS_SMC_RXBUFLEN 128 -#define CONFIG_SYS_MAXIDLE 10 -#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ - -#define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ -#define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ -#define CONFIG_PS2SERIAL 2 /* .. on COM3 */ -#define CONFIG_PS2MULT_DELAY (CONFIG_SYS_HZ/2) /* Initial delay */ - -#define CONFIG_BOOTCOUNT_LIMIT - -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_BOARD_TYPES 1 /* support board types */ - -#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "rootpath=/opt/eldk/ppc_8xx\0" \ - "bootfile=/tftpboot/HMI10/uImage\0" \ - "kernel_addr=40040000\0" \ - "ramdisk_addr=40100000\0" \ - "" -#define CONFIG_BOOTCOMMAND "run flash_self" - -#define CONFIG_BOARD_EARLY_INIT_R 1 -#define CONFIG_MISC_INIT_R 1 - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ - -/* enable I2C and select the hardware/software driver */ -#undef CONFIG_HARD_I2C /* I2C with hardware support */ -#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ - -#define CONFIG_SYS_I2C_SPEED 40000 /* 40 kHz is supposed to work */ -#define CONFIG_SYS_I2C_SLAVE 0xFE - -/* Software (bit-bang) I2C driver configuration */ -#define PB_SCL 0x00000020 /* PB 26 */ -#define PB_SDA 0x00000010 /* PB 27 */ - -#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) -#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) -#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) -#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) -#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ - else immr->im_cpm.cp_pbdat &= ~PB_SDA -#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ - else immr->im_cpm.cp_pbdat &= ~PB_SCL -#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */ - -#undef CONFIG_WATCHDOG /* watchdog disabled */ - -#define CONFIG_STATUS_LED 1 /* Status LED enabled */ - -#define CONFIG_CAN_DRIVER 1 /* CAN Driver support enabled */ - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_SUBNETMASK -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_BOOTFILESIZE - - -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION - -#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> - -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_FAT -#define CONFIG_CMD_I2C -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NFS -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_SPLASH_SCREEN - #define CONFIG_CMD_BMP -#endif - - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ - -#if 0 -#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ -#endif -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif - -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } - -/* - * Low Level Configuration Settings - * (address mappings, register initial values, etc.) - * You should know what you are doing if you make changes here. - */ -/*----------------------------------------------------------------------- - * Internal Memory Mapped Register - */ -#define CONFIG_SYS_IMMR 0xFFF00000 - -/*----------------------------------------------------------------------- - * Definitions for initial stack pointer and data area (in DPRAM) - */ -#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -/*----------------------------------------------------------------------- - * Start addresses for the final memory configuration - * (Set up by the startup code) - * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 - */ -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0x40000000 -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ - -/* - * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is - * the maximum mapped by the Linux kernel during initialization. - */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/*----------------------------------------------------------------------- - * FLASH organization - */ - -/* use CFI flash driver */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 -#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 71 /* max number of sectors on one chip */ - -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ -#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ - -/* Address and size of Redundant Environment Sector */ -#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/*----------------------------------------------------------------------- - * Hardware Information Block - */ -#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ -#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ -#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ - -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ -#endif - -/*----------------------------------------------------------------------- - * SYPCR - System Protection Control 11-9 - * SYPCR can only be written once after reset! - *----------------------------------------------------------------------- - * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze - */ -#if defined(CONFIG_WATCHDOG) -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ - SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) -#else -#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) -#endif - -/*----------------------------------------------------------------------- - * SIUMCR - SIU Module Configuration 11-6 - *----------------------------------------------------------------------- - * PCMCIA config., multi-function pin tri-state - */ -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#else /* we must activate GPL5 in the SIUMCR for CAN */ -#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) -#endif /* CONFIG_CAN_DRIVER */ - -/*----------------------------------------------------------------------- - * TBSCR - Time Base Status and Control 11-26 - *----------------------------------------------------------------------- - * Clear Reference Interrupt Status, Timebase freezing enabled - */ -#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) - -/*----------------------------------------------------------------------- - * RTCSC - Real-Time Clock Status and Control Register 11-27 - *----------------------------------------------------------------------- - */ -#define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) - -/*----------------------------------------------------------------------- - * PISCR - Periodic Interrupt Status and Control 11-31 - *----------------------------------------------------------------------- - * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled - */ -#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) - -/*----------------------------------------------------------------------- - * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 - *----------------------------------------------------------------------- - * Reset PLL lock status sticky bit, timer expired status bit and timer - * interrupt status bit - * - * If this is a 80 MHz CPU, set PLL multiplication factor to 5 (5*16=80)! - */ -#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST) - -/*----------------------------------------------------------------------- - * SCCR - System Clock and reset Control Register 15-27 - *----------------------------------------------------------------------- - * Set clock output, timebase and RTC source and divider, - * power management and some other internal clocks - */ -#define SCCR_MASK SCCR_EBDF11 -#define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ - SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ - SCCR_DFALCD00) - -/*----------------------------------------------------------------------- - * PCMCIA stuff - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0100000) -#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4100000) -#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8100000) -#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) -#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC100000) -#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) -#define PCMCIA_MEM_WIN_NO 5 -#define NSCU_OE_INV 1 /* PCMCIA_GCRX_CXOE is inverted */ - -/*----------------------------------------------------------------------- - * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) - *----------------------------------------------------------------------- - */ - -#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ - -#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ -#undef CONFIG_IDE_RESET /* reset for ide not supported */ -#ifndef CONFIG_STATUS_LED /* Status and IDE LED's are mutually exclusive */ -#define CONFIG_IDE_LED 1 /* LED for ide supported */ -#endif - -#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ - -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 - -#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_PCMCIA_MEM_ADDR - -/* Offset for data I/O */ -#define CONFIG_SYS_ATA_DATA_OFFSET (CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for normal register accesses */ -#define CONFIG_SYS_ATA_REG_OFFSET (2 * CONFIG_SYS_PCMCIA_MEM_SIZE + 0x320) - -/* Offset for alternate registers */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x0100 - -/*----------------------------------------------------------------------- - * - *----------------------------------------------------------------------- - * - */ -#define CONFIG_SYS_DER 0 - -/* - * Init Memory Controller: - * - * BR0/1 and OR0/1 (FLASH) - */ - -#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ - -/* used to re-map FLASH both when starting from SRAM or FLASH: - * restrict access enough to keep SRAM working (if any) - * but not too much to meddle with FLASH accesses - */ -#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ -#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ - -/* - * FLASH timing: - */ -#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ - OR_SCY_3_CLK | OR_EHTR | OR_BI) - -#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) -#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) - -#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP -#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR0_PRELIM -#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) - -/* - * BR2/3 and OR2/3 (SDRAM) - * - */ -#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ -#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ -#define SDRAM_MAX_SIZE 0x04000000 /* max 64 MB per bank */ - -/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ -#define CONFIG_SYS_OR_TIMING_SDRAM 0x00000A00 - -#define CONFIG_SYS_OR2_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_SDRAM ) -#define CONFIG_SYS_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) - -#ifndef CONFIG_CAN_DRIVER -#define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR2_PRELIM -#define CONFIG_SYS_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) -#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ -#define CONFIG_SYS_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ -#define CONFIG_SYS_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ -#define CONFIG_SYS_OR3_CAN (CONFIG_SYS_CAN_OR_AM | OR_G5LA | OR_BI) -#define CONFIG_SYS_BR3_CAN ((CONFIG_SYS_CAN_BASE & BR_BA_MSK) | \ - BR_PS_8 | BR_MS_UPMB | BR_V ) -#endif /* CONFIG_CAN_DRIVER */ - -/* - * Memory Periodic Timer Prescaler - * - * The Divider for PTA (refresh timer) configuration is based on an - * example SDRAM configuration (64 MBit, one bank). The adjustment to - * the number of chip selects (NCS) and the actually needed refresh - * rate is done by setting MPTPR. - * - * PTA is calculated from - * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) - * - * gclk CPU clock (not bus clock!) - * Trefresh Refresh cycle * 4 (four word bursts used) - * - * 4096 Rows from SDRAM example configuration - * 1000 factor s -> ms - * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration - * 4 Number of refresh cycles per period - * 64 Refresh cycle in ms per number of rows - * -------------------------------------------- - * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 - * - * 50 MHz => 50.000.000 / Divider = 98 - * 66 Mhz => 66.000.000 / Divider = 129 - * 80 Mhz => 80.000.000 / Divider = 156 - */ - -#define CONFIG_SYS_PTA_PER_CLK ((4096 * 32 * 1000) / (4 * 64)) -#define CONFIG_SYS_MAMR_PTA 98 - -/* - * For 16 MBit, refresh rates could be 31.3 us - * (= 64 ms / 2K = 125 / quad bursts). - * For a simpler initialization, 15.6 us is used instead. - * - * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks - * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank - */ -#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ - -/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ -#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ -#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ - -/* - * MAMR settings for SDRAM - */ - -/* 8 column SDRAM */ -#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) -/* 9 column SDRAM */ -#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ - MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ - MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) - - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 -#define CONFIG_HWCONFIG 1 - -#endif /* __CONFIG_H */ diff --git a/include/configs/HUB405.h b/include/configs/HUB405.h index 8c6d5ed..5dea96e 100644 --- a/include/configs/HUB405.h +++ b/include/configs/HUB405.h @@ -118,9 +118,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -334,12 +339,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/IDS8247.h b/include/configs/IDS8247.h index 71bb7b4..4e73941 100644 --- a/include/configs/IDS8247.h +++ b/include/configs/IDS8247.h @@ -227,7 +227,7 @@ #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CONFIG_SYS_FLASH_BANKS_LIST { 0xFF800000 } -#define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 1 +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ /* What should the base address of the main FLASH be and how big is * it (in MBytes)? This must contain TEXT_BASE from board/ids8247/config.mk * The main FLASH is whichever is connected to *CS0. @@ -242,7 +242,6 @@ /*----------------------------------------------------------------------- * FLASH organization */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */ #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */ #define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ diff --git a/include/configs/IP860.h b/include/configs/IP860.h index be63ea5..ed6b7fd 100644 --- a/include/configs/IP860.h +++ b/include/configs/IP860.h @@ -375,6 +375,8 @@ extern unsigned long ip860_get_clk_freq (void); #define SRAM_SIZE (1 + (~(CONFIG_SYS_OR3 & BR_BA_MSK))) #define CONFIG_SYS_OR3_PRELIM CONFIG_SYS_OR3 /* Make sure to map early */ #define CONFIG_SYS_BR3_PRELIM CONFIG_SYS_BR3 /* in case it's used for ENV */ +#define CONFIG_SYS_SRAM_BASE SRAM_BASE +#define CONFIG_SYS_SRAM_SIZE SRAM_SIZE /* * BR4/OR4 - Board Control & Status (8 bit) diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 5d3a744..3961100 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -280,7 +280,7 @@ #endif #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /* @@ -317,6 +317,10 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_SYS_HUSH_PARSER 1 /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ diff --git a/include/configs/JSE.h b/include/configs/JSE.h index 98f5661..b0b1175 100644 --- a/include/configs/JSE.h +++ b/include/configs/JSE.h @@ -95,18 +95,16 @@ #define CONFIG_ENV_OFFSET 0x00 #define CONFIG_ENV_SIZE 512 - /* The JSE connects UART1 to the console tap connector. */ -#define CONFIG_UART1_CONSOLE 1 +#define CONFIG_CONS_INDEX 2 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + /* Set console baudrate to 9600 */ #define CONFIG_BAUDRATE 9600 -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - /* * Configuration related to auto-boot. * diff --git a/include/configs/KAREF.h b/include/configs/KAREF.h index 05f7254..94cc317 100644 --- a/include/configs/KAREF.h +++ b/include/configs/KAREF.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -90,7 +89,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/METROBOX.h b/include/configs/METROBOX.h index 30a3035..2e63306 100644 --- a/include/configs/METROBOX.h +++ b/include/configs/METROBOX.h @@ -125,7 +125,6 @@ #define CONFIG_SYS_FLASH_BASE 0xfff80000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfff80000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -152,7 +151,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI 1 #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index ff9496b..bfff750 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -176,6 +176,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 916667 diff --git a/include/configs/ML2.h b/include/configs/ML2.h index 5fcc173..2fc0119 100644 --- a/include/configs/ML2.h +++ b/include/configs/ML2.h @@ -52,16 +52,6 @@ #define CONFIG_PREBOOT "fsload 0x00100000 /boot/image" -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#if 0 -#define CONFIG_SERIAL_SOFTWARE_FIFO 4000 -#else -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#endif - #if 0 #define CONFIG_BOOTARGS "root=/dev/nfs " \ "ip=192.168.2.176:192.168.2.190:192.168.2.79:255.255.255.0 " \ diff --git a/include/configs/MPC8308RDB.h b/include/configs/MPC8308RDB.h index 6cd5da7..1314271 100644 --- a/include/configs/MPC8308RDB.h +++ b/include/configs/MPC8308RDB.h @@ -85,10 +85,27 @@ /* * System IO Config */ -#define CONFIG_SYS_SICRH 0x01b7d103 -#define CONFIG_SYS_SICRL 0x00000040 /* 3.3V, no delay */ - -#define CONFIG_BOARD_EARLY_INIT_F /* call board_pre_init */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_SD |\ + SICRH_ESDHC_B_SD |\ + SICRH_ESDHC_C_SD |\ + SICRH_GPIO_A_TSEC2 |\ + SICRH_GPIO_B_TSEC2_GTX_CLK125 |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_CRS |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V2P5 |\ + SICRH_TSOBI2_V2P5) /* 0x01b7d103 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_GTX_CLK125) /* 0x00000040 */ /* * IMMR new address @@ -218,7 +235,7 @@ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_8MB) #define CONFIG_SYS_BR0_PRELIM (\ CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ @@ -260,7 +277,7 @@ /* 0xFFFF8396 */ #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) #ifdef CONFIG_VSC7385_ENET #define CONFIG_TSEC2 @@ -270,7 +287,7 @@ /* Access window base at VSC7385 base */ #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access window size 128K */ -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 #define CONFIG_VSC7385_IMAGE_SIZE 8192 @@ -279,7 +296,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -336,19 +352,8 @@ #define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 -/* - * Fake PCIE2 definitions: there is no PCIE2 on this board but the code - * in arch/powerpc/cpu/mpc83xx/pcie.c doesn't compile without this - */ -#define CONFIG_SYS_PCIE2_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_BASE 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC0000000 -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 -#define CONFIG_SYS_PCIE2_CFG_BASE 0xD0000000 -#define CONFIG_SYS_PCIE2_CFG_SIZE 0x01000000 -#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE2_IO_PHYS 0xD1000000 -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000 +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 #define CONFIG_PCI #define CONFIG_PCIE @@ -439,10 +444,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 524afa5..3fdd1b0 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) Freescale Semiconductor, Inc. 2006. + * Copyright (C) Freescale Semiconductor, Inc. 2006, 2010. * * See file CREDITS for list of people who contributed to this * project. @@ -232,6 +232,13 @@ #define CONFIG_SYS_NAND_BASE 0xE2800000 #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=e2800000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_CMD_NAND 1 @@ -453,10 +460,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index f1b110b..abc29c0 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007-2009 Freescale Semiconductor, Inc. + * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. * * Dave Liu <daveliu@freescale.com> * @@ -243,6 +243,13 @@ #define CONFIG_SYS_NAND_BASE 0xE0600000 #endif +#define CONFIG_MTD_DEVICE +#define CONFIG_MTD_PARTITION +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nand0=e0600000.flash" +#define MTDPARTS_DEFAULT \ + "mtdparts=e0600000.flash:512k(uboot),128k(env),3m@1m(kernel),-(fs)" + #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_CMD_NAND 1 @@ -298,7 +305,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -529,10 +535,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 9a296a1..0719fcea 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -262,7 +262,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -430,10 +429,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 68ff191..bed62bd 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -273,7 +273,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -447,10 +446,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 73dbea4..55e9de0 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -283,7 +283,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -496,10 +495,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index 9be571f..117f745 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -329,7 +329,6 @@ boards, we say we have two, but don't display a message if we find only one. */ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -539,10 +538,10 @@ boards, we say we have two, but don't display a message if we find only one. */ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index c58e003..d7381aa 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -307,7 +307,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -487,10 +486,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 9fa577d..fc53ecc 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -237,7 +237,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -404,10 +403,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 9092755..8546ebc 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -299,7 +299,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -537,10 +536,10 @@ extern int board_pci_host_broken(void); /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 79dadc4..20c2304 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -316,7 +316,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -545,10 +544,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 2a3c058..0a9f47b 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -400,7 +400,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 577c276..c133895 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -237,7 +237,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index 7daf934..75227a6 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -173,7 +173,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 8797b30..c3167e9 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -263,7 +263,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index d1ac32f..1804582 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -214,7 +214,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 33f49f5..e1e4acf 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -282,7 +282,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 0f71f11..b0dd175 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -261,7 +261,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 2dc2932..a98ecde 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -244,7 +244,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 8177db3..8ffd458 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -276,7 +276,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 1 #define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 081661e..34ebbdb 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -333,7 +333,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 4d9606e..645d947 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -24,9 +24,12 @@ /* video */ #undef CONFIG_VIDEO -#if defined(CONFIG_VIDEO) +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO #endif #ifdef RUN_DIAG @@ -218,7 +221,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 974cb6b..3b80d14 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -275,7 +275,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/MVBLM7.h b/include/configs/MVBLM7.h index c28eb64..25d8077 100644 --- a/include/configs/MVBLM7.h +++ b/include/configs/MVBLM7.h @@ -150,7 +150,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -300,10 +299,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW 0x0 #define CONFIG_SYS_HRCW_HIGH 0x0 diff --git a/include/configs/MVSMR.h b/include/configs/MVSMR.h index 6492068..000c4c6 100644 --- a/include/configs/MVSMR.h +++ b/include/configs/MVSMR.h @@ -185,7 +185,6 @@ */ #define CONFIG_ENV_IS_IN_FLASH #undef CONFIG_SYS_FLASH_PROTECTION -#define CONFIG_HAS_UID #define CONFIG_OVERWRITE_ETHADDR_ONCE #define CONFIG_ENV_OFFSET 0x8000 diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h index 55471af..ad2e4da 100644 --- a/include/configs/OCRTC.h +++ b/include/configs/OCRTC.h @@ -105,6 +105,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/ORSG.h b/include/configs/ORSG.h index 1424713..3d35362 100644 --- a/include/configs/ORSG.h +++ b/include/configs/ORSG.h @@ -105,6 +105,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 7e901e1..fa45b5b 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -281,7 +281,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 79ce2c0..74cff0c 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -337,7 +337,6 @@ * shorted - index 1 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/PCI405.h b/include/configs/PCI405.h index 0d443ea..244d6fe 100644 --- a/include/configs/PCI405.h +++ b/include/configs/PCI405.h @@ -110,6 +110,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/PIP405.h b/include/configs/PIP405.h index 3e57c0b..2901cfd 100644 --- a/include/configs/PIP405.h +++ b/include/configs/PIP405.h @@ -167,6 +167,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/PLU405.h b/include/configs/PLU405.h index f917eb5..928ed8e 100644 --- a/include/configs/PLU405.h +++ b/include/configs/PLU405.h @@ -135,9 +135,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -379,12 +384,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x00000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0x77FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 7426bca..cf8a8cf 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -174,7 +174,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/PMC405.h b/include/configs/PMC405.h index 00a12fb..c420efe 100644 --- a/include/configs/PMC405.h +++ b/include/configs/PMC405.h @@ -130,6 +130,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock */ #define CONFIG_SYS_BASE_BAUD 806400 diff --git a/include/configs/PMC405DE.h b/include/configs/PMC405DE.h index 2c048dd..5b1048e 100644 --- a/include/configs/PMC405DE.h +++ b/include/configs/PMC405DE.h @@ -107,9 +107,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x3000000 /* 1 ... 48 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index cc0ea7f..bf2247d 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -72,9 +72,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 #define CONFIG_SYS_PCI_MEMSIZE 0x80000000 /* 2GB! */ -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -95,10 +92,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 -#define CONFIG_SERIAL_MULTI 1 -#undef CONFIG_UART1_CONSOLE /* console on front panel */ +#define CONFIG_SERIAL_MULTI 1 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/PPChameleonEVB.h b/include/configs/PPChameleonEVB.h index 44f03dc..f9b2014 100644 --- a/include/configs/PPChameleonEVB.h +++ b/include/configs/PPChameleonEVB.h @@ -191,6 +191,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 @@ -542,13 +548,13 @@ * GPIO0[30] - EMAC0 input * GPIO0[31] - EMAC1 reject packet as output */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -/*#define CONFIG_SYS_GPIO0_ISR1L 0x15555445*/ -#define CONFIG_SYS_GPIO0_ISR1L 0x15555444 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +/*#define CONFIG_SYS_GPIO0_ISR1H 0x15555445*/ +#define CONFIG_SYS_GPIO0_ISR1H 0x15555444 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FF8014 /* @@ -577,17 +583,6 @@ #define DIMM_READ_ADDR 0xAB #define DIMM_WRITE_ADDR 0xAA -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - /* Defines for CPC0_PLLMR1 Register fields */ #define PLL_ACTIVE 0x80000000 #define CPC0_PLLMR1_SSCS 0x80000000 diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 5d424dd..d6b3cb8 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -205,7 +205,6 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/SIMPC8313.h b/include/configs/SIMPC8313.h index 70b7489..9c8c318 100644 --- a/include/configs/SIMPC8313.h +++ b/include/configs/SIMPC8313.h @@ -373,10 +373,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c1e0e64..d0c6a4d 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -101,10 +101,6 @@ * defined as tqm834x_num_flash_banks. */ #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 -#ifndef __ASSEMBLY__ -extern int tqm834x_num_flash_banks; -#endif -#define CONFIG_SYS_MAX_FLASH_BANKS (tqm834x_num_flash_banks) #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max sectors per device */ @@ -166,7 +162,6 @@ extern int tqm834x_num_flash_banks; * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -359,10 +354,10 @@ extern int tqm834x_num_flash_banks; /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_HRCW_LOW (\ HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index abbaf38..ccb339d 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -256,7 +256,6 @@ #else /* !CONFIG_TQM8560 */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/VOH405.h b/include/configs/VOH405.h index 9c91fcc..b9ea610 100644 --- a/include/configs/VOH405.h +++ b/include/configs/VOH405.h @@ -133,9 +133,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -388,12 +393,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs -> GPIO */ -#define CONFIG_SYS_GPIO0_OSRH 0x00000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555440 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x00000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555440 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0x777E0017 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/VOM405.h b/include/configs/VOM405.h index 871e4c3..a88b41a 100644 --- a/include/configs/VOM405.h +++ b/include/configs/VOM405.h @@ -120,9 +120,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#undef CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -273,12 +278,12 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ /* diff --git a/include/configs/W7OLMC.h b/include/configs/W7OLMC.h index f06bfe5..0fbe80c 100644 --- a/include/configs/W7OLMC.h +++ b/include/configs/W7OLMC.h @@ -125,6 +125,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 384000 diff --git a/include/configs/W7OLMG.h b/include/configs/W7OLMG.h index be8c9f8..f12fa55 100644 --- a/include/configs/W7OLMG.h +++ b/include/configs/W7OLMG.h @@ -133,6 +133,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 384000 diff --git a/include/configs/WUH405.h b/include/configs/WUH405.h index be9ac62..34a5fff 100644 --- a/include/configs/WUH405.h +++ b/include/configs/WUH405.h @@ -122,9 +122,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -332,12 +337,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x40000550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 #define CONFIG_SYS_DUART_RST (0x80000000 >> 14) diff --git a/include/configs/XPEDITE1000.h b/include/configs/XPEDITE1000.h index dfeaf74..8b47862 100644 --- a/include/configs/XPEDITE1000.h +++ b/include/configs/XPEDITE1000.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000) @@ -111,6 +110,12 @@ extern void out32(unsigned int, unsigned long); /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400} #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 8b01c70..39f85ae 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -89,6 +89,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/aev.h b/include/configs/aev.h index 98958a6..54e6c57 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -286,10 +286,11 @@ * Ethernet configuration */ #define CONFIG_MPC5xxx_FEC 1 +#define CONFIG_MPC5xxx_FEC_MII100 /* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb + * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb */ -/* #define CONFIG_FEC_10MBIT 1 */ +/* #define CONFIG_MPC5xxx_FEC_MII10 */ #define CONFIG_PHY_ADDR 0x00 /* diff --git a/include/configs/alpr.h b/include/configs/alpr.h index 326b324..7038291 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_MEMSIZE 0x40000000 /* size of mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_PCI_MEMBASE1 CONFIG_SYS_PCI_MEMBASE + 0x10000000 @@ -74,9 +73,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/amcc-common.h b/include/configs/amcc-common.h index 23a859f..9c53d37 100644 --- a/include/configs/amcc-common.h +++ b/include/configs/amcc-common.h @@ -31,8 +31,12 @@ /* * UART */ -#define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() +#define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/aria.h b/include/configs/aria.h index c5f9cc1..c5a3feb 100644 --- a/include/configs/aria.h +++ b/include/configs/aria.h @@ -321,7 +321,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration @@ -507,10 +506,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 8c4127d..18276c5 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -62,8 +62,7 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ -#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ +#define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ #define CONFIG_SYS_USB_DEVICE 0x50000000 @@ -85,9 +84,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * NVRAM/RTC diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 627060a..3e64492 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -123,7 +123,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 @@ -179,6 +179,7 @@ * (Set up by the startup code) */ #define CONFIG_SYS_SRAM_BASE 0xFFF00000 +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_FLASH_BASE 0xFFF80000 /*----------------------------------------------------------------------- @@ -283,12 +284,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x55555555 -#define CONFIG_SYS_GPIO0_OSRL 0x40000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x55555555 +#define CONFIG_SYS_GPIO0_OSRH 0x40000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xFFFF8014 /*----------------------------------------------------------------------- diff --git a/include/configs/canyonlands.h b/include/configs/canyonlands.h index 6fe7639..51087f7 100644 --- a/include/configs/canyonlands.h +++ b/include/configs/canyonlands.h @@ -111,10 +111,9 @@ #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals */ - #define CONFIG_SYS_AHB_BASE 0xE2000000 /* internal AHB peripherals */ /*----------------------------------------------------------------------- @@ -129,7 +128,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/csb272.h b/include/configs/csb272.h index 9ded330..7108210 100644 --- a/include/configs/csb272.h +++ b/include/configs/csb272.h @@ -160,6 +160,12 @@ * UART configuration * */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #define CONFIG_SYS_EXT_SERIAL_CLOCK 3868400 /* use external serial clock */ #undef CONFIG_SYS_BASE_BAUD #define CONFIG_BAUDRATE 38400 /* Default baud rate */ diff --git a/include/configs/csb472.h b/include/configs/csb472.h index 71eb083..7b9f29a 100644 --- a/include/configs/csb472.h +++ b/include/configs/csb472.h @@ -159,6 +159,12 @@ * UART configuration * */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* use internal serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 38400 /* Default baud rate */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 357715d..d02b196 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -39,7 +39,6 @@ #define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID) #define CONFIG_SYS_HZ 1000 #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ /* * Memory Info @@ -48,6 +47,7 @@ #define CONFIG_SYS_GBL_DATA_SIZE 128 /* reserved for initial data */ #define PHYS_SDRAM_1 DAVINCI_DDR_EMIF_DATA_BASE /* DDR Start */ #define PHYS_SDRAM_1_SIZE (64 << 20) /* SDRAM size 64MB */ +#define CONFIG_MAX_RAM_BANK_SIZE (512 << 20) /* max size from SPRS586*/ /* memtest start addr */ #define CONFIG_SYS_MEMTEST_START (PHYS_SDRAM_1 + 0x2000000) @@ -137,4 +137,9 @@ #undef CONFIG_CMD_ENV #endif +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0xc0000000 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* __CONFIG_H */ diff --git a/include/configs/davinci_schmoogie.h b/include/configs/davinci_schmoogie.h index 875dda4..04cdc21 100644 --- a/include/configs/davinci_schmoogie.h +++ b/include/configs/davinci_schmoogie.h @@ -99,7 +99,6 @@ /*=====================*/ #define CONFIG_RTC_DS1307 /* RTC chip on SCHMOOGIE */ #define CONFIG_SYS_I2C_RTC_ADDR 0x6f /* RTC chip I2C address */ -#define CONFIG_HAS_UID #define CONFIG_UID_DS28CM00 /* Unique ID on SCHMOOGIE */ #define CONFIG_SYS_UID_ADDR 0x50 /* UID chip I2C address */ /*==============================*/ diff --git a/include/configs/dlvision.h b/include/configs/dlvision.h index 4533799..21d2d28 100644 --- a/include/configs/dlvision.h +++ b/include/configs/dlvision.h @@ -97,7 +97,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/eNET.h b/include/configs/eNET.h index 361fe61..da2a97d 100644 --- a/include/configs/eNET.h +++ b/include/configs/eNET.h @@ -59,7 +59,6 @@ * Serial Configuration */ #define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 10f425d..8c3284a 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -61,7 +61,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -81,7 +80,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/gdppc440etx.h b/include/configs/gdppc440etx.h index d193919..d6db7bf 100644 --- a/include/configs/gdppc440etx.h +++ b/include/configs/gdppc440etx.h @@ -59,7 +59,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripheral*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs */ /*Don't change either of these*/ @@ -80,8 +79,12 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -#define CONFIG_UART1_CONSOLE /* * Environment diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 5adcc0f..f2ab50c 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -70,9 +70,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -93,8 +90,6 @@ *----------------------------------------------------------------------*/ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_BAUDRATE 115200 -#undef CONFIG_SERIAL_SOFTWARE_FIFO -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/icon.h b/include/configs/icon.h index eb419eb..ad0ca5d 100644 --- a/include/configs/icon.h +++ b/include/configs/icon.h @@ -52,7 +52,6 @@ * actual resources get mapped (not physical addresses) */ #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* later mapped to this addr */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -105,7 +104,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 1da8602..812e5f2 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -188,6 +188,7 @@ */ #include <config_cmd_default.h> #define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP #define CONFIG_CMD_DIAG #define CONFIG_CMD_FAT @@ -234,4 +235,9 @@ "mtdids=" MTDIDS_DEFAULT "\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* __IMX27LITE_COMMON_CONFIG_H */ diff --git a/include/configs/intip.h b/include/configs/intip.h index 19f12fa..82c8282 100644 --- a/include/configs/intip.h +++ b/include/configs/intip.h @@ -93,10 +93,9 @@ #define CONFIG_SYS_OCM_BASE 0xE3000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - #define CONFIG_SYS_AHB_BASE 0xE2000000 /* int. AHB periph. */ /* @@ -112,7 +111,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /* * Environment diff --git a/include/configs/jadecpu.h b/include/configs/jadecpu.h index 29c534c..a5d8764 100644 --- a/include/configs/jadecpu.h +++ b/include/configs/jadecpu.h @@ -146,6 +146,9 @@ #define PHYS_SDRAM 0x40000000 /* Start address of DDRRAM */ #define PHYS_SDRAM_SIZE 0x08000000 /* 128 megs */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_SP_ADDR 0x01008000 + /* * FLASH and environment organization */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index 5d14a10..e4ccd7d 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -61,7 +61,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -104,7 +103,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /*----------------------------------------------------------------------- diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index 8f813dd0..37eaf8f 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -57,7 +57,6 @@ #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_NAND_ADDR 0xF8000000 #define CONFIG_SYS_FPGA_BASE 0xF0000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -114,8 +113,7 @@ * Serial Port *----------------------------------------------------------------------*/ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/km_arm.h b/include/configs/km_arm.h index 1617e69..8673e6f 100644 --- a/include/configs/km_arm.h +++ b/include/configs/km_arm.h @@ -180,4 +180,8 @@ int get_scl (void); #undef CONFIG_JFFS2_CMDLINE #endif +/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_INIT_SP_ADDR (0x00000000 + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) #endif /* _CONFIG_KM_ARM_H */ diff --git a/include/configs/kmeter1.h b/include/configs/kmeter1.h index f7d36b1..4794256 100644 --- a/include/configs/kmeter1.h +++ b/include/configs/kmeter1.h @@ -257,7 +257,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -358,10 +357,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ /* * Core HID Setup diff --git a/include/configs/korat.h b/include/configs/korat.h index 23da72f..55ef4f0 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -71,9 +71,6 @@ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE + 0x20000000) -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -93,11 +90,14 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/luan.h b/include/configs/luan.h index b158b74..6b1a41f 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -53,12 +53,11 @@ #define CONFIG_SYS_LARGE_FLASH 0xffc00000 /* 4MB flash address CS0 */ #define CONFIG_SYS_SMALL_FLASH 0xff900000 /* 1MB flash address CS2 */ #define CONFIG_SYS_SRAM_BASE 0xff800000 /* 1MB SRAM address CS2 */ +#define CONFIG_SYS_SRAM_SIZE (1 << 20) #define CONFIG_SYS_EPLD_BASE 0xff000000 /* EPLD and FRAM CS1 */ #define CONFIG_SYS_ISRAM_BASE 0xf8000000 /* internal 8k SRAM (L2 cache) */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xf0000000 /* internal peripherals */ - #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */ @@ -87,8 +86,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* external 11.059MHz clk */ -#undef CONFIG_UART1_CONSOLE /* define if you want console on UART1 */ /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 295a18e..72e02f8 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -62,9 +62,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -106,11 +103,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/* define this if you want console on UART1 */ -#define CONFIG_UART1_CONSOLE 1 /* use UART1 as console */ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/makalu.h b/include/configs/makalu.h index f24d499..905c719 100644 --- a/include/configs/makalu.h +++ b/include/configs/makalu.h @@ -55,7 +55,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xFC000000 #define CONFIG_SYS_FPGA_BASE 0xF0000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal peripherals*/ /*----------------------------------------------------------------------- * Initial RAM & Stack Pointer Configuration Options @@ -111,9 +110,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no ext. clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/mcu25.h b/include/configs/mcu25.h index 50bed10..3e04cfe 100644 --- a/include/configs/mcu25.h +++ b/include/configs/mcu25.h @@ -86,16 +86,9 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -/* needed to be able to define CONFIG_SERIAL_SOFTWARE_FIFO */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 -/* Size (bytes) of interrupt driven serial port buffer. - * Set to 0 to use polling instead of interrupts. - * Setting to 0 will also disable RTS/CTS handshaking. - */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO - /* Set console baudrate to 9600 */ #define CONFIG_BAUDRATE 9600 diff --git a/include/configs/mecp5123.h b/include/configs/mecp5123.h index 92c4f5f..a26de0b 100644 --- a/include/configs/mecp5123.h +++ b/include/configs/mecp5123.h @@ -218,7 +218,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration @@ -344,10 +343,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Linux initial memory map */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Linux initial memory map */ /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/mpc5121ads.h b/include/configs/mpc5121ads.h index 5281042..3740316 100644 --- a/include/configs/mpc5121ads.h +++ b/include/configs/mpc5121ads.h @@ -47,14 +47,16 @@ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ -#undef CONFIG_FSL_DIU_LOGO_BMP /* Don't include FSL DIU binary bmp */ /* video */ #undef CONFIG_VIDEO -#if defined(CONFIG_VIDEO) +#ifdef CONFIG_VIDEO +#define CONFIG_CMD_BMP #define CONFIG_CFB_CONSOLE #define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO #endif /* CONFIG_PCI is defined at config time */ @@ -284,7 +286,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO /* * Serial console configuration @@ -477,10 +478,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/mpc8308_p1m.h b/include/configs/mpc8308_p1m.h new file mode 100644 index 0000000..b5a19e4 --- /dev/null +++ b/include/configs/mpc8308_p1m.h @@ -0,0 +1,555 @@ +/* + * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com + * + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + */ +#define CONFIG_E300 1 /* E300 family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC8308 1 /* MPC8308 CPU specific */ +#define CONFIG_MPC8308_P1M 1 /* mpc8308_p1m board specific */ + +/* + * On-board devices + * + * TSECs + */ +#define CONFIG_TSEC1 +#define CONFIG_TSEC2 + +/* + * System Clock Setup + */ +#define CONFIG_83XX_CLKIN 33333333 /* in Hz */ +#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN + +/* + * Hardware Reset Configuration Word + * if CLKIN is 66.66MHz, then + * CSB = 133MHz, DDRC = 266MHz, LBC = 133MHz + * We choose the A type silicon as default, so the core is 400Mhz. + */ +#define CONFIG_SYS_HRCW_LOW (\ + HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ + HRCWL_DDR_TO_SCB_CLK_2X1 |\ + HRCWL_SVCOD_DIV_2 |\ + HRCWL_CSB_TO_CLKIN_4X1 |\ + HRCWL_CORE_TO_CSB_3X1) +/* + * There are neither HRCWH_PCI_HOST nor HRCWH_PCI1_ARBITER_ENABLE bits + * in 8308's HRCWH according to the manual, but original Freescale's + * code has them and I've expirienced some problems using the board + * with BDI3000 attached when I've tried to set these bits to zero + * (UART doesn't work after the 'reset run' command). + */ +#define CONFIG_SYS_HRCW_HIGH (\ + HRCWH_PCI_HOST |\ + HRCWH_PCI1_ARBITER_ENABLE |\ + HRCWH_CORE_ENABLE |\ + HRCWH_FROM_0X00000100 |\ + HRCWH_BOOTSEQ_DISABLE |\ + HRCWH_SW_WATCHDOG_DISABLE |\ + HRCWH_ROM_LOC_LOCAL_16BIT |\ + HRCWH_RL_EXT_LEGACY |\ + HRCWH_TSEC1M_IN_MII |\ + HRCWH_TSEC2M_IN_MII |\ + HRCWH_BIG_ENDIAN) + +/* + * System IO Config + */ +#define CONFIG_SYS_SICRH (\ + SICRH_ESDHC_A_GPIO |\ + SICRH_ESDHC_B_GPIO |\ + SICRH_ESDHC_C_GTM |\ + SICRH_GPIO_A_TSEC2 |\ + SICRH_GPIO_B_TSEC2_TX_CLK |\ + SICRH_IEEE1588_A_GPIO |\ + SICRH_USB |\ + SICRH_GTM_GPIO |\ + SICRH_IEEE1588_B_GPIO |\ + SICRH_ETSEC2_CRS |\ + SICRH_GPIOSEL_1 |\ + SICRH_TMROBI_V3P3 |\ + SICRH_TSOBI1_V3P3 |\ + SICRH_TSOBI2_V3P3) /* 0xf577d100 */ +#define CONFIG_SYS_SICRL (\ + SICRL_SPI_PF0 |\ + SICRL_UART_PF0 |\ + SICRL_IRQ_PF0 |\ + SICRL_I2C2_PF0 |\ + SICRL_ETSEC1_TX_CLK) /* 0x00000000 */ + +#define CONFIG_SYS_GPIO1_PRELIM +/* GPIO Default input/output settings */ +#define CONFIG_SYS_GPIO1_DIR 0x7AAF8C00 +/* + * Default GPIO values: + * LED#1 enabled; WLAN enabled; Both COM LED on (orange) + */ +#define CONFIG_SYS_GPIO1_DAT 0x08008C00 + +/* + * IMMR new address + */ +#define CONFIG_SYS_IMMR 0xE0000000 + +/* + * SERDES + */ +#define CONFIG_FSL_SERDES +#define CONFIG_FSL_SERDES1 0xe3000 + +/* + * Arbiter Setup + */ +#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ +#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC emergency priority is highest */ + +/* + * DDR Setup + */ +#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \ + | DDRCDR_PZ_LOZ \ + | DDRCDR_NZ_LOZ \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x7b880001 */ +/* + * Manually set up DDR parameters + * consist of two chips HY5PS12621BFP-C4 from HYNIX + */ + +#define CONFIG_SYS_DDR_SIZE 128 /* MB */ + +#define CONFIG_SYS_DDR_CS0_BNDS 0x00000007 +#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ + | 0x00010000 /* ODT_WR to CSn */ \ + | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10) + /* 0x80010102 */ +#define CONFIG_SYS_DDR_TIMING_3 0x00000000 +#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \ + | (0 << TIMING_CFG0_WRT_SHIFT) \ + | (0 << TIMING_CFG0_RRT_SHIFT) \ + | (0 << TIMING_CFG0_WWT_SHIFT) \ + | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \ + | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \ + | (2 << TIMING_CFG0_MRS_CYC_SHIFT)) + /* 0x00220802 */ +#define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \ + | (7 << TIMING_CFG1_ACTTOPRE_SHIFT) \ + | (2 << TIMING_CFG1_ACTTORW_SHIFT) \ + | (5 << TIMING_CFG1_CASLAT_SHIFT) \ + | (6 << TIMING_CFG1_REFREC_SHIFT) \ + | (2 << TIMING_CFG1_WRREC_SHIFT) \ + | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \ + | (2 << TIMING_CFG1_WRTORD_SHIFT)) + /* 0x27256222 */ +#define CONFIG_SYS_DDR_TIMING_2 ((1 << TIMING_CFG2_ADD_LAT_SHIFT) \ + | (4 << TIMING_CFG2_CPO_SHIFT) \ + | (2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \ + | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \ + | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \ + | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \ + | (5 << TIMING_CFG2_FOUR_ACT_SHIFT)) + /* 0x121048c5 */ +#define CONFIG_SYS_DDR_INTERVAL ((0x0360 << SDRAM_INTERVAL_REFINT_SHIFT) \ + | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) + /* 0x03600100 */ +#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ + | SDRAM_CFG_SDRAM_TYPE_DDR2 \ + | SDRAM_CFG_32_BE) + /* 0x43080000 */ + +#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00401000 /* 1 posted refresh */ +#define CONFIG_SYS_DDR_MODE ((0x0448 << SDRAM_MODE_ESD_SHIFT) \ + | (0x0232 << SDRAM_MODE_SD_SHIFT)) + /* ODT 150ohm CL=3, AL=1 on SDRAM */ +#define CONFIG_SYS_DDR_MODE2 0x00000000 + +/* + * Memory test + */ +#define CONFIG_SYS_MEMTEST_START 0x00001000 /* memtest region */ +#define CONFIG_SYS_MEMTEST_END 0x07f00000 + +/* + * The reserved memory + */ +#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ + +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ +#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ + +/* + * Initial RAM Base Address Setup + */ +#define CONFIG_SYS_INIT_RAM_LOCK 1 +#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ +#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET \ + (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) + +/* + * Local Bus Configuration & Clock Setup + */ +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_2 +#define CONFIG_SYS_LBC_LBCR 0x00040000 + +/* + * FLASH on the Local Bus + */ +#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ +#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ +#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* FLASH base address */ +#define CONFIG_SYS_FLASH_SIZE 64 /* FLASH size is 64M */ +#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ + +/* Window base at flash base */ +#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) + +#define CONFIG_SYS_BR0_PRELIM (\ + CONFIG_SYS_FLASH_BASE /* Flash Base address */ |\ + (2 << BR_PS_SHIFT) /* 16 bit port size */ |\ + BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ + | OR_UPM_XAM \ + | OR_GPCM_CSNT \ + | OR_GPCM_ACS_DIV2 \ + | OR_GPCM_XACS \ + | OR_GPCM_SCY_4 \ + | OR_GPCM_TRLX \ + | OR_GPCM_EHTR \ + | OR_GPCM_EAD) + +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* Flash Erase Timeout (ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (1000 * 1024) +/* Flash Write Timeout (ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (500 * 1024) + +/* + * SJA1000 CAN controller on Local Bus + */ +#define CONFIG_SYS_SJA1000_BASE 0xFBFF0000 +#define CONFIG_SYS_BR1_PRELIM ( CONFIG_SYS_SJA1000_BASE \ + | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR1_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_GPCM_SCY_5 \ + | OR_GPCM_EHTR) + /* 0xFFFF8052 */ + +#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_SJA1000_BASE +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* + * CPLD on Local Bus + */ +#define CONFIG_SYS_CPLD_BASE 0xFBFF8000 +#define CONFIG_SYS_BR2_PRELIM ( CONFIG_SYS_CPLD_BASE \ + | (1 << BR_PS_SHIFT) /* 8 bit port size */ \ + | BR_V ) /* valid */ +#define CONFIG_SYS_OR2_PRELIM ( 0xFFFF8000 /* length 32K */ \ + | OR_GPCM_SCY_4 \ + | OR_GPCM_EHTR) + /* 0xFFFF8042 */ + +#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_CPLD_BASE +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 +#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " + +/* Pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + +/* I2C */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_FSL_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* + * General PCI + * Addresses are mapped 1-1. + */ +#define CONFIG_SYS_PCIE1_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_BASE 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 +#define CONFIG_SYS_PCIE1_CFG_BASE 0xB0000000 +#define CONFIG_SYS_PCIE1_CFG_SIZE 0x01000000 +#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xB1000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 + +/* enable PCIE clock */ +#define CONFIG_SYS_SCCR_PCIEXP1CM 1 + +#define CONFIG_PCI +#define CONFIG_PCIE + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ +#define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1 + +/* + * TSEC + */ +#define CONFIG_NET_MULTI +#define CONFIG_TSEC_ENET /* TSEC ethernet support */ +#define CONFIG_SYS_TSEC1_OFFSET 0x24000 +#define CONFIG_SYS_TSEC1 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET) +#define CONFIG_SYS_TSEC2_OFFSET 0x25000 +#define CONFIG_SYS_TSEC2 (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC2_OFFSET) + +/* + * TSEC ethernet configuration + */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_TSEC1_NAME "eTSEC0" +#define CONFIG_TSEC2_NAME "eTSEC1" +#define TSEC1_PHY_ADDR 1 +#define TSEC2_PHY_ADDR 2 +#define TSEC1_PHYIDX 0 +#define TSEC2_PHYIDX 0 +#define TSEC1_FLAGS 0 +#define TSEC2_FLAGS 0 + +/* Options are: eTSEC[0-1] */ +#define CONFIG_ETHPRIME "eTSEC0" + +/* + * Environment + */ +#define CONFIG_ENV_IS_IN_FLASH 1 +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + \ + CONFIG_SYS_MONITOR_LEN) +#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ + +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ + +/* + * Core HID Setup + */ +#define CONFIG_SYS_HID0_INIT 0x000000000 +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE | \ + HID0_ENABLE_DYNAMIC_POWER_MANAGMENT) +#define CONFIG_SYS_HID2 HID2_HBE + +/* + * MMU Setup + */ + +/* DDR: cache cacheable */ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_128M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L +#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U + +/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ +#define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR | BATL_PP_10 | \ + BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | \ + BATU_VP) +#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L +#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U + +/* FLASH: icache cacheable, but dcache-inhibit and guarded */ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT2U (CONFIG_SYS_FLASH_BASE | BATU_BL_8M | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT2L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ + BATL_CACHEINHIBIT | \ + BATL_GUARDEDSTORAGE) +#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U + +/* Stack in dcache: cacheable, no memory coherence */ +#define CONFIG_SYS_IBAT3L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT3U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \ + BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L +#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Environment Configuration + */ + +#define CONFIG_ENV_OVERWRITE + +#if defined(CONFIG_TSEC_ENET) +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ + +#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ + +#define xstr(s) str(s) +#define str(s) #s + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "consoledev=ttyS0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs}" \ + " console=${consoledev},${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addmisc=setenv bootargs ${bootargs}\0" \ + "kernel_addr=FC0A0000\0" \ + "fdt_addr=FC2A0000\0" \ + "ramdisk_addr=FC2C0000\0" \ + "u-boot=mpc8308_p1m/u-boot.bin\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr_r=C00000\0" \ + "hostname=mpc8308_p1m\0" \ + "bootfile=mpc8308_p1m/uImage\0" \ + "fdtfile=mpc8308_p1m/mpc8308_p1m.dtb\0" \ + "rootpath=/opt/eldk-4.2/ppc_6xx\0" \ + "flash_self=run ramargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "flash_nfs=run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_nfs=tftp ${kernel_addr_r} ${bootfile};" \ + "tftp ${fdt_addr_r} ${fdtfile};" \ + "run nfsargs addip addtty addmtd addmisc;" \ + "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ + "bootcmd=run flash_self\0" \ + "load=tftp ${loadaddr} ${u-boot}\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};era " xstr(CONFIG_SYS_MONITOR_BASE) \ + " +${filesize};cp.b ${fileaddr} " \ + xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0" \ + "upd=run load update\0" \ + +#endif /* __CONFIG_H */ diff --git a/include/configs/mucmc52.h b/include/configs/mucmc52.h index 07ed046..f87dc9c 100644 --- a/include/configs/mucmc52.h +++ b/include/configs/mucmc52.h @@ -80,6 +80,8 @@ #define CONFIG_SYS_CS1_SIZE 0x00100000 #define CONFIG_SYS_CS1_CFG 0x00019B00 +#define CONFIG_SYS_SRAM_SIZE CONFIG_SYS_CS1_SIZE + /* FRAM 32Kbyte @0x80700000 */ #define CONFIG_SYS_CS2_START 0x80700000 #define CONFIG_SYS_CS2_SIZE 0x00008000 diff --git a/include/configs/neo.h b/include/configs/neo.h index f275c7b..f8f53e8 100644 --- a/include/configs/neo.h +++ b/include/configs/neo.h @@ -98,7 +98,12 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index cb7efe7..8f42b6c 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -34,7 +34,12 @@ /* * UART */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SERIAL_MULTI +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 9cb66b7..d11d218 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -58,7 +58,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -80,7 +79,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index 71553f9..2463be4 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -120,6 +120,7 @@ /* commands to include */ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_EXT2 /* EXT2 Support */ #define CONFIG_CMD_FAT /* FAT support */ #define CONFIG_CMD_JFFS2 /* JFFS2 Support */ @@ -339,4 +340,9 @@ extern unsigned int boot_flash_sec; extern unsigned int boot_flash_type; #endif +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (LOW_LEVEL_SRAM_STACK - CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index d6b9207..6edf91e 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -49,7 +49,6 @@ #define CONFIG_SYS_FLASH_BASE 0xff800000 /* start of FLASH */ #define CONFIG_SYS_MONITOR_BASE 0xfffc0000 /* start of monitor */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -80,6 +79,12 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK #define CONFIG_BAUDRATE 115200 diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index 1f744b8..85152d1 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -60,7 +60,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ @@ -80,11 +79,14 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clk used */ #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI 1 -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} diff --git a/include/configs/pdm360ng.h b/include/configs/pdm360ng.h index 718abdf..f073fcd 100644 --- a/include/configs/pdm360ng.h +++ b/include/configs/pdm360ng.h @@ -412,11 +412,11 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Cache Configuration */ #define CONFIG_SYS_DCACHE_SIZE 32768 diff --git a/include/configs/qong.h b/include/configs/qong.h index 100fa3f..7a68b7b 100644 --- a/include/configs/qong.h +++ b/include/configs/qong.h @@ -104,6 +104,7 @@ #include <config_cmd_default.h> +#define CONFIG_CMD_CACHE #define CONFIG_CMD_PING #define CONFIG_CMD_DHCP #define CONFIG_CMD_NET @@ -281,4 +282,14 @@ extern int qong_nand_rdy(void *chip); "mtdparts=physmap-flash.0:384k(U-Boot),128k(env1)," \ "128k(env2),2432k(kernel),13m(ramdisk),-(user)" +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE 0x80000000 +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_END IRAM_SIZE +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET) + +#define CONFIG_BOARD_EARLY_INIT_F 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/quad100hd.h b/include/configs/quad100hd.h index 5538b18..0764cc8 100644 --- a/include/configs/quad100hd.h +++ b/include/configs/quad100hd.h @@ -105,6 +105,11 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 115200 @@ -270,12 +275,12 @@ * Taken in part from PPCBoot board/icecube/icecube.h */ /* see ./arch/powerpc/cpu/ppc4xx/cpu_init.c ./cpu/ppc4xx/start.S */ -#define CONFIG_SYS_GPIO0_OSRH 0x55555550 -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 -#define CONFIG_SYS_GPIO0_ISR1L 0x15555445 -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x55555550 +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 +#define CONFIG_SYS_GPIO0_ISR1H 0x15555445 #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xFFFF8097 #define CONFIG_SYS_GPIO0_ODR 0x00000000 diff --git a/include/configs/redwood.h b/include/configs/redwood.h index 87adbf8..3c1e882 100644 --- a/include/configs/redwood.h +++ b/include/configs/redwood.h @@ -47,7 +47,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -77,6 +76,11 @@ #define CONFIG_SYS_FPGA_BASE 0xe2000000 /* epld */ #define CONFIG_SYS_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ +/* + * Serial Port + */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer (placed in internal SRAM) *----------------------------------------------------------------------*/ diff --git a/include/configs/sbc405.h b/include/configs/sbc405.h index 429b11c..187002c 100644 --- a/include/configs/sbc405.h +++ b/include/configs/sbc405.h @@ -147,6 +147,12 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index deaddde..b8f4b6e 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -270,7 +270,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -465,10 +464,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 564f661..8d047de 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -338,7 +338,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 53d06ed..6352278 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -203,7 +203,6 @@ #undef CONFIG_CONS_NONE /* define if console on something else */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 618513a..a7831c0 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -257,7 +257,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/sc3.h b/include/configs/sc3.h index 19084ce..278b60e 100644 --- a/include/configs/sc3.h +++ b/include/configs/sc3.h @@ -76,15 +76,12 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #define CONFIG_SERIAL_MULTI -#undef CONFIG_SERIAL_SOFTWARE_FIFO -/* - * define CONFIG_POWER_DOWN if your cpu should power down while waiting for your input - * Works only, if you have enabled the CONFIG_SERIAL_SOFTWARE_FIFO feature - */ -#if CONFIG_SERIAL_SOFTWARE_FIFO - #define CONFIG_POWER_DOWN -#endif /* * define CONFIG_SYS_CLK_FREQ to your base crystal clock in Hz diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index ee4391f..988d41f 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -84,9 +84,6 @@ #define CONFIG_SYS_PCI_MEMBASE2 CONFIG_SYS_PCI_MEMBASE1 + 0x10000000 #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 -/* Don't change either of these */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ - #define CONFIG_SYS_USB2D0_BASE 0xe0000100 #define CONFIG_SYS_USB_DEVICE 0xe0000000 #define CONFIG_SYS_USB_HOST 0xe0000400 @@ -105,9 +102,8 @@ /* * Serial Port */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ -/* define this if you want console on UART1 */ -#undef CONFIG_UART1_CONSOLE /* * Environment diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h deleted file mode 100644 index 060026b..0000000 --- a/include/configs/smmaco4.h +++ /dev/null @@ -1,379 +0,0 @@ -/* - * (C) Copyright 2003-2006 - * Wolfgang Denk, DENX Software Engineering, wd@denx.de. - * - * (C) Copyright 2004-2005 - * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -/* - * High Level Configuration Options - * (easy to change) - */ - -#define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ -#define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ -#define CONFIG_TQM5200 1 /* ... on TQM5200 module */ -#undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ - -#define CONFIG_SYS_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ - -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* - * Serial console configuration - */ -#define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ -#define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ -#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } - -/* Partitions */ -#define CONFIG_MAC_PARTITION -#define CONFIG_DOS_PARTITION -#define CONFIG_ISO_PARTITION - -/* POST support */ -#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ - CONFIG_SYS_POST_CPU | \ - CONFIG_SYS_POST_I2C) - -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 -#endif - - -/* - * BOOTP options - */ -#define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - - -/* - * Command line configuration. - */ -#include <config_cmd_default.h> -#define CONFIG_CMD_ASKENV -#define CONFIG_CMD_DATE -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ECHO -#define CONFIG_CMD_EEPROM -#define CONFIG_CMD_I2C -#define CONFIG_CMD_JFFS2 -#define CONFIG_CMD_MII -#define CONFIG_CMD_NFS -#define CONFIG_CMD_PING -#define CONFIG_CMD_REGINFO -#define CONFIG_CMD_SNTP - -#ifdef CONFIG_POST -#define CONFIG_CMD_DIAG -#endif - - -#define CONFIG_TIMESTAMP /* display image timestamps */ - -#if (TEXT_BASE == 0xFC000000) /* Boot low */ -# define CONFIG_SYS_LOWBOOT 1 -#endif - -/* - * Autobooting - */ -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ - -#define CONFIG_PREBOOT "echo;" \ - "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ - "echo" - -#undef CONFIG_BOOTARGS - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "netdev=eth0\0" \ - "rootpath=/opt/eldk/ppc_6xx\0" \ - "ramargs=setenv bootargs root=/dev/ram rw\0" \ - "nfsargs=setenv bootargs root=/dev/nfs rw " \ - "nfsroot=${serverip}:${rootpath}\0" \ - "addip=setenv bootargs ${bootargs} " \ - "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ - ":${hostname}:${netdev}:off panic=1\0" \ - "flash_self=run ramargs addip;" \ - "bootm ${kernel_addr} ${ramdisk_addr}\0" \ - "flash_nfs=run nfsargs addip;" \ - "bootm ${kernel_addr}\0" \ - "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ - "bootfile=/tftpboot/smmaco4/uImage\0" \ - "load=tftp 200000 ${u-boot}\0" \ - "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \ - "update=protect off FC000000 FC05FFFF;" \ - "erase FC000000 FC05FFFF;" \ - "cp.b 200000 FC000000 ${filesize};" \ - "protect on FC000000 FC05FFFF\0" \ - "" - -#define CONFIG_BOOTCOMMAND "run net_nfs" - -/* - * IPB Bus clocking configuration. - */ -#define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ - -#if defined(CONFIG_SYS_IPBCLK_EQUALS_XLBCLK) -/* - * PCI Bus clocking configuration - * - * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if - * CONFIG_SYS_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock - * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. - */ -#define CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ -#endif - -/* - * I2C configuration - */ -#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ -#ifdef CONFIG_TQM5200_REV100 -#define CONFIG_SYS_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ -#else -#define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ -#endif - -/* - * I2C clock frequency - * - * Please notice, that the resulting clock frequency could differ from the - * configured value. This is because the I2C clock is derived from system - * clock over a frequency divider with only a few divider values. U-boot - * calculates the best approximation for CONFIG_SYS_I2C_SPEED. However the calculated - * approximation allways lies below the configured value, never above. - */ -#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ -#define CONFIG_SYS_I2C_SLAVE 0x7F - -/* - * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work - * also). For other EEPROMs configuration should be verified. On Mini-FAP the - * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the - * same configuration could be used. - */ -#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* 1010000x */ -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ -#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 - -/* - * Flash configuration - */ -#define CONFIG_SYS_FLASH_BASE TEXT_BASE /* 0xFC000000 */ - -/* use CFI flash driver if no module variant is spezified */ -#define CONFIG_SYS_FLASH_CFI 1 /* Flash is CFI conformant */ -#define CONFIG_FLASH_CFI_DRIVER 1 /* Use the common driver */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_BOOTCS_START } -#define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_SIZE 0x04000000 /* 64 MByte */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 /* max num of sects on one chip */ -#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ - -#if !defined(CONFIG_SYS_LOWBOOT) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00760000 + 0x00800000) -#else /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00060000) -#endif /* CONFIG_SYS_LOWBOOT */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks - (= chip selects) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ - -/* Dynamic MTD partition support */ -#define CONFIG_CMD_MTDPARTS -#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ -#define CONFIG_FLASH_CFI_MTD -#define MTDIDS_DEFAULT "nor0=TQM5200-0" -#define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ - "1408k(kernel)," \ - "2m(initrd)," \ - "4m(small-fs)," \ - "16m(big-fs)," \ - "8m(misc)" - -/* - * Environment settings - */ -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 -#define CONFIG_ENV_SECT_SIZE 0x20000 -#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) - -/* - * Memory map - */ -#define CONFIG_SYS_MBAR 0xF0000000 -#define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_DEFAULT_MBAR 0x80000000 - -/* Use ON-Chip SRAM until RAM will be available */ -#define CONFIG_SYS_INIT_RAM_ADDR MPC5XXX_SRAM -#ifdef CONFIG_POST -/* preserve space for the post_word at end of on-chip SRAM */ -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE -#else -#define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE -#endif - - -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET - -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) -# define CONFIG_SYS_RAMBOOT 1 -#endif - -#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ - -/* - * Ethernet configuration - */ -#define CONFIG_MPC5xxx_FEC 1 -/* - * Define CONFIG_FEC_10MBIT to force FEC at 10Mb - */ -/* #define CONFIG_FEC_10MBIT 1 */ -#define CONFIG_PHY_ADDR 0x00 - -/* - * GPIO configuration - * - * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): - * Bit 0 (mask: 0x80000000): 1 - * use ALT CAN position: Bits 2-3 (mask: 0x30000000): - * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. - * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. - * Use for REV200 STK52XX boards. Do not use with REV100 modules - * (because, there I2C1 is used as I2C bus) - * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 - * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) - * 000 -> All PSC2 pins are GIOPs - * 001 -> CAN1/2 on PSC2 pins - * Use for REV100 STK52xx boards - * use PSC6: - * on STK52xx: - * use as UART. Pins PSC6_0 to PSC6_3 are used. - * Bits 9:11 (mask: 0x00700000): - * 101 -> PSC6 : Extended POST test is not available - * on MINI-FAP and TQM5200_IB: - * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): - * 000 -> PSC6 could not be used as UART, CODEC or IrDA - * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST - * tests. - */ -#if defined (CONFIG_MINIFAP) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91000004 -#elif defined (CONFIG_STK52XX) -# if defined (CONFIG_STK52XX_REV100) -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81500014 -# else /* STK52xx REV200 and above */ -# if defined (CONFIG_TQM5200_REV100) -# error TQM5200 REV100 not supported on STK52XX REV200 or above -# else/* TQM5200 REV200 and above */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x91500004 -# endif -# endif -#else /* TMQ5200 Inbetriebnahme-Board */ -# define CONFIG_SYS_GPS_PORT_CONFIG 0x81000004 -#endif - -/* - * RTC configuration - */ -#define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ - -/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -/* Enable an alternate, more extensive memory test */ -#define CONFIG_SYS_ALT_MEMTEST - -#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ - -#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ - -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ - -#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ -#if defined(CONFIG_CMD_KGDB) -# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - -/* - * Enable loopw command. - */ -#define CONFIG_LOOPW - -/* - * Various low-level settings - */ -#define CONFIG_SYS_HID0_INIT HID0_ICE | HID0_ICFI -#define CONFIG_SYS_HID0_FINAL HID0_ICE - -#define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_BOOTCS_SIZE CONFIG_SYS_FLASH_SIZE -#ifdef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2 -#define CONFIG_SYS_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ -#else -#define CONFIG_SYS_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ -#endif -#define CONFIG_SYS_CS0_START CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_CS0_SIZE CONFIG_SYS_FLASH_SIZE - -#define CONFIG_SYS_CS_BURST 0x00000000 -#define CONFIG_SYS_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ - -#define CONFIG_SYS_RESET_ADDRESS 0xff000000 - -#endif /* __CONFIG_H */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index af1e19e..88be349 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -218,7 +218,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 57bb8d1..911c906 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -176,7 +176,6 @@ /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/t3corp.h b/include/configs/t3corp.h index b38886b..39ca793 100644 --- a/include/configs/t3corp.h +++ b/include/configs/t3corp.h @@ -86,10 +86,9 @@ #define CONFIG_SYS_OCM_BASE 0xE7000000 /* OCM: 64k */ #define CONFIG_SYS_SRAM_BASE 0xE8000000 /* SRAM: 256k */ +#define CONFIG_SYS_SRAM_SIZE (256 << 10) #define CONFIG_SYS_LOCAL_CONF_REGS 0xEF000000 -#define CONFIG_SYS_PERIPHERAL_BASE 0xEF600000 /* internal periph. */ - /* * Initial RAM & stack pointer (placed in OCM) */ @@ -103,7 +102,7 @@ /* * Serial Port */ -#undef CONFIG_UART1_CONSOLE /* define this if you want console on UART1 */ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ /* * Environment diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 836081d..7e660ee 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -127,11 +127,10 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE 1 /*----------------------------------------------------------------------- * I2C stuff diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 394dd8d..faf9e20 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -50,7 +50,6 @@ *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xe0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */ #define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */ @@ -76,7 +75,7 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#define CONFIG_UART1_CONSOLE 1 /* use of UART1 as console */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */ /*----------------------------------------------------------------------- diff --git a/include/configs/tx25.h b/include/configs/tx25.h index c8188ca..c798570 100644 --- a/include/configs/tx25.h +++ b/include/configs/tx25.h @@ -40,9 +40,9 @@ /* Start copying real U-boot from the second page */ #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x800 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x30000 -/* Load U-Boot to this address */ -#define CONFIG_SYS_NAND_U_BOOT_DST 0x81f00000 -#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST + +#define CONFIG_SYS_NAND_U_BOOT_DST (0x81fc0000) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #define CONFIG_SYS_NAND_PAGE_SIZE 2048 #define CONFIG_SYS_NAND_SPARE_SIZE 64 @@ -52,7 +52,6 @@ #define CONFIG_SYS_NAND_BAD_BLOCK_POS 0 #else #define CONFIG_SKIP_LOWLEVEL_INIT -#define CONFIG_SKIP_RELOCATE_UBOOT #endif #define CONFIG_DISPLAY_CPUINFO @@ -131,6 +130,7 @@ /* U-Boot commands */ #include <config_cmd_default.h> #define CONFIG_CMD_NAND +#define CONFIG_CMD_CACHE /* * Ethernet @@ -176,4 +176,10 @@ "update=nand erase 0 40000;nand write ${loadaddr} 0 40000\0" \ "upd=run load update\0" \ +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC /* This board is tested with relocation support */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - /* Fix this */ \ + CONFIG_SYS_GBL_DATA_SIZE) + #endif /* __CONFIG_H */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index fc0b103..1972261 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -65,9 +65,7 @@ #define CONFIG_SYS_IB_EPLD 0xc0500000 /* CS 7 */ /* SRAM */ -#define SRAM_BASE CONFIG_SYS_SRAM_BASE -#define SRAM_LEN 0x1fffff -#define SRAM_END (SRAM_BASE + SRAM_LEN) +#define CONFIG_SYS_SRAM_SIZE 0x200000 /* * GPIO configuration diff --git a/include/configs/ve8313.h b/include/configs/ve8313.h index 56d24f9..45976db 100644 --- a/include/configs/ve8313.h +++ b/include/configs/ve8313.h @@ -366,10 +366,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ /* 0x64050000 */ #define CONFIG_SYS_HRCW_LOW (\ diff --git a/include/configs/vme8349.h b/include/configs/vme8349.h index f493e75..f2fb592 100644 --- a/include/configs/vme8349.h +++ b/include/configs/vme8349.h @@ -184,7 +184,6 @@ * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -402,10 +401,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Init Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Init Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index 630c0d3..3be489d 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -84,7 +84,7 @@ * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock, * set Linux BASE_BAUD to 403200. */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ #undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */ #define CONFIG_SYS_BASE_BAUD 691200 diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index b66ab58..ed0560a 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -62,7 +62,6 @@ #define CONFIG_SYS_PCI_MEMBASE3 CONFIG_SYS_PCI_MEMBASE2 + 0x10000000 /*Don't change either of these*/ -#define CONFIG_SYS_PERIPHERAL_BASE 0xef600000 /* internal peripherals*/ #define CONFIG_SYS_PCI_BASE 0xe0000000 /* internal PCI regs*/ /*Don't change either of these*/ @@ -84,9 +83,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ #define CONFIG_SYS_EXT_SERIAL_CLOCK 11059200 /* use external 11.059MHz clk */ -/*define this if you want console on UART1*/ -#undef CONFIG_UART1_CONSOLE /*----------------------------------------------------------------------- * Environment diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 798c75a..4e64eec 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -60,7 +60,6 @@ * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ #define CONFIG_SYS_FLASH_BASE 0xfff00000 /* start of FLASH */ -#define CONFIG_SYS_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ #define CONFIG_SYS_ISRAM_BASE 0x90000000 /* internal SRAM */ #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped PCI memory */ @@ -105,9 +104,8 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ -#undef CONFIG_UART1_CONSOLE +#define CONFIG_CONS_INDEX 1 /* Use UART0 */ -#undef CONFIG_SERIAL_SOFTWARE_FIFO #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* #define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) */ /* Ext clk @ 11.059 MHz */ diff --git a/include/configs/zeus.h b/include/configs/zeus.h index 29ada9e..aa250cc 100644 --- a/include/configs/zeus.h +++ b/include/configs/zeus.h @@ -122,14 +122,18 @@ /*----------------------------------------------------------------------- * Serial Port *----------------------------------------------------------------------*/ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */ -#define CONFIG_SYS_BASE_BAUD 691200 +#define CONFIG_SYS_BASE_BAUD 691200 #define CONFIG_BAUDRATE 115200 #define CONFIG_SERIAL_MULTI -/* The following table includes the supported baudrates */ -#define CONFIG_SYS_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200, 230400} /*----------------------------------------------------------------------- * Miscellaneous configurable options @@ -280,12 +284,12 @@ * GPIO0[28-29] - UART1 data signal input/output * GPIO0[30-31] - EMAC0 and EMAC1 reject packet inputs */ -#define CONFIG_SYS_GPIO0_OSRH 0x15555550 /* Chip selects */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* UART_DTR-pin 27 alt out */ -#define CONFIG_SYS_GPIO0_ISR1H 0x10000041 /* Pin 2, 12 is input */ -#define CONFIG_SYS_GPIO0_ISR1L 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 +#define CONFIG_SYS_GPIO0_OSRL 0x15555550 /* Chip selects */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* UART_DTR-pin 27 alt out */ +#define CONFIG_SYS_GPIO0_ISR1L 0x10000041 /* Pin 2, 12 is input */ +#define CONFIG_SYS_GPIO0_ISR1H 0x15505440 /* OUT: LEDs 22/23; IN: pin12,2, NVALID# */ #define CONFIG_SYS_GPIO0_TSRL 0x00000000 +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 #define CONFIG_SYS_GPIO0_TCR 0xBFF68317 /* 3-state OUT: 22/23/29; 12,2 is not 3-state */ #define CONFIG_SYS_GPIO0_ODR 0x00000000 diff --git a/include/environment.h b/include/environment.h index fbccf6a..bedbc54 100644 --- a/include/environment.h +++ b/include/environment.h @@ -160,6 +160,9 @@ unsigned char env_get_char_memory (int index); void env_crc_update (void); /* [re]set to the default environment */ -void set_default_env(void); +void set_default_env(const char *s); + +/* Import from binary representation into hash table */ +int env_import(const char *buf, int check); #endif /* _ENVIRONMENT_H_ */ diff --git a/include/errno.h b/include/errno.h new file mode 100644 index 0000000..e24a33b --- /dev/null +++ b/include/errno.h @@ -0,0 +1,9 @@ +#ifndef _ERRNO_H + +#include <asm-generic/errno.h> + +extern int errno; + +#define __set_errno(val) do { errno = val; } while (0) + +#endif /* _ERRNO_H */ diff --git a/include/exports.h b/include/exports.h index 1d79a31..7404a7c 100644 --- a/include/exports.h +++ b/include/exports.h @@ -26,9 +26,6 @@ int setenv (char *varname, char *varvalue); long simple_strtol(const char *cp,char **endp,unsigned int base); int strcmp(const char * cs,const char * ct); int ustrtoul(const char *cp, char **endp, unsigned int base); -#ifdef CONFIG_HAS_UID -void forceenv (char *varname, char *varvalue); -#endif #if defined(CONFIG_CMD_I2C) int i2c_write (uchar, uint, int , uchar* , int); int i2c_read (uchar, uint, int , uchar* , int); diff --git a/include/flash.h b/include/flash.h index 8feca1b..1b6821a 100644 --- a/include/flash.h +++ b/include/flash.h @@ -58,6 +58,8 @@ typedef struct { #endif } flash_info_t; +extern flash_info_t flash_info[]; /* info for FLASH chips */ + typedef unsigned long flash_sect_t; /* diff --git a/include/image.h b/include/image.h index bcc08d1..18a9f0e 100644 --- a/include/image.h +++ b/include/image.h @@ -83,6 +83,7 @@ #define IH_OS_ARTOS 19 /* ARTOS */ #define IH_OS_UNITY 20 /* Unity OS */ #define IH_OS_INTEGRITY 21 /* INTEGRITY */ +#define IH_OS_OSE 22 /* OSE */ /* * CPU Architecture Codes (supported by Linux) diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h new file mode 100644 index 0000000..03541cb --- /dev/null +++ b/include/linux/usb/cdc.h @@ -0,0 +1,224 @@ +/* + * USB Communications Device Class (CDC) definitions + * + * CDC says how to talk to lots of different types of network adapters, + * notably ethernet adapters and various modems. It's used mostly with + * firmware based USB peripherals. + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + + + +#define USB_CDC_SUBCLASS_ACM 0x02 +#define USB_CDC_SUBCLASS_ETHERNET 0x06 +#define USB_CDC_SUBCLASS_WHCM 0x08 +#define USB_CDC_SUBCLASS_DMM 0x09 +#define USB_CDC_SUBCLASS_MDLM 0x0a +#define USB_CDC_SUBCLASS_OBEX 0x0b + +#define USB_CDC_PROTO_NONE 0 + +#define USB_CDC_ACM_PROTO_AT_V25TER 1 +#define USB_CDC_ACM_PROTO_AT_PCCA101 2 +#define USB_CDC_ACM_PROTO_AT_PCCA101_WAKE 3 +#define USB_CDC_ACM_PROTO_AT_GSM 4 +#define USB_CDC_ACM_PROTO_AT_3G 5 +#define USB_CDC_ACM_PROTO_AT_CDMA 6 +#define USB_CDC_ACM_PROTO_VENDOR 0xff + +/*-------------------------------------------------------------------------*/ + +/* + * Class-Specific descriptors ... there are a couple dozen of them + */ + +#define USB_CDC_HEADER_TYPE 0x00 /* header_desc */ +#define USB_CDC_CALL_MANAGEMENT_TYPE 0x01 /* call_mgmt_descriptor */ +#define USB_CDC_ACM_TYPE 0x02 /* acm_descriptor */ +#define USB_CDC_UNION_TYPE 0x06 /* union_desc */ +#define USB_CDC_COUNTRY_TYPE 0x07 +#define USB_CDC_NETWORK_TERMINAL_TYPE 0x0a /* network_terminal_desc */ +#define USB_CDC_ETHERNET_TYPE 0x0f /* ether_desc */ +#define USB_CDC_WHCM_TYPE 0x11 +#define USB_CDC_MDLM_TYPE 0x12 /* mdlm_desc */ +#define USB_CDC_MDLM_DETAIL_TYPE 0x13 /* mdlm_detail_desc */ +#define USB_CDC_DMM_TYPE 0x14 +#define USB_CDC_OBEX_TYPE 0x15 + +/* "Header Functional Descriptor" from CDC spec 5.2.3.1 */ +struct usb_cdc_header_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __le16 bcdCDC; +} __attribute__ ((packed)); + +/* "Call Management Descriptor" from CDC spec 5.2.3.2 */ +struct usb_cdc_call_mgmt_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 bmCapabilities; +#define USB_CDC_CALL_MGMT_CAP_CALL_MGMT 0x01 +#define USB_CDC_CALL_MGMT_CAP_DATA_INTF 0x02 + + __u8 bDataInterface; +} __attribute__ ((packed)); + +/* "Abstract Control Management Descriptor" from CDC spec 5.2.3.3 */ +struct usb_cdc_acm_descriptor { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 bmCapabilities; +} __attribute__ ((packed)); + +/* capabilities from 5.2.3.3 */ + +#define USB_CDC_COMM_FEATURE 0x01 +#define USB_CDC_CAP_LINE 0x02 +#define USB_CDC_CAP_BRK 0x04 +#define USB_CDC_CAP_NOTIFY 0x08 + +/* "Union Functional Descriptor" from CDC spec 5.2.3.8 */ +struct usb_cdc_union_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 bMasterInterface0; + __u8 bSlaveInterface0; + /* ... and there could be other slave interfaces */ +} __attribute__ ((packed)); + +/* "Country Selection Functional Descriptor" from CDC spec 5.2.3.9 */ +struct usb_cdc_country_functional_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 iCountryCodeRelDate; + __le16 wCountyCode0; + /* ... and there can be a lot of country codes */ +} __attribute__ ((packed)); + +/* "Network Channel Terminal Functional Descriptor" from CDC spec 5.2.3.11 */ +struct usb_cdc_network_terminal_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 bEntityId; + __u8 iName; + __u8 bChannelIndex; + __u8 bPhysicalInterface; +} __attribute__ ((packed)); + +/* "Ethernet Networking Functional Descriptor" from CDC spec 5.2.3.16 */ +struct usb_cdc_ether_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __u8 iMACAddress; + __le32 bmEthernetStatistics; + __le16 wMaxSegmentSize; + __le16 wNumberMCFilters; + __u8 bNumberPowerFilters; +} __attribute__ ((packed)); + +/* "MDLM Functional Descriptor" from CDC WMC spec 6.7.2.3 */ +struct usb_cdc_mdlm_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + __le16 bcdVersion; + __u8 bGUID[16]; +} __attribute__ ((packed)); + +/* "MDLM Detail Functional Descriptor" from CDC WMC spec 6.7.2.4 */ +struct usb_cdc_mdlm_detail_desc { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDescriptorSubType; + + /* type is associated with mdlm_desc.bGUID */ + __u8 bGuidDescriptorType; + __u8 bDetailData[0]; +} __attribute__ ((packed)); + +/*-------------------------------------------------------------------------*/ + +/* + * Class-Specific Control Requests (6.2) + * + * section 3.6.2.1 table 4 has the ACM profile, for modems. + * section 3.8.2 table 10 has the ethernet profile. + */ + +#define USB_CDC_SEND_ENCAPSULATED_COMMAND 0x00 +#define USB_CDC_GET_ENCAPSULATED_RESPONSE 0x01 +#define USB_CDC_REQ_SET_LINE_CODING 0x20 +#define USB_CDC_REQ_GET_LINE_CODING 0x21 +#define USB_CDC_REQ_SET_CONTROL_LINE_STATE 0x22 +#define USB_CDC_REQ_SEND_BREAK 0x23 +#define USB_CDC_SET_ETHERNET_MULTICAST_FILTERS 0x40 +#define USB_CDC_SET_ETHERNET_PM_PATTERN_FILTER 0x41 +#define USB_CDC_GET_ETHERNET_PM_PATTERN_FILTER 0x42 +#define USB_CDC_SET_ETHERNET_PACKET_FILTER 0x43 +#define USB_CDC_GET_ETHERNET_STATISTIC 0x44 + +/* Line Coding Structure from CDC spec 6.2.13 */ +struct usb_cdc_line_coding { + __le32 dwDTERate; + __u8 bCharFormat; +#define USB_CDC_1_STOP_BITS 0 +#define USB_CDC_1_5_STOP_BITS 1 +#define USB_CDC_2_STOP_BITS 2 + + __u8 bParityType; +#define USB_CDC_NO_PARITY 0 +#define USB_CDC_ODD_PARITY 1 +#define USB_CDC_EVEN_PARITY 2 +#define USB_CDC_MARK_PARITY 3 +#define USB_CDC_SPACE_PARITY 4 + + __u8 bDataBits; +} __attribute__ ((packed)); + +/* table 62; bits in multicast filter */ +#define USB_CDC_PACKET_TYPE_PROMISCUOUS (1 << 0) +#define USB_CDC_PACKET_TYPE_ALL_MULTICAST (1 << 1) /* no filter */ +#define USB_CDC_PACKET_TYPE_DIRECTED (1 << 2) +#define USB_CDC_PACKET_TYPE_BROADCAST (1 << 3) +#define USB_CDC_PACKET_TYPE_MULTICAST (1 << 4) /* filtered */ + + +/*-------------------------------------------------------------------------*/ + +/* + * Class-Specific Notifications (6.3) sent by interrupt transfers + * + * section 3.8.2 table 11 of the CDC spec lists Ethernet notifications + * section 3.6.2.1 table 5 specifies ACM notifications + */ + +#define USB_CDC_NOTIFY_NETWORK_CONNECTION 0x00 +#define USB_CDC_NOTIFY_RESPONSE_AVAILABLE 0x01 +#define USB_CDC_NOTIFY_SERIAL_STATE 0x20 +#define USB_CDC_NOTIFY_SPEED_CHANGE 0x2a + +struct usb_cdc_notification { + __u8 bmRequestType; + __u8 bNotificationType; + __le16 wValue; + __le16 wIndex; + __le16 wLength; +} __attribute__ ((packed)); + diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h new file mode 100644 index 0000000..49b7483 --- /dev/null +++ b/include/linux/usb/ch9.h @@ -0,0 +1,587 @@ +/* + * This file holds USB constants and structures that are needed for + * USB device APIs. These are used by the USB device model, which is + * defined in chapter 9 of the USB 2.0 specification and in the + * Wireless USB 1.0 (spread around). Linux has several APIs in C that + * need these: + * + * - the master/host side Linux-USB kernel driver API; + * - the "usbfs" user space API; and + * - the Linux "gadget" slave/device/peripheral side driver API. + * + * USB 2.0 adds an additional "On The Go" (OTG) mode, which lets systems + * act either as a USB master/host or as a USB slave/device. That means + * the master and slave side APIs benefit from working well together. + * + * There's also "Wireless USB", using low power short range radios for + * peripheral interconnection but otherwise building on the USB framework. + * + * Note all descriptors are declared '__attribute__((packed))' so that: + * + * [a] they never get padded, either internally (USB spec writers + * probably handled that) or externally; + * + * [b] so that accessing bigger-than-a-bytes fields will never + * generate bus errors on any platform, even when the location of + * its descriptor inside a bundle isn't "naturally aligned", and + * + * [c] for consistency, removing all doubt even when it appears to + * someone that the two other points are non-issues for that + * particular descriptor type. + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + +#ifndef __LINUX_USB_CH9_H +#define __LINUX_USB_CH9_H + +#include <linux/types.h> /* __u8 etc */ + +/*-------------------------------------------------------------------------*/ + +/* CONTROL REQUEST SUPPORT */ + +/* + * USB directions + * + * This bit flag is used in endpoint descriptors' bEndpointAddress field. + * It's also one of three fields in control requests bRequestType. + */ +#define USB_DIR_OUT 0 /* to device */ +#define USB_DIR_IN 0x80 /* to host */ + +/* + * USB types, the second of three bRequestType fields + */ +#define USB_TYPE_MASK (0x03 << 5) +#define USB_TYPE_STANDARD (0x00 << 5) +#define USB_TYPE_CLASS (0x01 << 5) +#define USB_TYPE_VENDOR (0x02 << 5) +#define USB_TYPE_RESERVED (0x03 << 5) + +/* + * USB recipients, the third of three bRequestType fields + */ +#define USB_RECIP_MASK 0x1f +#define USB_RECIP_DEVICE 0x00 +#define USB_RECIP_INTERFACE 0x01 +#define USB_RECIP_ENDPOINT 0x02 +#define USB_RECIP_OTHER 0x03 +/* From Wireless USB 1.0 */ +#define USB_RECIP_PORT 0x04 +#define USB_RECIP_RPIPE 0x05 + +/* + * Standard requests, for the bRequest field of a SETUP packet. + * + * These are qualified by the bRequestType field, so that for example + * TYPE_CLASS or TYPE_VENDOR specific feature flags could be retrieved + * by a GET_STATUS request. + */ +#define USB_REQ_GET_STATUS 0x00 +#define USB_REQ_CLEAR_FEATURE 0x01 +#define USB_REQ_SET_FEATURE 0x03 +#define USB_REQ_SET_ADDRESS 0x05 +#define USB_REQ_GET_DESCRIPTOR 0x06 +#define USB_REQ_SET_DESCRIPTOR 0x07 +#define USB_REQ_GET_CONFIGURATION 0x08 +#define USB_REQ_SET_CONFIGURATION 0x09 +#define USB_REQ_GET_INTERFACE 0x0A +#define USB_REQ_SET_INTERFACE 0x0B +#define USB_REQ_SYNCH_FRAME 0x0C + +#define USB_REQ_SET_ENCRYPTION 0x0D /* Wireless USB */ +#define USB_REQ_GET_ENCRYPTION 0x0E +#define USB_REQ_RPIPE_ABORT 0x0E +#define USB_REQ_SET_HANDSHAKE 0x0F +#define USB_REQ_RPIPE_RESET 0x0F +#define USB_REQ_GET_HANDSHAKE 0x10 +#define USB_REQ_SET_CONNECTION 0x11 +#define USB_REQ_SET_SECURITY_DATA 0x12 +#define USB_REQ_GET_SECURITY_DATA 0x13 +#define USB_REQ_SET_WUSB_DATA 0x14 +#define USB_REQ_LOOPBACK_DATA_WRITE 0x15 +#define USB_REQ_LOOPBACK_DATA_READ 0x16 +#define USB_REQ_SET_INTERFACE_DS 0x17 + +/* + * USB feature flags are written using USB_REQ_{CLEAR,SET}_FEATURE, and + * are read as a bit array returned by USB_REQ_GET_STATUS. (So there + * are at most sixteen features of each type.) + */ +#define USB_DEVICE_SELF_POWERED 0 /* (read only) */ +#define USB_DEVICE_REMOTE_WAKEUP 1 /* dev may initiate wakeup */ +#define USB_DEVICE_TEST_MODE 2 /* (wired high speed only) */ +#define USB_DEVICE_BATTERY 2 /* (wireless) */ +#define USB_DEVICE_B_HNP_ENABLE 3 /* (otg) dev may initiate HNP */ +#define USB_DEVICE_WUSB_DEVICE 3 /* (wireless)*/ +#define USB_DEVICE_A_HNP_SUPPORT 4 /* (otg) RH port supports HNP */ +#define USB_DEVICE_A_ALT_HNP_SUPPORT 5 /* (otg) other RH port does */ +#define USB_DEVICE_DEBUG_MODE 6 /* (special devices only) */ + +#define USB_ENDPOINT_HALT 0 /* IN/OUT will STALL */ + + +/** + * struct usb_ctrlrequest - SETUP data for a USB device control request + * @bRequestType: matches the USB bmRequestType field + * @bRequest: matches the USB bRequest field + * @wValue: matches the USB wValue field (le16 byte order) + * @wIndex: matches the USB wIndex field (le16 byte order) + * @wLength: matches the USB wLength field (le16 byte order) + * + * This structure is used to send control requests to a USB device. It matches + * the different fields of the USB 2.0 Spec section 9.3, table 9-2. See the + * USB spec for a fuller description of the different fields, and what they are + * used for. + * + * Note that the driver for any interface can issue control requests. + * For most devices, interfaces don't coordinate with each other, so + * such requests may be made at any time. + */ +#if defined(__BIG_ENDIAN) || defined(__ARMEB__) +#error (functionality not verified for big endian targets, todo...) +#endif + +struct usb_ctrlrequest { + __u8 bRequestType; + __u8 bRequest; + __le16 wValue; + __le16 wIndex; + __le16 wLength; +} __attribute__ ((packed)); + +/*-------------------------------------------------------------------------*/ + +/* + * STANDARD DESCRIPTORS ... as returned by GET_DESCRIPTOR, or + * (rarely) accepted by SET_DESCRIPTOR. + * + * Note that all multi-byte values here are encoded in little endian + * byte order "on the wire". But when exposed through Linux-USB APIs, + * they've been converted to cpu byte order. + */ + +/* + * Descriptor types ... USB 2.0 spec table 9.5 + */ +#define USB_DT_DEVICE 0x01 +#define USB_DT_CONFIG 0x02 +#define USB_DT_STRING 0x03 +#define USB_DT_INTERFACE 0x04 +#define USB_DT_ENDPOINT 0x05 +#define USB_DT_DEVICE_QUALIFIER 0x06 +#define USB_DT_OTHER_SPEED_CONFIG 0x07 +#define USB_DT_INTERFACE_POWER 0x08 +/* these are from a minor usb 2.0 revision (ECN) */ +#define USB_DT_OTG 0x09 +#define USB_DT_DEBUG 0x0a +#define USB_DT_INTERFACE_ASSOCIATION 0x0b +/* these are from the Wireless USB spec */ +#define USB_DT_SECURITY 0x0c +#define USB_DT_KEY 0x0d +#define USB_DT_ENCRYPTION_TYPE 0x0e +#define USB_DT_BOS 0x0f +#define USB_DT_DEVICE_CAPABILITY 0x10 +#define USB_DT_WIRELESS_ENDPOINT_COMP 0x11 +#define USB_DT_WIRE_ADAPTER 0x21 +#define USB_DT_RPIPE 0x22 + +/* Conventional codes for class-specific descriptors. The convention is + * defined in the USB "Common Class" Spec (3.11). Individual class specs + * are authoritative for their usage, not the "common class" writeup. + */ +#define USB_DT_CS_DEVICE (USB_TYPE_CLASS | USB_DT_DEVICE) +#define USB_DT_CS_CONFIG (USB_TYPE_CLASS | USB_DT_CONFIG) +#define USB_DT_CS_STRING (USB_TYPE_CLASS | USB_DT_STRING) +#define USB_DT_CS_INTERFACE (USB_TYPE_CLASS | USB_DT_INTERFACE) +#define USB_DT_CS_ENDPOINT (USB_TYPE_CLASS | USB_DT_ENDPOINT) + +/* All standard descriptors have these 2 fields at the beginning */ +struct usb_descriptor_header { + __u8 bLength; + __u8 bDescriptorType; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE: Device descriptor */ +struct usb_device_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 bcdUSB; + __u8 bDeviceClass; + __u8 bDeviceSubClass; + __u8 bDeviceProtocol; + __u8 bMaxPacketSize0; + __le16 idVendor; + __le16 idProduct; + __le16 bcdDevice; + __u8 iManufacturer; + __u8 iProduct; + __u8 iSerialNumber; + __u8 bNumConfigurations; +} __attribute__ ((packed)); + +#define USB_DT_DEVICE_SIZE 18 + + +/* + * Device and/or Interface Class codes + * as found in bDeviceClass or bInterfaceClass + * and defined by www.usb.org documents + */ +#define USB_CLASS_PER_INTERFACE 0 /* for DeviceClass */ +#define USB_CLASS_AUDIO 1 +#define USB_CLASS_COMM 2 +#define USB_CLASS_HID 3 +#define USB_CLASS_PHYSICAL 5 +#define USB_CLASS_STILL_IMAGE 6 +#define USB_CLASS_PRINTER 7 +#define USB_CLASS_MASS_STORAGE 8 +#define USB_CLASS_HUB 9 +#define USB_CLASS_CDC_DATA 0x0a +#define USB_CLASS_CSCID 0x0b /* chip+ smart card */ +#define USB_CLASS_CONTENT_SEC 0x0d /* content security */ +#define USB_CLASS_VIDEO 0x0e +#define USB_CLASS_WIRELESS_CONTROLLER 0xe0 +#define USB_CLASS_MISC 0xef +#define USB_CLASS_APP_SPEC 0xfe +#define USB_CLASS_VENDOR_SPEC 0xff + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_CONFIG: Configuration descriptor information. + * + * USB_DT_OTHER_SPEED_CONFIG is the same descriptor, except that the + * descriptor type is different. Highspeed-capable devices can look + * different depending on what speed they're currently running. Only + * devices with a USB_DT_DEVICE_QUALIFIER have any OTHER_SPEED_CONFIG + * descriptors. + */ +struct usb_config_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumInterfaces; + __u8 bConfigurationValue; + __u8 iConfiguration; + __u8 bmAttributes; + __u8 bMaxPower; +} __attribute__ ((packed)); + +#define USB_DT_CONFIG_SIZE 9 + +/* from config descriptor bmAttributes */ +#define USB_CONFIG_ATT_ONE (1 << 7) /* must be set */ +#define USB_CONFIG_ATT_SELFPOWER (1 << 6) /* self powered */ +#define USB_CONFIG_ATT_WAKEUP (1 << 5) /* can wakeup */ +#define USB_CONFIG_ATT_BATTERY (1 << 4) /* battery powered */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_STRING: String descriptor */ +struct usb_string_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wData[1]; /* UTF-16LE encoded */ +} __attribute__ ((packed)); + +/* note that "string" zero is special, it holds language codes that + * the device supports, not Unicode characters. + */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE: Interface descriptor */ +struct usb_interface_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bInterfaceNumber; + __u8 bAlternateSetting; + __u8 bNumEndpoints; + __u8 bInterfaceClass; + __u8 bInterfaceSubClass; + __u8 bInterfaceProtocol; + __u8 iInterface; +} __attribute__ ((packed)); + +#define USB_DT_INTERFACE_SIZE 9 + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENDPOINT: Endpoint descriptor */ +struct usb_endpoint_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bEndpointAddress; + __u8 bmAttributes; + __le16 wMaxPacketSize; + __u8 bInterval; + + /* NOTE: these two are _only_ in audio endpoints. */ + /* use USB_DT_ENDPOINT*_SIZE in bLength, not sizeof. */ + __u8 bRefresh; + __u8 bSynchAddress; +} __attribute__ ((packed)); + +#define USB_DT_ENDPOINT_SIZE 7 +#define USB_DT_ENDPOINT_AUDIO_SIZE 9 /* Audio extension */ + + +/* + * Endpoints + */ +#define USB_ENDPOINT_NUMBER_MASK 0x0f /* in bEndpointAddress */ +#define USB_ENDPOINT_DIR_MASK 0x80 + +#define USB_ENDPOINT_XFERTYPE_MASK 0x03 /* in bmAttributes */ +#define USB_ENDPOINT_XFER_CONTROL 0 +#define USB_ENDPOINT_XFER_ISOC 1 +#define USB_ENDPOINT_XFER_BULK 2 +#define USB_ENDPOINT_XFER_INT 3 +#define USB_ENDPOINT_MAX_ADJUSTABLE 0x80 + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_QUALIFIER: Device Qualifier descriptor */ +struct usb_qualifier_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 bcdUSB; + __u8 bDeviceClass; + __u8 bDeviceSubClass; + __u8 bDeviceProtocol; + __u8 bMaxPacketSize0; + __u8 bNumConfigurations; + __u8 bRESERVED; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_OTG (from OTG 1.0a supplement) */ +struct usb_otg_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bmAttributes; /* support for HNP, SRP, etc */ +} __attribute__ ((packed)); + +/* from usb_otg_descriptor.bmAttributes */ +#define USB_OTG_SRP (1 << 0) +#define USB_OTG_HNP (1 << 1) /* swap host/device roles */ + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEBUG: for special highspeed devices, replacing serial console */ +struct usb_debug_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + /* bulk endpoints with 8 byte maxpacket */ + __u8 bDebugInEndpoint; + __u8 bDebugOutEndpoint; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_INTERFACE_ASSOCIATION: groups interfaces */ +struct usb_interface_assoc_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bFirstInterface; + __u8 bInterfaceCount; + __u8 bFunctionClass; + __u8 bFunctionSubClass; + __u8 bFunctionProtocol; + __u8 iFunction; +} __attribute__ ((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_SECURITY: group of wireless security descriptors, including + * encryption types available for setting up a CC/association. + */ +struct usb_security_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumEncryptionTypes; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_KEY: used with {GET,SET}_SECURITY_DATA; only public keys + * may be retrieved. + */ +struct usb_key_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 tTKID[3]; + __u8 bReserved; + __u8 bKeyData[0]; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_ENCRYPTION_TYPE: bundled in DT_SECURITY groups */ +struct usb_encryption_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bEncryptionType; +#define USB_ENC_TYPE_UNSECURE 0 +#define USB_ENC_TYPE_WIRED 1 /* non-wireless mode */ +#define USB_ENC_TYPE_CCM_1 2 /* aes128/cbc session */ +#define USB_ENC_TYPE_RSA_1 3 /* rsa3072/sha1 auth */ + __u8 bEncryptionValue; /* use in SET_ENCRYPTION */ + __u8 bAuthKeyIndex; +} __attribute__((packed)); + + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_BOS: group of wireless capabilities */ +struct usb_bos_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __le16 wTotalLength; + __u8 bNumDeviceCaps; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_DEVICE_CAPABILITY: grouped with BOS */ +struct usb_dev_cap_header { + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; +} __attribute__((packed)); + +#define USB_CAP_TYPE_WIRELESS_USB 1 + +struct usb_wireless_cap_descriptor { /* Ultra Wide Band */ + __u8 bLength; + __u8 bDescriptorType; + __u8 bDevCapabilityType; + + __u8 bmAttributes; +#define USB_WIRELESS_P2P_DRD (1 << 1) +#define USB_WIRELESS_BEACON_MASK (3 << 2) +#define USB_WIRELESS_BEACON_SELF (1 << 2) +#define USB_WIRELESS_BEACON_DIRECTED (2 << 2) +#define USB_WIRELESS_BEACON_NONE (3 << 2) + __le16 wPHYRates; /* bit rates, Mbps */ +#define USB_WIRELESS_PHY_53 (1 << 0) /* always set */ +#define USB_WIRELESS_PHY_80 (1 << 1) +#define USB_WIRELESS_PHY_107 (1 << 2) /* always set */ +#define USB_WIRELESS_PHY_160 (1 << 3) +#define USB_WIRELESS_PHY_200 (1 << 4) /* always set */ +#define USB_WIRELESS_PHY_320 (1 << 5) +#define USB_WIRELESS_PHY_400 (1 << 6) +#define USB_WIRELESS_PHY_480 (1 << 7) + __u8 bmTFITXPowerInfo; /* TFI power levels */ + __u8 bmFFITXPowerInfo; /* FFI power levels */ + __le16 bmBandGroup; + __u8 bReserved; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_DT_WIRELESS_ENDPOINT_COMP: companion descriptor associated with + * each endpoint descriptor for a wireless device + */ +struct usb_wireless_ep_comp_descriptor { + __u8 bLength; + __u8 bDescriptorType; + + __u8 bMaxBurst; + __u8 bMaxSequence; + __le16 wMaxStreamDelay; + __le16 wOverTheAirPacketSize; + __u8 bOverTheAirInterval; + __u8 bmCompAttributes; +#define USB_ENDPOINT_SWITCH_MASK 0x03 /* in bmCompAttributes */ +#define USB_ENDPOINT_SWITCH_NO 0 +#define USB_ENDPOINT_SWITCH_SWITCH 1 +#define USB_ENDPOINT_SWITCH_SCALE 2 +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_HANDSHAKE is a four-way handshake used between a wireless + * host and a device for connection set up, mutual authentication, and + * exchanging short lived session keys. The handshake depends on a CC. + */ +struct usb_handshake { + __u8 bMessageNumber; + __u8 bStatus; + __u8 tTKID[3]; + __u8 bReserved; + __u8 CDID[16]; + __u8 nonce[16]; + __u8 MIC[8]; +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB_REQ_SET_CONNECTION modifies or revokes a connection context (CC). + * A CC may also be set up using non-wireless secure channels (including + * wired USB!), and some devices may support CCs with multiple hosts. + */ +struct usb_connection_context { + __u8 CHID[16]; /* persistent host id */ + __u8 CDID[16]; /* device id (unique w/in host context) */ + __u8 CK[16]; /* connection key */ +} __attribute__((packed)); + +/*-------------------------------------------------------------------------*/ + +/* USB 2.0 defines three speeds, here's how Linux identifies them */ + +enum usb_device_speed { + USB_SPEED_UNKNOWN = 0, /* enumerating */ + USB_SPEED_LOW, USB_SPEED_FULL, /* usb 1.1 */ + USB_SPEED_HIGH, /* usb 2.0 */ + USB_SPEED_VARIABLE, /* wireless (usb 2.5) */ +}; + +enum usb_device_state { + /* NOTATTACHED isn't in the USB spec, and this state acts + * the same as ATTACHED ... but it's clearer this way. + */ + USB_STATE_NOTATTACHED = 0, + + /* chapter 9 and authentication (wireless) device states */ + USB_STATE_ATTACHED, + USB_STATE_POWERED, /* wired */ + USB_STATE_UNAUTHENTICATED, /* auth */ + USB_STATE_RECONNECTING, /* auth */ + USB_STATE_DEFAULT, /* limited function */ + USB_STATE_ADDRESS, + USB_STATE_CONFIGURED, /* most functions */ + + USB_STATE_SUSPENDED + + /* NOTE: there are actually four different SUSPENDED + * states, returning to POWERED, DEFAULT, ADDRESS, or + * CONFIGURED respectively when SOF tokens flow again. + */ +}; + +#endif /* __LINUX_USB_CH9_H */ diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h new file mode 100644 index 0000000..275cb5f --- /dev/null +++ b/include/linux/usb/gadget.h @@ -0,0 +1,857 @@ +/* + * <linux/usb/gadget.h> + * + * We call the USB code inside a Linux-based peripheral device a "gadget" + * driver, except for the hardware-specific bus glue. One USB host can + * master many USB gadgets, but the gadgets are only slaved to one host. + * + * + * (C) Copyright 2002-2004 by David Brownell + * All Rights Reserved. + * + * This software is licensed under the GNU GPL version 2. + * + * Ported to U-boot by: Thomas Smits <ts.smits@gmail.com> and + * Remy Bohmer <linux@bohmer.net> + */ + +#ifndef __LINUX_USB_GADGET_H +#define __LINUX_USB_GADGET_H + +#include <linux/list.h> + +struct usb_ep; + +/** + * struct usb_request - describes one i/o request + * @buf: Buffer used for data. Always provide this; some controllers + * only use PIO, or don't use DMA for some endpoints. + * @dma: DMA address corresponding to 'buf'. If you don't set this + * field, and the usb controller needs one, it is responsible + * for mapping and unmapping the buffer. + * @length: Length of that data + * @no_interrupt: If true, hints that no completion irq is needed. + * Helpful sometimes with deep request queues that are handled + * directly by DMA controllers. + * @zero: If true, when writing data, makes the last packet be "short" + * by adding a zero length packet as needed; + * @short_not_ok: When reading data, makes short packets be + * treated as errors (queue stops advancing till cleanup). + * @complete: Function called when request completes, so this request and + * its buffer may be re-used. + * Reads terminate with a short packet, or when the buffer fills, + * whichever comes first. When writes terminate, some data bytes + * will usually still be in flight (often in a hardware fifo). + * Errors (for reads or writes) stop the queue from advancing + * until the completion function returns, so that any transfers + * invalidated by the error may first be dequeued. + * @context: For use by the completion callback + * @list: For use by the gadget driver. + * @status: Reports completion code, zero or a negative errno. + * Normally, faults block the transfer queue from advancing until + * the completion callback returns. + * Code "-ESHUTDOWN" indicates completion caused by device disconnect, + * or when the driver disabled the endpoint. + * @actual: Reports bytes transferred to/from the buffer. For reads (OUT + * transfers) this may be less than the requested length. If the + * short_not_ok flag is set, short reads are treated as errors + * even when status otherwise indicates successful completion. + * Note that for writes (IN transfers) some data bytes may still + * reside in a device-side FIFO when the request is reported as + * complete. + * + * These are allocated/freed through the endpoint they're used with. The + * hardware's driver can add extra per-request data to the memory it returns, + * which often avoids separate memory allocations (potential failures), + * later when the request is queued. + * + * Request flags affect request handling, such as whether a zero length + * packet is written (the "zero" flag), whether a short read should be + * treated as an error (blocking request queue advance, the "short_not_ok" + * flag), or hinting that an interrupt is not required (the "no_interrupt" + * flag, for use with deep request queues). + * + * Bulk endpoints can use any size buffers, and can also be used for interrupt + * transfers. interrupt-only endpoints can be much less functional. + * + * NOTE: this is analagous to 'struct urb' on the host side, except that + * it's thinner and promotes more pre-allocation. + */ + +struct usb_request { + void *buf; + unsigned length; + dma_addr_t dma; + + unsigned no_interrupt:1; + unsigned zero:1; + unsigned short_not_ok:1; + + void (*complete)(struct usb_ep *ep, + struct usb_request *req); + void *context; + struct list_head list; + + int status; + unsigned actual; +}; + +/*-------------------------------------------------------------------------*/ + +/* endpoint-specific parts of the api to the usb controller hardware. + * unlike the urb model, (de)multiplexing layers are not required. + * (so this api could slash overhead if used on the host side...) + * + * note that device side usb controllers commonly differ in how many + * endpoints they support, as well as their capabilities. + */ +struct usb_ep_ops { + int (*enable) (struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc); + int (*disable) (struct usb_ep *ep); + + struct usb_request *(*alloc_request) (struct usb_ep *ep, + gfp_t gfp_flags); + void (*free_request) (struct usb_ep *ep, struct usb_request *req); + + int (*queue) (struct usb_ep *ep, struct usb_request *req, + gfp_t gfp_flags); + int (*dequeue) (struct usb_ep *ep, struct usb_request *req); + + int (*set_halt) (struct usb_ep *ep, int value); + int (*fifo_status) (struct usb_ep *ep); + void (*fifo_flush) (struct usb_ep *ep); +}; + +/** + * struct usb_ep - device side representation of USB endpoint + * @name:identifier for the endpoint, such as "ep-a" or "ep9in-bulk" + * @ops: Function pointers used to access hardware-specific operations. + * @ep_list:the gadget's ep_list holds all of its endpoints + * @maxpacket:The maximum packet size used on this endpoint. The initial + * value can sometimes be reduced (hardware allowing), according to + * the endpoint descriptor used to configure the endpoint. + * @driver_data:for use by the gadget driver. all other fields are + * read-only to gadget drivers. + * + * the bus controller driver lists all the general purpose endpoints in + * gadget->ep_list. the control endpoint (gadget->ep0) is not in that list, + * and is accessed only in response to a driver setup() callback. + */ +struct usb_ep { + void *driver_data; + const char *name; + const struct usb_ep_ops *ops; + struct list_head ep_list; + unsigned maxpacket:16; +}; + +/*-------------------------------------------------------------------------*/ + +/** + * usb_ep_enable - configure endpoint, making it usable + * @ep:the endpoint being configured. may not be the endpoint named "ep0". + * drivers discover endpoints through the ep_list of a usb_gadget. + * @desc:descriptor for desired behavior. caller guarantees this pointer + * remains valid until the endpoint is disabled; the data byte order + * is little-endian (usb-standard). + * + * when configurations are set, or when interface settings change, the driver + * will enable or disable the relevant endpoints. while it is enabled, an + * endpoint may be used for i/o until the driver receives a disconnect() from + * the host or until the endpoint is disabled. + * + * the ep0 implementation (which calls this routine) must ensure that the + * hardware capabilities of each endpoint match the descriptor provided + * for it. for example, an endpoint named "ep2in-bulk" would be usable + * for interrupt transfers as well as bulk, but it likely couldn't be used + * for iso transfers or for endpoint 14. some endpoints are fully + * configurable, with more generic names like "ep-a". (remember that for + * USB, "in" means "towards the USB master".) + * + * returns zero, or a negative error code. + */ +static inline int usb_ep_enable(struct usb_ep *ep, + const struct usb_endpoint_descriptor *desc) +{ + return ep->ops->enable(ep, desc); +} + +/** + * usb_ep_disable - endpoint is no longer usable + * @ep:the endpoint being unconfigured. may not be the endpoint named "ep0". + * + * no other task may be using this endpoint when this is called. + * any pending and uncompleted requests will complete with status + * indicating disconnect (-ESHUTDOWN) before this call returns. + * gadget drivers must call usb_ep_enable() again before queueing + * requests to the endpoint. + * + * returns zero, or a negative error code. + */ +static inline int usb_ep_disable(struct usb_ep *ep) +{ + return ep->ops->disable(ep); +} + +/** + * usb_ep_alloc_request - allocate a request object to use with this endpoint + * @ep:the endpoint to be used with with the request + * @gfp_flags:GFP_* flags to use + * + * Request objects must be allocated with this call, since they normally + * need controller-specific setup and may even need endpoint-specific + * resources such as allocation of DMA descriptors. + * Requests may be submitted with usb_ep_queue(), and receive a single + * completion callback. Free requests with usb_ep_free_request(), when + * they are no longer needed. + * + * Returns the request, or null if one could not be allocated. + */ +static inline struct usb_request *usb_ep_alloc_request(struct usb_ep *ep, + gfp_t gfp_flags) +{ + return ep->ops->alloc_request(ep, gfp_flags); +} + +/** + * usb_ep_free_request - frees a request object + * @ep:the endpoint associated with the request + * @req:the request being freed + * + * Reverses the effect of usb_ep_alloc_request(). + * Caller guarantees the request is not queued, and that it will + * no longer be requeued (or otherwise used). + */ +static inline void usb_ep_free_request(struct usb_ep *ep, + struct usb_request *req) +{ + ep->ops->free_request(ep, req); +} + +/** + * usb_ep_queue - queues (submits) an I/O request to an endpoint. + * @ep:the endpoint associated with the request + * @req:the request being submitted + * @gfp_flags: GFP_* flags to use in case the lower level driver couldn't + * pre-allocate all necessary memory with the request. + * + * This tells the device controller to perform the specified request through + * that endpoint (reading or writing a buffer). When the request completes, + * including being canceled by usb_ep_dequeue(), the request's completion + * routine is called to return the request to the driver. Any endpoint + * (except control endpoints like ep0) may have more than one transfer + * request queued; they complete in FIFO order. Once a gadget driver + * submits a request, that request may not be examined or modified until it + * is given back to that driver through the completion callback. + * + * Each request is turned into one or more packets. The controller driver + * never merges adjacent requests into the same packet. OUT transfers + * will sometimes use data that's already buffered in the hardware. + * Drivers can rely on the fact that the first byte of the request's buffer + * always corresponds to the first byte of some USB packet, for both + * IN and OUT transfers. + * + * Bulk endpoints can queue any amount of data; the transfer is packetized + * automatically. The last packet will be short if the request doesn't fill it + * out completely. Zero length packets (ZLPs) should be avoided in portable + * protocols since not all usb hardware can successfully handle zero length + * packets. (ZLPs may be explicitly written, and may be implicitly written if + * the request 'zero' flag is set.) Bulk endpoints may also be used + * for interrupt transfers; but the reverse is not true, and some endpoints + * won't support every interrupt transfer. (Such as 768 byte packets.) + * + * Interrupt-only endpoints are less functional than bulk endpoints, for + * example by not supporting queueing or not handling buffers that are + * larger than the endpoint's maxpacket size. They may also treat data + * toggle differently. + * + * Control endpoints ... after getting a setup() callback, the driver queues + * one response (even if it would be zero length). That enables the + * status ack, after transfering data as specified in the response. Setup + * functions may return negative error codes to generate protocol stalls. + * (Note that some USB device controllers disallow protocol stall responses + * in some cases.) When control responses are deferred (the response is + * written after the setup callback returns), then usb_ep_set_halt() may be + * used on ep0 to trigger protocol stalls. + * + * For periodic endpoints, like interrupt or isochronous ones, the usb host + * arranges to poll once per interval, and the gadget driver usually will + * have queued some data to transfer at that time. + * + * Returns zero, or a negative error code. Endpoints that are not enabled + * report errors; errors will also be + * reported when the usb peripheral is disconnected. + */ +static inline int usb_ep_queue(struct usb_ep *ep, + struct usb_request *req, gfp_t gfp_flags) +{ + return ep->ops->queue(ep, req, gfp_flags); +} + +/** + * usb_ep_dequeue - dequeues (cancels, unlinks) an I/O request from an endpoint + * @ep:the endpoint associated with the request + * @req:the request being canceled + * + * if the request is still active on the endpoint, it is dequeued and its + * completion routine is called (with status -ECONNRESET); else a negative + * error code is returned. + * + * note that some hardware can't clear out write fifos (to unlink the request + * at the head of the queue) except as part of disconnecting from usb. such + * restrictions prevent drivers from supporting configuration changes, + * even to configuration zero (a "chapter 9" requirement). + */ +static inline int usb_ep_dequeue(struct usb_ep *ep, struct usb_request *req) +{ + return ep->ops->dequeue(ep, req); +} + +/** + * usb_ep_set_halt - sets the endpoint halt feature. + * @ep: the non-isochronous endpoint being stalled + * + * Use this to stall an endpoint, perhaps as an error report. + * Except for control endpoints, + * the endpoint stays halted (will not stream any data) until the host + * clears this feature; drivers may need to empty the endpoint's request + * queue first, to make sure no inappropriate transfers happen. + * + * Note that while an endpoint CLEAR_FEATURE will be invisible to the + * gadget driver, a SET_INTERFACE will not be. To reset endpoints for the + * current altsetting, see usb_ep_clear_halt(). When switching altsettings, + * it's simplest to use usb_ep_enable() or usb_ep_disable() for the endpoints. + * + * Returns zero, or a negative error code. On success, this call sets + * underlying hardware state that blocks data transfers. + * Attempts to halt IN endpoints will fail (returning -EAGAIN) if any + * transfer requests are still queued, or if the controller hardware + * (usually a FIFO) still holds bytes that the host hasn't collected. + */ +static inline int usb_ep_set_halt(struct usb_ep *ep) +{ + return ep->ops->set_halt(ep, 1); +} + +/** + * usb_ep_clear_halt - clears endpoint halt, and resets toggle + * @ep:the bulk or interrupt endpoint being reset + * + * Use this when responding to the standard usb "set interface" request, + * for endpoints that aren't reconfigured, after clearing any other state + * in the endpoint's i/o queue. + * + * Returns zero, or a negative error code. On success, this call clears + * the underlying hardware state reflecting endpoint halt and data toggle. + * Note that some hardware can't support this request (like pxa2xx_udc), + * and accordingly can't correctly implement interface altsettings. + */ +static inline int usb_ep_clear_halt(struct usb_ep *ep) +{ + return ep->ops->set_halt(ep, 0); +} + +/** + * usb_ep_fifo_status - returns number of bytes in fifo, or error + * @ep: the endpoint whose fifo status is being checked. + * + * FIFO endpoints may have "unclaimed data" in them in certain cases, + * such as after aborted transfers. Hosts may not have collected all + * the IN data written by the gadget driver (and reported by a request + * completion). The gadget driver may not have collected all the data + * written OUT to it by the host. Drivers that need precise handling for + * fault reporting or recovery may need to use this call. + * + * This returns the number of such bytes in the fifo, or a negative + * errno if the endpoint doesn't use a FIFO or doesn't support such + * precise handling. + */ +static inline int usb_ep_fifo_status(struct usb_ep *ep) +{ + if (ep->ops->fifo_status) + return ep->ops->fifo_status(ep); + else + return -EOPNOTSUPP; +} + +/** + * usb_ep_fifo_flush - flushes contents of a fifo + * @ep: the endpoint whose fifo is being flushed. + * + * This call may be used to flush the "unclaimed data" that may exist in + * an endpoint fifo after abnormal transaction terminations. The call + * must never be used except when endpoint is not being used for any + * protocol translation. + */ +static inline void usb_ep_fifo_flush(struct usb_ep *ep) +{ + if (ep->ops->fifo_flush) + ep->ops->fifo_flush(ep); +} + + +/*-------------------------------------------------------------------------*/ + +struct usb_gadget; + +/* the rest of the api to the controller hardware: device operations, + * which don't involve endpoints (or i/o). + */ +struct usb_gadget_ops { + int (*get_frame)(struct usb_gadget *); + int (*wakeup)(struct usb_gadget *); + int (*set_selfpowered) (struct usb_gadget *, int is_selfpowered); + int (*vbus_session) (struct usb_gadget *, int is_active); + int (*vbus_draw) (struct usb_gadget *, unsigned mA); + int (*pullup) (struct usb_gadget *, int is_on); + int (*ioctl)(struct usb_gadget *, + unsigned code, unsigned long param); +}; + +struct device { + void *driver_data; /* data private to the driver */ +}; + +/** + * struct usb_gadget - represents a usb slave device + * @ops: Function pointers used to access hardware-specific operations. + * @ep0: Endpoint zero, used when reading or writing responses to + * driver setup() requests + * @ep_list: List of other endpoints supported by the device. + * @speed: Speed of current connection to USB host. + * @is_dualspeed: True if the controller supports both high and full speed + * operation. If it does, the gadget driver must also support both. + * @is_otg: True if the USB device port uses a Mini-AB jack, so that the + * gadget driver must provide a USB OTG descriptor. + * @is_a_peripheral: False unless is_otg, the "A" end of a USB cable + * is in the Mini-AB jack, and HNP has been used to switch roles + * so that the "A" device currently acts as A-Peripheral, not A-Host. + * @a_hnp_support: OTG device feature flag, indicating that the A-Host + * supports HNP at this port. + * @a_alt_hnp_support: OTG device feature flag, indicating that the A-Host + * only supports HNP on a different root port. + * @b_hnp_enable: OTG device feature flag, indicating that the A-Host + * enabled HNP support. + * @name: Identifies the controller hardware type. Used in diagnostics + * and sometimes configuration. + * @dev: Driver model state for this abstract device. + * + * Gadgets have a mostly-portable "gadget driver" implementing device + * functions, handling all usb configurations and interfaces. Gadget + * drivers talk to hardware-specific code indirectly, through ops vectors. + * That insulates the gadget driver from hardware details, and packages + * the hardware endpoints through generic i/o queues. The "usb_gadget" + * and "usb_ep" interfaces provide that insulation from the hardware. + * + * Except for the driver data, all fields in this structure are + * read-only to the gadget driver. That driver data is part of the + * "driver model" infrastructure in 2.6 (and later) kernels, and for + * earlier systems is grouped in a similar structure that's not known + * to the rest of the kernel. + * + * Values of the three OTG device feature flags are updated before the + * setup() call corresponding to USB_REQ_SET_CONFIGURATION, and before + * driver suspend() calls. They are valid only when is_otg, and when the + * device is acting as a B-Peripheral (so is_a_peripheral is false). + */ +struct usb_gadget { + /* readonly to gadget driver */ + const struct usb_gadget_ops *ops; + struct usb_ep *ep0; + struct list_head ep_list; /* of usb_ep */ + enum usb_device_speed speed; + unsigned is_dualspeed:1; + unsigned is_otg:1; + unsigned is_a_peripheral:1; + unsigned b_hnp_enable:1; + unsigned a_hnp_support:1; + unsigned a_alt_hnp_support:1; + const char *name; + struct device dev; +}; + +static inline void set_gadget_data(struct usb_gadget *gadget, void *data) +{ + gadget->dev.driver_data = data; +} + +static inline void *get_gadget_data(struct usb_gadget *gadget) +{ + return gadget->dev.driver_data; +} + +/* iterates the non-control endpoints; 'tmp' is a struct usb_ep pointer */ +#define gadget_for_each_ep(tmp, gadget) \ + list_for_each_entry(tmp, &(gadget)->ep_list, ep_list) + + +/** + * gadget_is_dualspeed - return true iff the hardware handles high speed + * @g: controller that might support both high and full speeds + */ +static inline int gadget_is_dualspeed(struct usb_gadget *g) +{ +#ifdef CONFIG_USB_GADGET_DUALSPEED + /* runtime test would check "g->is_dualspeed" ... that might be + * useful to work around hardware bugs, but is mostly pointless + */ + return 1; +#else + return 0; +#endif +} + +/** + * gadget_is_otg - return true iff the hardware is OTG-ready + * @g: controller that might have a Mini-AB connector + * + * This is a runtime test, since kernels with a USB-OTG stack sometimes + * run on boards which only have a Mini-B (or Mini-A) connector. + */ +static inline int gadget_is_otg(struct usb_gadget *g) +{ +#ifdef CONFIG_USB_OTG + return g->is_otg; +#else + return 0; +#endif +} + +/** + * usb_gadget_frame_number - returns the current frame number + * @gadget: controller that reports the frame number + * + * Returns the usb frame number, normally eleven bits from a SOF packet, + * or negative errno if this device doesn't support this capability. + */ +static inline int usb_gadget_frame_number(struct usb_gadget *gadget) +{ + return gadget->ops->get_frame(gadget); +} + +/** + * usb_gadget_wakeup - tries to wake up the host connected to this gadget + * @gadget: controller used to wake up the host + * + * Returns zero on success, else negative error code if the hardware + * doesn't support such attempts, or its support has not been enabled + * by the usb host. Drivers must return device descriptors that report + * their ability to support this, or hosts won't enable it. + * + * This may also try to use SRP to wake the host and start enumeration, + * even if OTG isn't otherwise in use. OTG devices may also start + * remote wakeup even when hosts don't explicitly enable it. + */ +static inline int usb_gadget_wakeup(struct usb_gadget *gadget) +{ + if (!gadget->ops->wakeup) + return -EOPNOTSUPP; + return gadget->ops->wakeup(gadget); +} + +/** + * usb_gadget_set_selfpowered - sets the device selfpowered feature. + * @gadget:the device being declared as self-powered + * + * this affects the device status reported by the hardware driver + * to reflect that it now has a local power supply. + * + * returns zero on success, else negative errno. + */ +static inline int usb_gadget_set_selfpowered(struct usb_gadget *gadget) +{ + if (!gadget->ops->set_selfpowered) + return -EOPNOTSUPP; + return gadget->ops->set_selfpowered(gadget, 1); +} + +/** + * usb_gadget_clear_selfpowered - clear the device selfpowered feature. + * @gadget:the device being declared as bus-powered + * + * this affects the device status reported by the hardware driver. + * some hardware may not support bus-powered operation, in which + * case this feature's value can never change. + * + * returns zero on success, else negative errno. + */ +static inline int usb_gadget_clear_selfpowered(struct usb_gadget *gadget) +{ + if (!gadget->ops->set_selfpowered) + return -EOPNOTSUPP; + return gadget->ops->set_selfpowered(gadget, 0); +} + +/** + * usb_gadget_vbus_connect - Notify controller that VBUS is powered + * @gadget:The device which now has VBUS power. + * + * This call is used by a driver for an external transceiver (or GPIO) + * that detects a VBUS power session starting. Common responses include + * resuming the controller, activating the D+ (or D-) pullup to let the + * host detect that a USB device is attached, and starting to draw power + * (8mA or possibly more, especially after SET_CONFIGURATION). + * + * Returns zero on success, else negative errno. + */ +static inline int usb_gadget_vbus_connect(struct usb_gadget *gadget) +{ + if (!gadget->ops->vbus_session) + return -EOPNOTSUPP; + return gadget->ops->vbus_session(gadget, 1); +} + +/** + * usb_gadget_vbus_draw - constrain controller's VBUS power usage + * @gadget:The device whose VBUS usage is being described + * @mA:How much current to draw, in milliAmperes. This should be twice + * the value listed in the configuration descriptor bMaxPower field. + * + * This call is used by gadget drivers during SET_CONFIGURATION calls, + * reporting how much power the device may consume. For example, this + * could affect how quickly batteries are recharged. + * + * Returns zero on success, else negative errno. + */ +static inline int usb_gadget_vbus_draw(struct usb_gadget *gadget, unsigned mA) +{ + if (!gadget->ops->vbus_draw) + return -EOPNOTSUPP; + return gadget->ops->vbus_draw(gadget, mA); +} + +/** + * usb_gadget_vbus_disconnect - notify controller about VBUS session end + * @gadget:the device whose VBUS supply is being described + * + * This call is used by a driver for an external transceiver (or GPIO) + * that detects a VBUS power session ending. Common responses include + * reversing everything done in usb_gadget_vbus_connect(). + * + * Returns zero on success, else negative errno. + */ +static inline int usb_gadget_vbus_disconnect(struct usb_gadget *gadget) +{ + if (!gadget->ops->vbus_session) + return -EOPNOTSUPP; + return gadget->ops->vbus_session(gadget, 0); +} + +/** + * usb_gadget_connect - software-controlled connect to USB host + * @gadget:the peripheral being connected + * + * Enables the D+ (or potentially D-) pullup. The host will start + * enumerating this gadget when the pullup is active and a VBUS session + * is active (the link is powered). This pullup is always enabled unless + * usb_gadget_disconnect() has been used to disable it. + * + * Returns zero on success, else negative errno. + */ +static inline int usb_gadget_connect(struct usb_gadget *gadget) +{ + if (!gadget->ops->pullup) + return -EOPNOTSUPP; + return gadget->ops->pullup(gadget, 1); +} + +/** + * usb_gadget_disconnect - software-controlled disconnect from USB host + * @gadget:the peripheral being disconnected + * + * Disables the D+ (or potentially D-) pullup, which the host may see + * as a disconnect (when a VBUS session is active). Not all systems + * support software pullup controls. + * + * This routine may be used during the gadget driver bind() call to prevent + * the peripheral from ever being visible to the USB host, unless later + * usb_gadget_connect() is called. For example, user mode components may + * need to be activated before the system can talk to hosts. + * + * Returns zero on success, else negative errno. + */ +static inline int usb_gadget_disconnect(struct usb_gadget *gadget) +{ + if (!gadget->ops->pullup) + return -EOPNOTSUPP; + return gadget->ops->pullup(gadget, 0); +} + + +/*-------------------------------------------------------------------------*/ + +/** + * struct usb_gadget_driver - driver for usb 'slave' devices + * @speed: Highest speed the driver handles. + * @bind: Invoked when the driver is bound to a gadget, usually + * after registering the driver. + * At that point, ep0 is fully initialized, and ep_list holds + * the currently-available endpoints. + * Called in a context that permits sleeping. + * @setup: Invoked for ep0 control requests that aren't handled by + * the hardware level driver. Most calls must be handled by + * the gadget driver, including descriptor and configuration + * management. The 16 bit members of the setup data are in + * USB byte order. Called in_interrupt; this may not sleep. Driver + * queues a response to ep0, or returns negative to stall. + * @disconnect: Invoked after all transfers have been stopped, + * when the host is disconnected. May be called in_interrupt; this + * may not sleep. Some devices can't detect disconnect, so this might + * not be called except as part of controller shutdown. + * @unbind: Invoked when the driver is unbound from a gadget, + * usually from rmmod (after a disconnect is reported). + * Called in a context that permits sleeping. + * @suspend: Invoked on USB suspend. May be called in_interrupt. + * @resume: Invoked on USB resume. May be called in_interrupt. + * + * Devices are disabled till a gadget driver successfully bind()s, which + * means the driver will handle setup() requests needed to enumerate (and + * meet "chapter 9" requirements) then do some useful work. + * + * If gadget->is_otg is true, the gadget driver must provide an OTG + * descriptor during enumeration, or else fail the bind() call. In such + * cases, no USB traffic may flow until both bind() returns without + * having called usb_gadget_disconnect(), and the USB host stack has + * initialized. + * + * Drivers use hardware-specific knowledge to configure the usb hardware. + * endpoint addressing is only one of several hardware characteristics that + * are in descriptors the ep0 implementation returns from setup() calls. + * + * Except for ep0 implementation, most driver code shouldn't need change to + * run on top of different usb controllers. It'll use endpoints set up by + * that ep0 implementation. + * + * The usb controller driver handles a few standard usb requests. Those + * include set_address, and feature flags for devices, interfaces, and + * endpoints (the get_status, set_feature, and clear_feature requests). + * + * Accordingly, the driver's setup() callback must always implement all + * get_descriptor requests, returning at least a device descriptor and + * a configuration descriptor. Drivers must make sure the endpoint + * descriptors match any hardware constraints. Some hardware also constrains + * other descriptors. (The pxa250 allows only configurations 1, 2, or 3). + * + * The driver's setup() callback must also implement set_configuration, + * and should also implement set_interface, get_configuration, and + * get_interface. Setting a configuration (or interface) is where + * endpoints should be activated or (config 0) shut down. + * + * (Note that only the default control endpoint is supported. Neither + * hosts nor devices generally support control traffic except to ep0.) + * + * Most devices will ignore USB suspend/resume operations, and so will + * not provide those callbacks. However, some may need to change modes + * when the host is not longer directing those activities. For example, + * local controls (buttons, dials, etc) may need to be re-enabled since + * the (remote) host can't do that any longer; or an error state might + * be cleared, to make the device behave identically whether or not + * power is maintained. + */ +struct usb_gadget_driver { + enum usb_device_speed speed; + int (*bind)(struct usb_gadget *); + void (*unbind)(struct usb_gadget *); + int (*setup)(struct usb_gadget *, + const struct usb_ctrlrequest *); + void (*disconnect)(struct usb_gadget *); + void (*suspend)(struct usb_gadget *); + void (*resume)(struct usb_gadget *); +}; + + +/*-------------------------------------------------------------------------*/ + +/* driver modules register and unregister, as usual. + * these calls must be made in a context that can sleep. + * + * these will usually be implemented directly by the hardware-dependent + * usb bus interface driver, which will only support a single driver. + */ + +/** + * usb_gadget_register_driver - register a gadget driver + * @driver:the driver being registered + * + * Call this in your gadget driver's module initialization function, + * to tell the underlying usb controller driver about your driver. + * The driver's bind() function will be called to bind it to a + * gadget before this registration call returns. It's expected that + * the bind() functions will be in init sections. + * This function must be called in a context that can sleep. + */ +int usb_gadget_register_driver(struct usb_gadget_driver *driver); + +/** + * usb_gadget_unregister_driver - unregister a gadget driver + * @driver:the driver being unregistered + * + * Call this in your gadget driver's module cleanup function, + * to tell the underlying usb controller that your driver is + * going away. If the controller is connected to a USB host, + * it will first disconnect(). The driver is also requested + * to unbind() and clean up any device state, before this procedure + * finally returns. It's expected that the unbind() functions + * will in in exit sections, so may not be linked in some kernels. + * This function must be called in a context that can sleep. + */ +int usb_gadget_unregister_driver(struct usb_gadget_driver *driver); + +/*-------------------------------------------------------------------------*/ + +/* utility to simplify dealing with string descriptors */ + +/** + * struct usb_string - wraps a C string and its USB id + * @id:the (nonzero) ID for this string + * @s:the string, in UTF-8 encoding + * + * If you're using usb_gadget_get_string(), use this to wrap a string + * together with its ID. + */ +struct usb_string { + u8 id; + const char *s; +}; + +/** + * struct usb_gadget_strings - a set of USB strings in a given language + * @language:identifies the strings' language (0x0409 for en-us) + * @strings:array of strings with their ids + * + * If you're using usb_gadget_get_string(), use this to wrap all the + * strings for a given language. + */ +struct usb_gadget_strings { + u16 language; /* 0x0409 for en-us */ + struct usb_string *strings; +}; + +/* put descriptor for string with that id into buf (buflen >= 256) */ +int usb_gadget_get_string(struct usb_gadget_strings *table, int id, u8 *buf); + +/*-------------------------------------------------------------------------*/ + +/* utility to simplify managing config descriptors */ + +/* write vector of descriptors into buffer */ +int usb_descriptor_fillbuf(void *, unsigned, + const struct usb_descriptor_header **); + +/* build config descriptor from single descriptor vector */ +int usb_gadget_config_buf(const struct usb_config_descriptor *config, + void *buf, unsigned buflen, const struct usb_descriptor_header **desc); + +/*-------------------------------------------------------------------------*/ + +/* utility wrapping a simple endpoint selection policy */ + +extern struct usb_ep *usb_ep_autoconfig(struct usb_gadget *, + struct usb_endpoint_descriptor *); + +extern void usb_ep_autoconfig_reset(struct usb_gadget *); + +extern int usb_gadget_handle_interrupts(void); + +#endif /* __LINUX_USB_GADGET_H */ diff --git a/include/mpc83xx.h b/include/mpc83xx.h index ba6cdf1..07e0e0b 100644 --- a/include/mpc83xx.h +++ b/include/mpc83xx.h @@ -319,6 +319,54 @@ #define SICRH_GPIO2_H 0x00000030 #define SICRH_SPI 0x00000003 #define SICRH_SPI_SD 0x00000001 + +#elif defined(CONFIG_MPC8308) +/* SICRL bits - MPC8308 specific */ +#define SICRL_SPI_PF0 (0 << 28) +#define SICRL_SPI_PF1 (1 << 28) +#define SICRL_SPI_PF3 (3 << 28) +#define SICRL_UART_PF0 (0 << 26) +#define SICRL_UART_PF1 (1 << 26) +#define SICRL_UART_PF3 (3 << 26) +#define SICRL_IRQ_PF0 (0 << 24) +#define SICRL_IRQ_PF1 (1 << 24) +#define SICRL_I2C2_PF0 (0 << 20) +#define SICRL_I2C2_PF1 (1 << 20) +#define SICRL_ETSEC1_TX_CLK (0 << 6) +#define SICRL_ETSEC1_GTX_CLK125 (1 << 6) + +/* SICRH bits - MPC8308 specific */ +#define SICRH_ESDHC_A_SD (0 << 30) +#define SICRH_ESDHC_A_GTM (1 << 30) +#define SICRH_ESDHC_A_GPIO (3 << 30) +#define SICRH_ESDHC_B_SD (0 << 28) +#define SICRH_ESDHC_B_GTM (1 << 28) +#define SICRH_ESDHC_B_GPIO (3 << 28) +#define SICRH_ESDHC_C_SD (0 << 26) +#define SICRH_ESDHC_C_GTM (1 << 26) +#define SICRH_ESDHC_C_GPIO (3 << 26) +#define SICRH_GPIO_A_GPIO (0 << 24) +#define SICRH_GPIO_A_TSEC2 (1 << 24) +#define SICRH_GPIO_B_GPIO (0 << 22) +#define SICRH_GPIO_B_TSEC2_TX_CLK (1 << 22) +#define SICRH_GPIO_B_TSEC2_GTX_CLK125 (2 << 22) +#define SICRH_IEEE1588_A_TMR (1 << 20) +#define SICRH_IEEE1588_A_GPIO (3 << 20) +#define SICRH_USB (1 << 18) +#define SICRH_GTM_GTM (1 << 16) +#define SICRH_GTM_GPIO (3 << 16) +#define SICRH_IEEE1588_B_TMR (1 << 14) +#define SICRH_IEEE1588_B_GPIO (3 << 14) +#define SICRH_ETSEC2_CRS (1 << 12) +#define SICRH_ETSEC2_GPIO (3 << 12) +#define SICRH_GPIOSEL_0 (0 << 8) +#define SICRH_GPIOSEL_1 (1 << 8) +#define SICRH_TMROBI_V3P3 (0 << 4) +#define SICRH_TMROBI_V2P5 (1 << 4) +#define SICRH_TSOBI1_V3P3 (0 << 1) +#define SICRH_TSOBI1_V2P5 (1 << 1) +#define SICRH_TSOBI2_V3P3 (0 << 0) +#define SICRH_TSOBI2_V2P5 (1 << 0) #endif /* SWCRR - System Watchdog Control Register @@ -1216,9 +1264,9 @@ #ifndef __ASSEMBLY__ struct pci_region; -void mpc83xx_pci_init(int num_buses, struct pci_region **reg, int warmboot); +void mpc83xx_pci_init(int num_buses, struct pci_region **reg); void mpc83xx_pcislave_unlock(int bus); -void mpc83xx_pcie_init(int num_buses, struct pci_region **reg, int warmboot); +void mpc83xx_pcie_init(int num_buses, struct pci_region **reg); #endif #endif /* __MPC83XX_H__ */ diff --git a/include/mtd/cfi_flash.h b/include/mtd/cfi_flash.h index 2aa6911..2ff00f2 100644 --- a/include/mtd/cfi_flash.h +++ b/include/mtd/cfi_flash.h @@ -151,6 +151,24 @@ struct cfi_pri_hdr { u8 minor_version; } __attribute__((packed)); +#ifndef CONFIG_SYS_FLASH_BANKS_LIST +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#endif + +/* + * CFI_MAX_FLASH_BANKS only used for flash_info struct declaration. + * + * Use CONFIG_SYS_MAX_FLASH_BANKS_DETECT if defined + */ +#if defined(CONFIG_SYS_MAX_FLASH_BANKS_DETECT) +#define CONFIG_SYS_MAX_FLASH_BANKS (cfi_flash_num_flash_banks) +#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS_DETECT +/* board code can update this variable before CFI detection */ +extern int cfi_flash_num_flash_banks; +#else +#define CFI_MAX_FLASH_BANKS CONFIG_SYS_MAX_FLASH_BANKS +#endif + void flash_write_cmd(flash_info_t * info, flash_sect_t sect, uint offset, u32 cmd); diff --git a/include/net.h b/include/net.h index ab571eb..a29dafc 100644 --- a/include/net.h +++ b/include/net.h @@ -125,8 +125,10 @@ extern int eth_getenv_enetaddr(char *name, uchar *enetaddr); extern int eth_setenv_enetaddr(char *name, const uchar *enetaddr); extern int eth_getenv_enetaddr_by_index(int index, uchar *enetaddr); +extern int usb_eth_initialize(bd_t *bi); extern int eth_init(bd_t *bis); /* Initialize the device */ extern int eth_send(volatile void *packet, int length); /* Send a packet */ + #ifdef CONFIG_API extern int eth_receive(volatile void *packet, int length); /* Receive a packet*/ #endif @@ -481,7 +483,18 @@ static inline int is_multicast_ether_addr(const u8 *addr) return (0x01 & addr[0]); } -/** +/* + * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast + * @addr: Pointer to a six-byte array containing the Ethernet address + * + * Return true if the address is the broadcast address. + */ +static inline int is_broadcast_ether_addr(const u8 *addr) +{ + return (addr[0] & addr[1] & addr[2] & addr[3] & addr[4] & addr[5]) == 0xff; +} + +/* * is_valid_ether_addr - Determine if the given Ethernet address is valid * @addr: Pointer to a six-byte array containing the Ethernet address * @@ -490,7 +503,7 @@ static inline int is_multicast_ether_addr(const u8 *addr) * * Return true if the address is valid. */ -static inline int is_valid_ether_addr(const u8 * addr) +static inline int is_valid_ether_addr(const u8 *addr) { /* FF:FF:FF:FF:FF:FF is a multicast address so we don't need to * explicitly check for it here. */ diff --git a/include/ppc405.h b/include/ppc405.h deleted file mode 100644 index bc2d051..0000000 --- a/include/ppc405.h +++ /dev/null @@ -1,832 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - -#ifndef __PPC405_H__ -#define __PPC405_H__ - -/* Define bits and masks for real-mode storage attribute control registers */ -#define PPC_128MB_SACR_BIT(addr) ((addr) >> 27) -#define PPC_128MB_SACR_VALUE(addr) PPC_REG_VAL(PPC_128MB_SACR_BIT(addr),1) - -#ifndef CONFIG_IOP480 -#define CONFIG_SYS_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ -#else -#define CONFIG_SYS_DCACHE_SIZE (2 << 10) /* For PLX IOP480(403)*/ -#endif - -/****************************************************************************** - * Special for PPC405GP - ******************************************************************************/ - -/****************************************************************************** - * DMA - ******************************************************************************/ -#define DMA_DCR_BASE 0x100 -#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define DMADA0 (DMA_DCR_BASE+0x02) /* DMA destination address register 0 */ -#define DMASA0 (DMA_DCR_BASE+0x03) /* DMA source address register 0 */ -#define DMASB0 (DMA_DCR_BASE+0x04) /* DMA scatter/gather descriptor addr 0 */ -#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define DMADA1 (DMA_DCR_BASE+0x0a) /* DMA destination address register 1 */ -#define DMASA1 (DMA_DCR_BASE+0x0b) /* DMA source address register 1 */ -#define DMASB1 (DMA_DCR_BASE+0x0c) /* DMA scatter/gather descriptor addr 1 */ -#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define DMADA2 (DMA_DCR_BASE+0x12) /* DMA destination address register 2 */ -#define DMASA2 (DMA_DCR_BASE+0x13) /* DMA source address register 2 */ -#define DMASB2 (DMA_DCR_BASE+0x14) /* DMA scatter/gather descriptor addr 2 */ -#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 3 */ -#define DMACT3 (DMA_DCR_BASE+0x19) /* DMA count register 3 */ -#define DMADA3 (DMA_DCR_BASE+0x1a) /* DMA destination address register 3 */ -#define DMASA3 (DMA_DCR_BASE+0x1b) /* DMA source address register 3 */ -#define DMASB3 (DMA_DCR_BASE+0x1c) /* DMA scatter/gather descriptor addr 3 */ -#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ -#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ -#define DMAADR (DMA_DCR_BASE+0x24) /* DMA address decode register */ - -#ifndef CONFIG_405EP -/****************************************************************************** - * Decompression Controller - ******************************************************************************/ -#define DECOMP_DCR_BASE 0x14 -#define KIAR (DECOMP_DCR_BASE+0x0) /* Decompression controller addr reg */ -#define KIDR (DECOMP_DCR_BASE+0x1) /* Decompression controller data reg */ -/* values for kiar register - indirect addressing of these regs */ -#define KCONF 0x40 /* decompression core config register */ -#endif - -/****************************************************************************** - * Power Management - ******************************************************************************/ -#ifdef CONFIG_405EX -#define POWERMAN_DCR_BASE 0xb0 -#else -#define POWERMAN_DCR_BASE 0xb8 -#endif -#define CPMSR (POWERMAN_DCR_BASE+0x0) /* Power management status */ -#define CPMER (POWERMAN_DCR_BASE+0x1) /* Power management enable */ -#define CPMFR (POWERMAN_DCR_BASE+0x2) /* Power management force */ - -/****************************************************************************** - * Extrnal Bus Controller - ******************************************************************************/ - /* values for EBC0_CFGADDR register - indirect addressing of these regs */ - #define PB0CR 0x00 /* periph bank 0 config reg */ - #define PB1CR 0x01 /* periph bank 1 config reg */ - #define PB2CR 0x02 /* periph bank 2 config reg */ - #define PB3CR 0x03 /* periph bank 3 config reg */ - #define PB4CR 0x04 /* periph bank 4 config reg */ -#ifndef CONFIG_405EP - #define PB5CR 0x05 /* periph bank 5 config reg */ - #define PB6CR 0x06 /* periph bank 6 config reg */ - #define PB7CR 0x07 /* periph bank 7 config reg */ -#endif - #define PB0AP 0x10 /* periph bank 0 access parameters */ - #define PB1AP 0x11 /* periph bank 1 access parameters */ - #define PB2AP 0x12 /* periph bank 2 access parameters */ - #define PB3AP 0x13 /* periph bank 3 access parameters */ - #define PB4AP 0x14 /* periph bank 4 access parameters */ -#ifndef CONFIG_405EP - #define PB5AP 0x15 /* periph bank 5 access parameters */ - #define PB6AP 0x16 /* periph bank 6 access parameters */ - #define PB7AP 0x17 /* periph bank 7 access parameters */ -#endif - #define PBEAR 0x20 /* periph bus error addr reg */ - #define PBESR0 0x21 /* periph bus error status reg 0 */ - #define PBESR1 0x22 /* periph bus error status reg 1 */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ - -#ifdef CONFIG_405EP -/****************************************************************************** - * Control - ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0f0 -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode register 0 */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Clock status register */ -#define CPC0_EPCTL (CNTRL_DCR_BASE+0x3) /* EMAC to PHY control register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode register 1 */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART control register */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI control register */ - -#define CPC0_PLLMR0 (CNTRL_DCR_BASE+0x0) /* PLL mode 0 register */ -#define CPC0_BOOT (CNTRL_DCR_BASE+0x1) /* Chip Clock Status register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x2) /* Chip Control 1 register */ -#define CPC0_EPRCSR (CNTRL_DCR_BASE+0x3) /* EMAC PHY Rcv Clk Src register */ -#define CPC0_PLLMR1 (CNTRL_DCR_BASE+0x4) /* PLL mode 1 register */ -#define CPC0_UCR (CNTRL_DCR_BASE+0x5) /* UART Control register */ -#define CPC0_SRR (CNTRL_DCR_BASE+0x6) /* Soft Reset register */ -#define CPC0_JTAGID (CNTRL_DCR_BASE+0x7) /* JTAG ID register */ -#define CPC0_SPARE (CNTRL_DCR_BASE+0x8) /* Spare DCR */ -#define CPC0_PCI (CNTRL_DCR_BASE+0x9) /* PCI Control register */ - -/* Bit definitions */ -#define PLLMR0_CPU_DIV_MASK 0x00300000 /* CPU clock divider */ -#define PLLMR0_CPU_DIV_BYPASS 0x00000000 -#define PLLMR0_CPU_DIV_2 0x00100000 -#define PLLMR0_CPU_DIV_3 0x00200000 -#define PLLMR0_CPU_DIV_4 0x00300000 - -#define PLLMR0_CPU_TO_PLB_MASK 0x00030000 /* CPU:PLB Frequency Divisor */ -#define PLLMR0_CPU_PLB_DIV_1 0x00000000 -#define PLLMR0_CPU_PLB_DIV_2 0x00010000 -#define PLLMR0_CPU_PLB_DIV_3 0x00020000 -#define PLLMR0_CPU_PLB_DIV_4 0x00030000 - -#define PLLMR0_OPB_TO_PLB_MASK 0x00003000 /* OPB:PLB Frequency Divisor */ -#define PLLMR0_OPB_PLB_DIV_1 0x00000000 -#define PLLMR0_OPB_PLB_DIV_2 0x00001000 -#define PLLMR0_OPB_PLB_DIV_3 0x00002000 -#define PLLMR0_OPB_PLB_DIV_4 0x00003000 - -#define PLLMR0_EXB_TO_PLB_MASK 0x00000300 /* External Bus:PLB Divisor */ -#define PLLMR0_EXB_PLB_DIV_2 0x00000000 -#define PLLMR0_EXB_PLB_DIV_3 0x00000100 -#define PLLMR0_EXB_PLB_DIV_4 0x00000200 -#define PLLMR0_EXB_PLB_DIV_5 0x00000300 - -#define PLLMR0_MAL_TO_PLB_MASK 0x00000030 /* MAL:PLB Divisor */ -#define PLLMR0_MAL_PLB_DIV_1 0x00000000 -#define PLLMR0_MAL_PLB_DIV_2 0x00000010 -#define PLLMR0_MAL_PLB_DIV_3 0x00000020 -#define PLLMR0_MAL_PLB_DIV_4 0x00000030 - -#define PLLMR0_PCI_TO_PLB_MASK 0x00000003 /* PCI:PLB Frequency Divisor */ -#define PLLMR0_PCI_PLB_DIV_1 0x00000000 -#define PLLMR0_PCI_PLB_DIV_2 0x00000001 -#define PLLMR0_PCI_PLB_DIV_3 0x00000002 -#define PLLMR0_PCI_PLB_DIV_4 0x00000003 - -#define PLLMR1_SSCS_MASK 0x80000000 /* Select system clock source */ -#define PLLMR1_PLLR_MASK 0x40000000 /* PLL reset */ -#define PLLMR1_FBMUL_MASK 0x00F00000 /* PLL feedback multiplier value */ -#define PLLMR1_FBMUL_DIV_16 0x00000000 -#define PLLMR1_FBMUL_DIV_1 0x00100000 -#define PLLMR1_FBMUL_DIV_2 0x00200000 -#define PLLMR1_FBMUL_DIV_3 0x00300000 -#define PLLMR1_FBMUL_DIV_4 0x00400000 -#define PLLMR1_FBMUL_DIV_5 0x00500000 -#define PLLMR1_FBMUL_DIV_6 0x00600000 -#define PLLMR1_FBMUL_DIV_7 0x00700000 -#define PLLMR1_FBMUL_DIV_8 0x00800000 -#define PLLMR1_FBMUL_DIV_9 0x00900000 -#define PLLMR1_FBMUL_DIV_10 0x00A00000 -#define PLLMR1_FBMUL_DIV_11 0x00B00000 -#define PLLMR1_FBMUL_DIV_12 0x00C00000 -#define PLLMR1_FBMUL_DIV_13 0x00D00000 -#define PLLMR1_FBMUL_DIV_14 0x00E00000 -#define PLLMR1_FBMUL_DIV_15 0x00F00000 - -#define PLLMR1_FWDVA_MASK 0x00070000 /* PLL forward divider A value */ -#define PLLMR1_FWDVA_DIV_8 0x00000000 -#define PLLMR1_FWDVA_DIV_7 0x00010000 -#define PLLMR1_FWDVA_DIV_6 0x00020000 -#define PLLMR1_FWDVA_DIV_5 0x00030000 -#define PLLMR1_FWDVA_DIV_4 0x00040000 -#define PLLMR1_FWDVA_DIV_3 0x00050000 -#define PLLMR1_FWDVA_DIV_2 0x00060000 -#define PLLMR1_FWDVA_DIV_1 0x00070000 -#define PLLMR1_FWDVB_MASK 0x00007000 /* PLL forward divider B value */ -#define PLLMR1_TUNING_MASK 0x000003FF /* PLL tune bits */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -/* Defines for CPC0_PCI Register */ -#define CPC0_PCI_SPE 0x00000010 /* PCIINT/WE select */ -#define CPC0_PCI_HOST_CFG_EN 0x00000008 /* PCI host config Enable */ -#define CPC0_PCI_ARBIT_EN 0x00000001 /* PCI Internal Arb Enabled */ - -/* Defines for CPC0_BOOR Register */ -#define CPC0_BOOT_SEP 0x00000002 /* serial EEPROM present */ - -/* Defines for CPC0_PLLMR1 Register fields */ -#define PLL_ACTIVE 0x80000000 -#define CPC0_PLLMR1_SSCS 0x80000000 -#define PLL_RESET 0x40000000 -#define CPC0_PLLMR1_PLLR 0x40000000 - /* Feedback multiplier */ -#define PLL_FBKDIV 0x00F00000 -#define CPC0_PLLMR1_FBDV 0x00F00000 -#define PLL_FBKDIV_16 0x00000000 -#define PLL_FBKDIV_1 0x00100000 -#define PLL_FBKDIV_2 0x00200000 -#define PLL_FBKDIV_3 0x00300000 -#define PLL_FBKDIV_4 0x00400000 -#define PLL_FBKDIV_5 0x00500000 -#define PLL_FBKDIV_6 0x00600000 -#define PLL_FBKDIV_7 0x00700000 -#define PLL_FBKDIV_8 0x00800000 -#define PLL_FBKDIV_9 0x00900000 -#define PLL_FBKDIV_10 0x00A00000 -#define PLL_FBKDIV_11 0x00B00000 -#define PLL_FBKDIV_12 0x00C00000 -#define PLL_FBKDIV_13 0x00D00000 -#define PLL_FBKDIV_14 0x00E00000 -#define PLL_FBKDIV_15 0x00F00000 - /* Forward A divisor */ -#define PLL_FWDDIVA 0x00070000 -#define CPC0_PLLMR1_FWDVA 0x00070000 -#define PLL_FWDDIVA_8 0x00000000 -#define PLL_FWDDIVA_7 0x00010000 -#define PLL_FWDDIVA_6 0x00020000 -#define PLL_FWDDIVA_5 0x00030000 -#define PLL_FWDDIVA_4 0x00040000 -#define PLL_FWDDIVA_3 0x00050000 -#define PLL_FWDDIVA_2 0x00060000 -#define PLL_FWDDIVA_1 0x00070000 - /* Forward B divisor */ -#define PLL_FWDDIVB 0x00007000 -#define CPC0_PLLMR1_FWDVB 0x00007000 -#define PLL_FWDDIVB_8 0x00000000 -#define PLL_FWDDIVB_7 0x00001000 -#define PLL_FWDDIVB_6 0x00002000 -#define PLL_FWDDIVB_5 0x00003000 -#define PLL_FWDDIVB_4 0x00004000 -#define PLL_FWDDIVB_3 0x00005000 -#define PLL_FWDDIVB_2 0x00006000 -#define PLL_FWDDIVB_1 0x00007000 - /* PLL tune bits */ -#define PLL_TUNE_MASK 0x000003FF -#define PLL_TUNE_2_M_3 0x00000133 /* 2 <= M <= 3 */ -#define PLL_TUNE_4_M_6 0x00000134 /* 3 < M <= 6 */ -#define PLL_TUNE_7_M_10 0x00000138 /* 6 < M <= 10 */ -#define PLL_TUNE_11_M_14 0x0000013C /* 10 < M <= 14 */ -#define PLL_TUNE_15_M_40 0x0000023E /* 14 < M <= 40 */ -#define PLL_TUNE_VCO_LOW 0x00000000 /* 500MHz <= VCO <= 800MHz */ -#define PLL_TUNE_VCO_HI 0x00000080 /* 800MHz < VCO <= 1000MHz */ - -/* Defines for CPC0_PLLMR0 Register fields */ - /* CPU divisor */ -#define PLL_CPUDIV 0x00300000 -#define CPC0_PLLMR0_CCDV 0x00300000 -#define PLL_CPUDIV_1 0x00000000 -#define PLL_CPUDIV_2 0x00100000 -#define PLL_CPUDIV_3 0x00200000 -#define PLL_CPUDIV_4 0x00300000 - /* PLB divisor */ -#define PLL_PLBDIV 0x00030000 -#define CPC0_PLLMR0_CBDV 0x00030000 -#define PLL_PLBDIV_1 0x00000000 -#define PLL_PLBDIV_2 0x00010000 -#define PLL_PLBDIV_3 0x00020000 -#define PLL_PLBDIV_4 0x00030000 - /* OPB divisor */ -#define PLL_OPBDIV 0x00003000 -#define CPC0_PLLMR0_OPDV 0x00003000 -#define PLL_OPBDIV_1 0x00000000 -#define PLL_OPBDIV_2 0x00001000 -#define PLL_OPBDIV_3 0x00002000 -#define PLL_OPBDIV_4 0x00003000 - /* EBC divisor */ -#define PLL_EXTBUSDIV 0x00000300 -#define CPC0_PLLMR0_EPDV 0x00000300 -#define PLL_EXTBUSDIV_2 0x00000000 -#define PLL_EXTBUSDIV_3 0x00000100 -#define PLL_EXTBUSDIV_4 0x00000200 -#define PLL_EXTBUSDIV_5 0x00000300 - /* MAL divisor */ -#define PLL_MALDIV 0x00000030 -#define CPC0_PLLMR0_MPDV 0x00000030 -#define PLL_MALDIV_1 0x00000000 -#define PLL_MALDIV_2 0x00000010 -#define PLL_MALDIV_3 0x00000020 -#define PLL_MALDIV_4 0x00000030 - /* PCI divisor */ -#define PLL_PCIDIV 0x00000003 -#define CPC0_PLLMR0_PPFD 0x00000003 -#define PLL_PCIDIV_1 0x00000000 -#define PLL_PCIDIV_2 0x00000001 -#define PLL_PCIDIV_3 0x00000002 -#define PLL_PCIDIV_4 0x00000003 - -/* - *------------------------------------------------------------------------------ - * PLL settings for 266MHz CPU, 133MHz PLB/SDRAM, 66MHz EBC, 33MHz PCI, - * assuming a 33.3MHz input clock to the 405EP. - *------------------------------------------------------------------------------ - */ -#define PLLMR0_266_133_66 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) - -#define PLLMR0_133_66_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_1 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_133_66_66_33 (PLL_FBKDIV_4 | \ - PLL_FWDDIVA_6 | PLL_FWDDIVB_6 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_200_100_50_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_3 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_200_100_50_33 (PLL_FBKDIV_6 | \ - PLL_FWDDIVA_4 | PLL_FWDDIVB_4 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_133_66_33 (PLL_CPUDIV_1 | PLL_PLBDIV_2 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_4 | \ - PLL_MALDIV_1 | PLL_PCIDIV_4) -#define PLLMR1_266_133_66_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_266_66_33_33 (PLL_CPUDIV_1 | PLL_PLBDIV_4 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_2) -#define PLLMR1_266_66_33_33 (PLL_FBKDIV_8 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_LOW) -#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_3) -#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) -#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 | \ - PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 | \ - PLL_MALDIV_1 | PLL_PCIDIV_1) -#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 | \ - PLL_FWDDIVA_3 | PLL_FWDDIVB_3 | \ - PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI) - -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. - */ -#define VCO_MIN 500 -#define VCO_MAX 1000 -#elif defined(CONFIG_405EZ) -#define SDR0_NAND0 0x4000 -#define SDR0_ULTRA0 0x4040 -#define SDR0_ULTRA1 0x4050 -#define SDR0_ICINTSTAT 0x4510 - -#define SDR_NAND0_NDEN 0x80000000 -#define SDR_NAND0_NDBTEN 0x40000000 -#define SDR_NAND0_NDBADR_MASK 0x30000000 -#define SDR_NAND0_NDBPG_MASK 0x0f000000 -#define SDR_NAND0_NDAREN 0x00800000 -#define SDR_NAND0_NDRBEN 0x00400000 - -#define SDR_ULTRA0_NDGPIOBP 0x80000000 -#define SDR_ULTRA0_CSN_MASK 0x78000000 -#define SDR_ULTRA0_CSNSEL0 0x40000000 -#define SDR_ULTRA0_CSNSEL1 0x20000000 -#define SDR_ULTRA0_CSNSEL2 0x10000000 -#define SDR_ULTRA0_CSNSEL3 0x08000000 -#define SDR_ULTRA0_EBCRDYEN 0x04000000 -#define SDR_ULTRA0_SPISSINEN 0x02000000 -#define SDR_ULTRA0_NFSRSTEN 0x01000000 - -#define SDR_ULTRA1_LEDNENABLE 0x40000000 - -#define SDR_ICRX_STAT 0x80000000 -#define SDR_ICTX0_STAT 0x40000000 -#define SDR_ICTX1_STAT 0x20000000 - -#define SDR0_PINSTP 0x40 - -/****************************************************************************** - * Control - ******************************************************************************/ -/* CPR Registers */ -#define CPR0_CLKUP 0x020 /* CPR_CLKUPD */ -#define CPR0_PLLC 0x040 /* CPR_PLLC */ -#define CPR0_PLLD 0x060 /* CPR_PLLD */ -#define CPC0_PRIMAD 0x080 /* CPR_PRIMAD */ -#define CPC0_PERD0 0x0e0 /* CPR_PERD0 */ -#define CPC0_PERD1 0x0e1 /* CPR_PERD1 */ -#define CPC0_PERC0 0x180 /* CPR_PERC0 */ - -#define CPR_CLKUPD_ENPLLCH_EN 0x40000000 /* Enable CPR PLL Changes */ -#define CPR_CLKUPD_ENDVCH_EN 0x20000000 /* Enable CPR Sys. Div. Changes */ -#define CPR_PERD0_SPIDV_MASK 0x000F0000 /* SPI Clock Divider */ - -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ - -#define PLLD_FBDV_MASK 0x1F000000 /* PLL feedback divider value */ -#define PLLD_FWDVA_MASK 0x000F0000 /* PLL forward divider A value */ -#define PLLD_FWDVB_MASK 0x00000700 /* PLL forward divider B value */ - -#define PRIMAD_CPUDV_MASK 0x0F000000 /* CPU Clock Divisor Mask */ -#define PRIMAD_PLBDV_MASK 0x000F0000 /* PLB Clock Divisor Mask */ -#define PRIMAD_OPBDV_MASK 0x00000F00 /* OPB Clock Divisor Mask */ -#define PRIMAD_EBCDV_MASK 0x0000000F /* EBC Clock Divisor Mask */ - -#define PERD0_PWMDV_MASK 0xFF000000 /* PWM Divider Mask */ -#define PERD0_SPIDV_MASK 0x000F0000 /* SPI Divider Mask */ -#define PERD0_U0DV_MASK 0x0000FF00 /* UART 0 Divider Mask */ -#define PERD0_U1DV_MASK 0x000000FF /* UART 1 Divider Mask */ - -#else /* #ifdef CONFIG_405EP */ -/****************************************************************************** - * Control - ******************************************************************************/ -#define CNTRL_DCR_BASE 0x0b0 -#define CPC0_PLLMR (CNTRL_DCR_BASE + 0x0) /* PLL mode register */ -#define CPC0_CR0 (CNTRL_DCR_BASE + 0x1) /* chip control register 0 */ -#define CPC0_CR1 (CNTRL_DCR_BASE + 0x2) /* chip control register 1 */ -#define CPC0_PSR (CNTRL_DCR_BASE + 0x4) /* chip pin strapping reg */ - -/* CPC0_ECR/CPC0_EIRR: PPC405GPr only */ -#define CPC0_EIRR (CNTRL_DCR_BASE + 0x6) /* ext interrupt routing reg */ -#define CPC0_ECR 0xaa /* edge conditioner register */ - -/* Bit definitions */ -#define PLLMR_FWD_DIV_MASK 0xE0000000 /* Forward Divisor */ -#define PLLMR_FWD_DIV_BYPASS 0xE0000000 -#define PLLMR_FWD_DIV_3 0xA0000000 -#define PLLMR_FWD_DIV_4 0x80000000 -#define PLLMR_FWD_DIV_6 0x40000000 - -#define PLLMR_FB_DIV_MASK 0x1E000000 /* Feedback Divisor */ -#define PLLMR_FB_DIV_1 0x02000000 -#define PLLMR_FB_DIV_2 0x04000000 -#define PLLMR_FB_DIV_3 0x06000000 -#define PLLMR_FB_DIV_4 0x08000000 - -#define PLLMR_TUNING_MASK 0x01F80000 - -#define PLLMR_CPU_TO_PLB_MASK 0x00060000 /* CPU:PLB Frequency Divisor */ -#define PLLMR_CPU_PLB_DIV_1 0x00000000 -#define PLLMR_CPU_PLB_DIV_2 0x00020000 -#define PLLMR_CPU_PLB_DIV_3 0x00040000 -#define PLLMR_CPU_PLB_DIV_4 0x00060000 - -#define PLLMR_OPB_TO_PLB_MASK 0x00018000 /* OPB:PLB Frequency Divisor */ -#define PLLMR_OPB_PLB_DIV_1 0x00000000 -#define PLLMR_OPB_PLB_DIV_2 0x00008000 -#define PLLMR_OPB_PLB_DIV_3 0x00010000 -#define PLLMR_OPB_PLB_DIV_4 0x00018000 - -#define PLLMR_PCI_TO_PLB_MASK 0x00006000 /* PCI:PLB Frequency Divisor */ -#define PLLMR_PCI_PLB_DIV_1 0x00000000 -#define PLLMR_PCI_PLB_DIV_2 0x00002000 -#define PLLMR_PCI_PLB_DIV_3 0x00004000 -#define PLLMR_PCI_PLB_DIV_4 0x00006000 - -#define PLLMR_EXB_TO_PLB_MASK 0x00001800 /* External Bus:PLB Divisor */ -#define PLLMR_EXB_PLB_DIV_2 0x00000000 -#define PLLMR_EXB_PLB_DIV_3 0x00000800 -#define PLLMR_EXB_PLB_DIV_4 0x00001000 -#define PLLMR_EXB_PLB_DIV_5 0x00001800 - -/* definitions for PPC405GPr (new mode strapping) */ -#define PLLMR_FWDB_DIV_MASK 0x00000007 /* Forward Divisor B */ - -#define PSR_PLL_FWD_MASK 0xC0000000 -#define PSR_PLL_FDBACK_MASK 0x30000000 -#define PSR_PLL_TUNING_MASK 0x0E000000 -#define PSR_PLB_CPU_MASK 0x01800000 -#define PSR_OPB_PLB_MASK 0x00600000 -#define PSR_PCI_PLB_MASK 0x00180000 -#define PSR_EB_PLB_MASK 0x00060000 -#define PSR_ROM_WIDTH_MASK 0x00018000 -#define PSR_ROM_LOC 0x00004000 -#define PSR_PCI_ASYNC_EN 0x00001000 -#define PSR_PERCLK_SYNC_MODE_EN 0x00000800 /* PPC405GPr only */ -#define PSR_PCI_ARBIT_EN 0x00000400 -#define PSR_NEW_MODE_EN 0x00000020 /* PPC405GPr only */ - -#ifndef CONFIG_IOP480 -/* - * PLL Voltage Controlled Oscillator (VCO) definitions - * Maximum and minimum values (in MHz) for correct PLL operation. -*/ -#define VCO_MIN 400 -#define VCO_MAX 800 -#endif /* #ifndef CONFIG_IOP480 */ -#endif /* #ifdef CONFIG_405EP */ - -/****************************************************************************** - * Memory Access Layer - ******************************************************************************/ -#if defined(CONFIG_405EZ) -#define MAL_DCR_BASE 0x380 -#else -#define MAL_DCR_BASE 0x180 -#endif -#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ -#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Err Status (Read/Clear) */ -#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ -#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ -#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ -#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status */ -#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int reg */ -#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ -#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ -#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status */ -#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int reg */ -#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table ptr */ -#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table ptr */ -#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table ptr */ -#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table ptr */ -#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table ptr */ -#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table ptr */ -#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table ptr */ -#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table ptr */ -#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table ptr */ -#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table ptr */ -#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table ptr */ -#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ -#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ -#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ -#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ -#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ -#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ -#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ - -/*----------------------------------------------------------------------------- -| UART Register Offsets -'----------------------------------------------------------------------------*/ -#define DATA_REG 0x00 -#define DL_LSB 0x00 -#define DL_MSB 0x01 -#define INT_ENABLE 0x01 -#define FIFO_CONTROL 0x02 -#define LINE_CONTROL 0x03 -#define MODEM_CONTROL 0x04 -#define LINE_STATUS 0x05 -#define MODEM_STATUS 0x06 -#define SCRATCH 0x07 - -/****************************************************************************** - * On Chip Memory - ******************************************************************************/ -#if defined(CONFIG_405EZ) -#define OCM_DCR_BASE 0x020 -#define OCM0_PLBCR1 (OCM_DCR_BASE + 0x00) /* OCM PLB3 Bank 1 Config */ -#define OCM0_PLBCR2 (OCM_DCR_BASE + 0x01) /* OCM PLB3 Bank 2 Config */ -#define OCM0_PLBBEAR (OCM_DCR_BASE + 0x02) /* OCM PLB3 Bus Error Add */ -#define OCM0_DSRC1 (OCM_DCR_BASE + 0x08) /* OCM D-side Bank 1 Config */ -#define OCM0_DSRC2 (OCM_DCR_BASE + 0x09) /* OCM D-side Bank 2 Config */ -#define OCM0_ISRC1 (OCM_DCR_BASE + 0x0A) /* OCM I-side Bank 1Config */ -#define OCM0_ISRC2 (OCM_DCR_BASE + 0x0B) /* OCM I-side Bank 2 Config */ -#define OCM0_DISDPC (OCM_DCR_BASE + 0x0C) /* OCM D-/I-side Data Par Chk */ -#else -#define OCM_DCR_BASE 0x018 -#define OCM0_ISCNTL (OCM_DCR_BASE+0x01) /* OCM I-side control reg */ -#define OCM0_DSARC (OCM_DCR_BASE+0x02) /* OCM D-side address compare */ -#define OCM0_DSCNTL (OCM_DCR_BASE+0x03) /* OCM D-side control */ -#endif /* CONFIG_405EZ */ - -/****************************************************************************** - * GPIO macro register defines - ******************************************************************************/ -#if defined(CONFIG_405EZ) -/* Only the 405EZ has 2 GPIOs */ -#define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_RR3 (GPIO_BASE+0x28) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) - -#define GPIO1_BASE 0xEF600800 -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) - -#elif defined(CONFIG_405EX) -#define GPIO_BASE 0xEF600800 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRL (GPIO_BASE+0x8) -#define GPIO0_OSRH (GPIO_BASE+0xC) -#define GPIO0_TSRL (GPIO_BASE+0x10) -#define GPIO0_TSRH (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1L (GPIO_BASE+0x30) -#define GPIO0_ISR1H (GPIO_BASE+0x34) -#define GPIO0_ISR2L (GPIO_BASE+0x38) -#define GPIO0_ISR2H (GPIO_BASE+0x3C) -#define GPIO0_ISR3L (GPIO_BASE+0x40) -#define GPIO0_ISR3H (GPIO_BASE+0x44) - -#else /* !405EZ */ - -#define GPIO_BASE 0xEF600700 -#define GPIO0_OR (GPIO_BASE+0x0) -#define GPIO0_TCR (GPIO_BASE+0x4) -#define GPIO0_OSRH (GPIO_BASE+0x8) -#define GPIO0_OSRL (GPIO_BASE+0xC) -#define GPIO0_TSRH (GPIO_BASE+0x10) -#define GPIO0_TSRL (GPIO_BASE+0x14) -#define GPIO0_ODR (GPIO_BASE+0x18) -#define GPIO0_IR (GPIO_BASE+0x1C) -#define GPIO0_RR1 (GPIO_BASE+0x20) -#define GPIO0_RR2 (GPIO_BASE+0x24) -#define GPIO0_ISR1H (GPIO_BASE+0x30) -#define GPIO0_ISR1L (GPIO_BASE+0x34) -#define GPIO0_ISR2H (GPIO_BASE+0x38) -#define GPIO0_ISR2L (GPIO_BASE+0x3C) - -#endif /* CONFIG_405EZ */ - -#define GPIO0_BASE GPIO_BASE - -#if defined(CONFIG_405EX) -#define SDR0_SRST 0x0200 - -/* - * Software Reset Register - */ -#define SDR0_SRST_BGO PPC_REG_VAL(0, 1) -#define SDR0_SRST_PLB4 PPC_REG_VAL(1, 1) -#define SDR0_SRST_EBC PPC_REG_VAL(2, 1) -#define SDR0_SRST_OPB PPC_REG_VAL(3, 1) -#define SDR0_SRST_UART0 PPC_REG_VAL(4, 1) -#define SDR0_SRST_UART1 PPC_REG_VAL(5, 1) -#define SDR0_SRST_IIC0 PPC_REG_VAL(6, 1) -#define SDR0_SRST_BGI PPC_REG_VAL(7, 1) -#define SDR0_SRST_GPIO PPC_REG_VAL(8, 1) -#define SDR0_SRST_GPT PPC_REG_VAL(9, 1) -#define SDR0_SRST_DMC PPC_REG_VAL(10, 1) -#define SDR0_SRST_RGMII PPC_REG_VAL(11, 1) -#define SDR0_SRST_EMAC0 PPC_REG_VAL(12, 1) -#define SDR0_SRST_EMAC1 PPC_REG_VAL(13, 1) -#define SDR0_SRST_CPM PPC_REG_VAL(14, 1) -#define SDR0_SRST_EPLL PPC_REG_VAL(15, 1) -#define SDR0_SRST_UIC PPC_REG_VAL(16, 1) -#define SDR0_SRST_UPRST PPC_REG_VAL(17, 1) -#define SDR0_SRST_IIC1 PPC_REG_VAL(18, 1) -#define SDR0_SRST_SCP PPC_REG_VAL(19, 1) -#define SDR0_SRST_UHRST PPC_REG_VAL(20, 1) -#define SDR0_SRST_DMA PPC_REG_VAL(21, 1) -#define SDR0_SRST_DMAC PPC_REG_VAL(22, 1) -#define SDR0_SRST_MAL PPC_REG_VAL(23, 1) -#define SDR0_SRST_EBM PPC_REG_VAL(24, 1) -#define SDR0_SRST_GPTR PPC_REG_VAL(25, 1) -#define SDR0_SRST_PE0 PPC_REG_VAL(26, 1) -#define SDR0_SRST_PE1 PPC_REG_VAL(27, 1) -#define SDR0_SRST_CRYP PPC_REG_VAL(28, 1) -#define SDR0_SRST_PKP PPC_REG_VAL(29, 1) -#define SDR0_SRST_AHB PPC_REG_VAL(30, 1) -#define SDR0_SRST_NDFC PPC_REG_VAL(31, 1) - -#define SDR0_UART0 0x0120 /* UART0 Config */ -#define SDR0_UART1 0x0121 /* UART1 Config */ -#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ - -/* Defines for CPC0_EPRCSR register */ -#define CPC0_EPRCSR_E0NFE 0x80000000 -#define CPC0_EPRCSR_E1NFE 0x40000000 -#define CPC0_EPRCSR_E1RPP 0x00000080 -#define CPC0_EPRCSR_E0RPP 0x00000040 -#define CPC0_EPRCSR_E1ERP 0x00000020 -#define CPC0_EPRCSR_E0ERP 0x00000010 -#define CPC0_EPRCSR_E1PCI 0x00000002 -#define CPC0_EPRCSR_E0PCI 0x00000001 - -#define CPR0_CLKUPD 0x020 -#define CPR0_PLLC 0x040 -#define CPR0_PLLD 0x060 -#define CPR0_CPUD 0x080 -#define CPR0_PLBD 0x0a0 -#define CPR0_OPBD0 0x0c0 -#define CPR0_PERD 0x0e0 - -#define SDR0_PINSTP 0x0040 -#define SDR0_SDCS0 0x0060 - -#define SDR0_SDCS_SDD (0x80000000 >> 31) - -/* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width= 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width= 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Sel Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Sel Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /* All Chip Sel Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Sel0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Sel1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Sel2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Sel3 Gating Enable */ - -#define SDR0_PFC0 0x4100 -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME 0x02000000 -#define SDR0_PFC1_U0ME 0x00080000 -#define SDR0_PFC1_U0IM 0x00040000 -#define SDR0_PFC1_SIS 0x00020000 -#define SDR0_PFC1_DMAAEN 0x00010000 -#define SDR0_PFC1_DMADEN 0x00008000 -#define SDR0_PFC1_USBEN 0x00004000 -#define SDR0_PFC1_AHBSWAP 0x00000020 -#define SDR0_PFC1_USBBIGEN 0x00000010 -#define SDR0_PFC1_GPT_FREQ 0x0000000f -#endif - -/* General Purpose Timer (GPT) Register Offsets */ -#define GPT0_TBC 0x00000000 -#define GPT0_IM 0x00000018 -#define GPT0_ISS 0x0000001C -#define GPT0_ISC 0x00000020 -#define GPT0_IE 0x00000024 -#define GPT0_COMP0 0x00000080 -#define GPT0_COMP1 0x00000084 -#define GPT0_COMP2 0x00000088 -#define GPT0_COMP3 0x0000008C -#define GPT0_COMP4 0x00000090 -#define GPT0_COMP5 0x00000094 -#define GPT0_COMP6 0x00000098 -#define GPT0_MASK0 0x000000C0 -#define GPT0_MASK1 0x000000C4 -#define GPT0_MASK2 0x000000C8 -#define GPT0_MASK3 0x000000CC -#define GPT0_MASK4 0x000000D0 -#define GPT0_MASK5 0x000000D4 -#define GPT0_MASK6 0x000000D8 -#define GPT0_DCT0 0x00000110 -#define GPT0_DCIS 0x0000011C - -#endif /* __PPC405_H__ */ diff --git a/include/ppc440.h b/include/ppc440.h deleted file mode 100644 index 6727753..0000000 --- a/include/ppc440.h +++ /dev/null @@ -1,1958 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of the -| GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - -/* - * (C) Copyright 2006 - * Sylvie Gohl, AMCC/IBM, gohl.sylvie@fr.ibm.com - * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com - * Thierry Roman, AMCC/IBM, thierry_roman@fr.ibm.com - * Alain Saurel, AMCC/IBM, alain.saurel@fr.ibm.com - * Robert Snyder, AMCC/IBM, rob.snyder@fr.ibm.com - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __PPC440_H__ -#define __PPC440_H__ - -#define CONFIG_SYS_DCACHE_SIZE (32 << 10) /* For AMCC 440 CPUs */ - -/****************************************************************************** - * DCRs & Related - ******************************************************************************/ - -/*----------------------------------------------------------------------------- - | Clocking Controller - +----------------------------------------------------------------------------*/ -/* values for clkcfga register - indirect addressing of these regs */ -#define CPR0_PLLC 0x0040 -#define CPR0_PLLD 0x0060 -#define CPR0_PRIMAD0 0x0080 -#define CPR0_PRIMBD0 0x00a0 -#define CPR0_OPBD0 0x00c0 -#define CPR0_PERD 0x00e0 -#define CPR0_MALD 0x0100 -#define CPR0_SPCID 0x0120 -#define CPR0_ICFG 0x0140 - -/* 440EPX boot strap options */ -#define BOOT_STRAP_OPTION_A 0x00000000 -#define BOOT_STRAP_OPTION_B 0x00000001 -#define BOOT_STRAP_OPTION_D 0x00000003 -#define BOOT_STRAP_OPTION_E 0x00000004 - -/* 440gx sdr register definations */ -#define SDR0_SDSTP0 0x0020 /* */ -#define SDR0_SDSTP1 0x0021 /* */ -#define SDR0_PINSTP 0x0040 -#define SDR0_SDCS0 0x0060 -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_DDRCFG 0x00e0 -#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ -#define SDR0_EBC 0x0100 -#define SDR0_UART0 0x0120 /* UART0 Config */ -#define SDR0_UART1 0x0121 /* UART1 Config */ -#define SDR0_UART2 0x0122 /* UART2 Config */ -#define SDR0_UART3 0x0123 /* UART3 Config */ -#define SDR0_CP440 0x0180 -#define SDR0_XCR 0x01c0 -#define SDR0_XPLLC 0x01c1 -#define SDR0_XPLLD 0x01c2 -#define SDR0_SRST 0x0200 -#define SD0_AMP0 0x0240 /* Override PLB4 prioritiy for up to 8 masters */ -#define SD0_AMP1 0x0241 /* Override PLB3 prioritiy for up to 8 masters */ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_PCI0 0x01c0 -#else -#define SDR0_PCI0 0x0300 -#endif -#define SDR0_USB0 0x0320 -#define SDR0_CUST0 0x4000 -#define SDR0_CUST1 0x4002 -#define SDR0_PFC0 0x4100 /* Pin Function 0 */ -#define SDR0_PFC1 0x4101 /* Pin Function 1 */ -#define SDR0_MFR 0x4300 /* SDR0_MFR reg */ - -#if defined(CONFIG_440GX) -#define SD0_AMP 0x0240 -#define SDR0_XPLLC 0x01c1 -#define SDR0_XPLLD 0x01c2 -#define SDR0_XCR 0x01c0 -#define SDR0_SDSTP2 0x4001 -#define SDR0_SDSTP3 0x4003 -#endif /* CONFIG_440GX */ - -/*----------------------------------------------------------------------------+ -| Core Configuration/MMU configuration for 440 (CCR1 for 440x5 only). -+----------------------------------------------------------------------------*/ -#define CCR0_PRE 0x40000000 -#define CCR0_CRPE 0x08000000 -#define CCR0_DSTG 0x00200000 -#define CCR0_DAPUIB 0x00100000 -#define CCR0_DTB 0x00008000 -#define CCR0_GICBT 0x00004000 -#define CCR0_GDCBT 0x00002000 -#define CCR0_FLSTA 0x00000100 -#define CCR0_ICSLC_MASK 0x0000000C -#define CCR0_ICSLT_MASK 0x00000003 -#define CCR1_TCS_MASK 0x00000080 -#define CCR1_TCS_INTCLK 0x00000000 -#define CCR1_TCS_EXTCLK 0x00000080 -#define MMUCR_SWOA 0x01000000 -#define MMUCR_U1TE 0x00400000 -#define MMUCR_U2SWOAE 0x00200000 -#define MMUCR_DULXE 0x00800000 -#define MMUCR_IULXE 0x00400000 -#define MMUCR_STS 0x00100000 -#define MMUCR_STID_MASK 0x000000FF - -#ifdef CONFIG_440SPE -#undef SDR0_SDSTP2 -#define SDR0_SDSTP2 0x0022 -#undef SDR0_SDSTP3 -#define SDR0_SDSTP3 0x0023 -#define SDR0_DDR0 0x00E1 -#define SDR0_UART2 0x0122 -#define SDR0_XCR0 0x01c0 -#define SDR0_XCR1 0x01c3 -#define SDR0_XCR2 0x01c6 -#define SDR0_XPLLC0 0x01c1 -#define SDR0_XPLLD0 0x01c2 -#define SDR0_XPLLC1 0x01c4 /* notRCW - SG */ -#define SDR0_XPLLD1 0x01c5 /* notRCW - SG */ -#define SDR0_XPLLC2 0x01c7 /* notRCW - SG */ -#define SDR0_XPLLD2 0x01c8 /* dnotRCW - SG */ -#define SD0_AMP0 0x0240 -#define SD0_AMP1 0x0241 -#define SDR0_CUST2 0x4004 -#define SDR0_CUST3 0x4006 -#define SDR0_SDSTP4 0x4001 -#define SDR0_SDSTP5 0x4003 -#define SDR0_SDSTP6 0x4005 -#define SDR0_SDSTP7 0x4007 - -#endif /* CONFIG_440SPE */ - -/*----------------------------------------------------------------------------- - | External Bus Controller - +----------------------------------------------------------------------------*/ -/* values for EBC0_CFGADDR register - indirect addressing of these regs */ -#define PB0CR 0x00 /* periph bank 0 config reg */ -#define PB1CR 0x01 /* periph bank 1 config reg */ -#define PB2CR 0x02 /* periph bank 2 config reg */ -#define PB3CR 0x03 /* periph bank 3 config reg */ -#define PB4CR 0x04 /* periph bank 4 config reg */ -#define PB5CR 0x05 /* periph bank 5 config reg */ -#define PB6CR 0x06 /* periph bank 6 config reg */ -#define PB7CR 0x07 /* periph bank 7 config reg */ -#define PB0AP 0x10 /* periph bank 0 access parameters */ -#define PB1AP 0x11 /* periph bank 1 access parameters */ -#define PB2AP 0x12 /* periph bank 2 access parameters */ -#define PB3AP 0x13 /* periph bank 3 access parameters */ -#define PB4AP 0x14 /* periph bank 4 access parameters */ -#define PB5AP 0x15 /* periph bank 5 access parameters */ -#define PB6AP 0x16 /* periph bank 6 access parameters */ -#define PB7AP 0x17 /* periph bank 7 access parameters */ -#define PBEAR 0x20 /* periph bus error addr reg */ -#define PBESR 0x21 /* periph bus error status reg */ -#define EBC0_CFG 0x23 /* external bus configuration reg */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - - /* PLB3 Arbiter */ -#define PLB3_DCR_BASE 0x070 -#define PLB3_ACR (PLB3_DCR_BASE + 0x7) - - /* PLB4 Arbiter - PowerPC440EP Pass1 */ -#define PLB4_DCR_BASE 0x080 -#define PLB4_ACR (PLB4_DCR_BASE + 0x1) - -#define PLB4_ACR_WRP (0x80000000 >> 7) - - /* Pin Function Control Register 1 */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold - Req Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) - Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) - Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. - Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject - Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject - Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject - Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor Enable - Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor - Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor - Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation - Gated In */ - - /* USB Control Register */ -#define SDR0_USB0 0x0320 -#define SDR0_USB0_USB_DEVSEL_MASK 0x00000002 /* USB Device Selection */ -#define SDR0_USB0_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ -#define SDR0_USB0_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ -#define SDR0_USB0_LEEN_MASK 0x00000001 /* Little Endian selection */ -#define SDR0_USB0_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ -#define SDR0_USB0_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ - - /* Miscealleneaous Function Reg. */ -#define SDR0_MFR 0x4300 -#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ -#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) - -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ - -#define GPT0_COMP6 0x00000098 -#define GPT0_COMP5 0x00000094 -#define GPT0_COMP4 0x00000090 -#define GPT0_COMP3 0x0000008C -#define GPT0_COMP2 0x00000088 -#define GPT0_COMP1 0x00000084 - -#define GPT0_MASK6 0x000000D8 -#define GPT0_MASK5 0x000000D4 -#define GPT0_MASK4 0x000000D0 -#define GPT0_MASK3 0x000000CC -#define GPT0_MASK2 0x000000C8 -#define GPT0_MASK1 0x000000C4 - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_USB2D0CR 0x0320 -#define SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK 0x00000004 /* USB 2.0 Device/EBC - Master Selection */ -#define SDR0_USB2D0CR_USB2DEV_SELECTION 0x00000004 /* USB 2.0 Device Selection*/ -#define SDR0_USB2D0CR_EBC_SELECTION 0x00000000 /* EBC Selection */ - -#define SDR0_USB2D0CR_USB_DEV_INT_SEL_MASK 0x00000002 /* USB Device Interface - Selection */ -#define SDR0_USB2D0CR_USB20D_DEVSEL 0x00000000 /* USB2.0 Device Selected */ -#define SDR0_USB2D0CR_USB11D_DEVSEL 0x00000002 /* USB1.1 Device Selected */ - -#define SDR0_USB2D0CR_LEEN_MASK 0x00000001 /* Little Endian selection */ -#define SDR0_USB2D0CR_LEEN_DISABLE 0x00000000 /* Little Endian Disable */ -#define SDR0_USB2D0CR_LEEN_ENABLE 0x00000001 /* Little Endian Enable */ - - /* USB2 Host Control Register */ -#define SDR0_USB2H0CR 0x0340 -#define SDR0_USB2H0CR_WDINT_MASK 0x00000001 /* Host UTMI Word Interface*/ -#define SDR0_USB2H0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit/60MHz */ -#define SDR0_USB2H0CR_WDINT_16BIT_30MHZ 0x00000001 /* 16-bit/30MHz */ -#define SDR0_USB2H0CR_EFLADJ_MASK 0x0000007e /* EHCI Frame Length - Adjustment */ - - /* Pin Function Control Register 1 */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ - -#define SDR0_PFC1_SELECT_MASK 0x01C00000 /* Ethernet Pin Select - EMAC 0 */ -#define SDR0_PFC1_SELECT_CONFIG_1_1 0x00C00000 /* 1xMII using RGMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_2 0x00C00000 /* 1xGMII using RGMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_3 0x01000000 /* 1xTBI using RGMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_4 0x01400000 /* 2xRGMII using RGMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_5 0x01800000 /* 2xRTBI using RGMII - bridge */ -#define SDR0_PFC1_SELECT_CONFIG_6 0x00800000 /* 2xSMII using ZMII - bridge */ - -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req - Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) - Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) - Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject - Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject - Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject - Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 - /* PLB3/PLB4 Perf. Monitor En. Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 - /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 - /* PLB3 Performance Monitor Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation - Gated In */ - - /* Ethernet PLL Configuration Register */ -#define SDR0_PFC2 0x4102 -#define SDR0_PFC2_TUNE_MASK 0x01FF8000 /* Loop stability tuning bits */ -#define SDR0_PFC2_MULTI_MASK 0x00007C00 /* Frequency multiplication - selector */ -#define SDR0_PFC2_RANGEB_MASK 0x00000380 /* PLLOUTB/C frequency selector */ -#define SDR0_PFC2_RANGEA_MASK 0x00000071 /* PLLOUTA frequency selector */ - -#define SDR0_PFC2_SELECT_MASK 0xE0000000 /* Ethernet Pin select EMAC1 */ -#define SDR0_PFC2_SELECT_CONFIG_1_1 0x60000000 /* 1xMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_1_2 0x00000000 /* 1xMII using ZMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_2 0x60000000 /* 1xGMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_3 0x80000000 /* 1xTBI using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_4 0xA0000000 /* 2xRGMII using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_5 0xC0000000 /* 2xRTBI using RGMII bridge */ -#define SDR0_PFC2_SELECT_CONFIG_6 0x40000000 /* 2xSMII using ZMII bridge */ - -#define SDR0_PFC4 0x4104 - - /* USB2PHY0 Control Register */ -#define SDR0_USB2PHY0CR 0x4103 -#define SDR0_USB2PHY0CR_UTMICN_MASK 0x00100000 - - /* PHY UTMI interface connection */ -#define SDR0_USB2PHY0CR_UTMICN_DEV 0x00000000 /* Device support */ -#define SDR0_USB2PHY0CR_UTMICN_HOST 0x00100000 /* Host support */ - -#define SDR0_USB2PHY0CR_DWNSTR_MASK 0x00400000 /* Select downstream port mode */ -#define SDR0_USB2PHY0CR_DWNSTR_DEV 0x00000000 /* Device */ -#define SDR0_USB2PHY0CR_DWNSTR_HOST 0x00400000 /* Host */ - -#define SDR0_USB2PHY0CR_DVBUS_MASK 0x00800000 - /* VBus detect (Device mode only) */ -#define SDR0_USB2PHY0CR_DVBUS_PURDIS 0x00000000 - /* Pull-up resistance on D+ is disabled */ -#define SDR0_USB2PHY0CR_DVBUS_PUREN 0x00800000 - /* Pull-up resistance on D+ is enabled */ - -#define SDR0_USB2PHY0CR_WDINT_MASK 0x01000000 - /* PHY UTMI data width and clock select */ -#define SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ 0x00000000 /* 8-bit data/60MHz */ -#define SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ 0x01000000 /* 16-bit data/30MHz */ - -#define SDR0_USB2PHY0CR_LOOPEN_MASK 0x02000000 /* Loop back test enable */ -#define SDR0_USB2PHY0CR_LOOP_ENABLE 0x00000000 /* Loop back disabled */ -#define SDR0_USB2PHY0CR_LOOP_DISABLE 0x02000000 - /* Loop back enabled (only test purposes) */ - -#define SDR0_USB2PHY0CR_XOON_MASK 0x04000000 - /* Force XO block on during a suspend */ -#define SDR0_USB2PHY0CR_XO_ON 0x00000000 /* PHY XO block is powered-on */ -#define SDR0_USB2PHY0CR_XO_OFF 0x04000000 - /* PHY XO block is powered-off when all ports are suspended */ - -#define SDR0_USB2PHY0CR_PWRSAV_MASK 0x08000000 /* Select PHY power-save mode */ -#define SDR0_USB2PHY0CR_PWRSAV_OFF 0x00000000 /* Non-power-save mode */ -#define SDR0_USB2PHY0CR_PWRSAV_ON 0x08000000 /* Power-save mode. Valid only - for full-speed operation */ - -#define SDR0_USB2PHY0CR_XOREF_MASK 0x10000000 /* Select reference clock - source */ -#define SDR0_USB2PHY0CR_XOREF_INTERNAL 0x00000000 /* PHY PLL uses chip internal - 48M clock as a reference */ -#define SDR0_USB2PHY0CR_XOREF_XO 0x10000000 /* PHY PLL uses internal XO - block output as a reference */ - -#define SDR0_USB2PHY0CR_XOCLK_MASK 0x20000000 /* Select clock for XO - block*/ -#define SDR0_USB2PHY0CR_XOCLK_EXTERNAL 0x00000000 /* PHY macro used an external - clock */ -#define SDR0_USB2PHY0CR_XOCLK_CRYSTAL 0x20000000 /* PHY macro uses the clock - from a crystal */ - -#define SDR0_USB2PHY0CR_CLKSEL_MASK 0xc0000000 /* Select ref clk freq */ -#define SDR0_USB2PHY0CR_CLKSEL_12MHZ 0x00000000 /* Select ref clk freq - = 12 MHz */ -#define SDR0_USB2PHY0CR_CLKSEL_48MHZ 0x40000000 /* Select ref clk freq - = 48 MHz */ -#define SDR0_USB2PHY0CR_CLKSEL_24MHZ 0x80000000 /* Select ref clk freq - = 24 MHz */ - - /* Miscealleneaous Function Reg. */ -#define SDR0_MFR 0x4300 -#define SDR0_MFR_ETH0_CLK_SEL_MASK 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH0_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ETH1_CLK_SEL_MASK 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL_EXT 0x00000000 -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ZM_ENCODE(n) ((((unsigned long)(n))&0x3)<<24) -#define SDR0_MFR_ZM_DECODE(n) ((((unsigned long)(n))<<24)&0x3) - -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#define SDR0_MFR_PKT_REJ_MASK 0x00180000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00180000 /* Pkt Rej. Ena. on both EMAC3 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00100000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00080000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00200000 /* Packet Reject Polarity */ - -#endif /* defined(CONFIG_440EPX) || defined(CONFIG_440GRX) */ - - /* CUST1 Customer Configuration Register1 */ -#define SDR0_CUST1 0x4002 -#define SDR0_CUST1_NDRSC_MASK 0xFFFF0000 /* NDRSC Device Read Count */ -#define SDR0_CUST1_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFFF)<<16) -#define SDR0_CUST1_NDRSC_DECODE(n) ((((unsigned long)(n))>>16)&0xFFFF) - - /* Pin Function Control Register 0 */ -#define SDR0_PFC0 0x4100 -#define SDR0_PFC0_CPU_TR_EN_MASK 0x00000100 /* CPU Trace Enable Mask */ -#define SDR0_PFC0_CPU_TRACE_EN 0x00000100 /* CPU Trace Enable */ -#define SDR0_PFC0_CPU_TRACE_DIS 0x00000100 /* CPU Trace Disable */ -#define SDR0_PFC0_CTE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) -#define SDR0_PFC0_CTE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) - - /* Pin Function Control Register 1 */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins */ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins */ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ -#define SDR0_PFC1_UES_MASK 0x00010000 /* USB2D_RX_Active / EBC_Hold Req - Selection */ -#define SDR0_PFC1_UES_USB2D_SEL 0x00000000 /* USB2D_RX_Active Selected */ -#define SDR0_PFC1_UES_EBCHR_SEL 0x00010000 /* EBC_Hold Req Selected */ -#define SDR0_PFC1_DIS_MASK 0x00008000 /* DMA_Req(1) / UIC_IRQ(5) - Selection */ -#define SDR0_PFC1_DIS_DMAR_SEL 0x00000000 /* DMA_Req(1) Selected */ -#define SDR0_PFC1_DIS_UICIRQ5_SEL 0x00008000 /* UIC_IRQ(5) Selected */ -#define SDR0_PFC1_ERE_MASK 0x00004000 /* EBC Mast.Ext.Req.En./GPIO0(27) - Selection */ -#define SDR0_PFC1_ERE_EXTR_SEL 0x00000000 /* EBC Mast.Ext.Req.En. Selected */ -#define SDR0_PFC1_ERE_GPIO0_27_SEL 0x00004000 /* GPIO0(27) Selected */ -#define SDR0_PFC1_UPR_MASK 0x00002000 /* USB2 Device Packet Reject - Selection */ -#define SDR0_PFC1_UPR_DISABLE 0x00000000 /* USB2 Device Packet Reject - Disable */ -#define SDR0_PFC1_UPR_ENABLE 0x00002000 /* USB2 Device Packet Reject - Enable */ - -#define SDR0_PFC1_PLB_PME_MASK 0x00001000 /* PLB3/PLB4 Perf. Monitor En. - Selection */ -#define SDR0_PFC1_PLB_PME_PLB3_SEL 0x00000000 /* PLB3 Performance Monitor - Enable */ -#define SDR0_PFC1_PLB_PME_PLB4_SEL 0x00001000 /* PLB3 Performance Monitor - Enable */ -#define SDR0_PFC1_GFGGI_MASK 0x0000000F /* GPT Frequency Generation - Gated In */ - -#endif /* 440EP || 440GR || 440EPX || 440GRX */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) - /* CUST0 Customer Configuration Register0 */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_MUX_E_N_G_MASK 0xC0000000 /* Mux_Emac_NDFC_GPIO */ -#define SDR0_CUST0_MUX_EMAC_SEL 0x40000000 /* Emac Selection */ -#define SDR0_CUST0_MUX_NDFC_SEL 0x80000000 /* NDFC Selection */ -#define SDR0_CUST0_MUX_GPIO_SEL 0xC0000000 /* GPIO Selection */ - -#define SDR0_CUST0_NDFC_EN_MASK 0x20000000 /* NDFC Enable Mask */ -#define SDR0_CUST0_NDFC_ENABLE 0x20000000 /* NDFC Enable */ -#define SDR0_CUST0_NDFC_DISABLE 0x00000000 /* NDFC Disable */ - -#define SDR0_CUST0_NDFC_BW_MASK 0x10000000 /* NDFC Boot Width */ -#define SDR0_CUST0_NDFC_BW_16_BIT 0x10000000 /* NDFC Boot Width = 16 Bit */ -#define SDR0_CUST0_NDFC_BW_8_BIT 0x00000000 /* NDFC Boot Width = 8 Bit */ - -#define SDR0_CUST0_NDFC_BP_MASK 0x0F000000 /* NDFC Boot Page */ -#define SDR0_CUST0_NDFC_BP_ENCODE(n) ((((unsigned long)(n))&0xF)<<24) -#define SDR0_CUST0_NDFC_BP_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) - -#define SDR0_CUST0_NDFC_BAC_MASK 0x00C00000 /* NDFC Boot Address Cycle */ -#define SDR0_CUST0_NDFC_BAC_ENCODE(n) ((((unsigned long)(n))&0x3)<<22) -#define SDR0_CUST0_NDFC_BAC_DECODE(n) ((((unsigned long)(n))>>22)&0x03) - -#define SDR0_CUST0_NDFC_ARE_MASK 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_ENABLE 0x00200000 /* NDFC Auto Read Enable */ -#define SDR0_CUST0_NDFC_ARE_DISABLE 0x00000000 /* NDFC Auto Read Disable */ - -#define SDR0_CUST0_NRB_MASK 0x00100000 /* NDFC Ready / Busy */ -#define SDR0_CUST0_NRB_BUSY 0x00100000 /* Busy */ -#define SDR0_CUST0_NRB_READY 0x00000000 /* Ready */ - -#define SDR0_CUST0_NDRSC_MASK 0x0000FFF0 /* NDFC Device Reset Count Mask */ -#define SDR0_CUST0_NDRSC_ENCODE(n) ((((unsigned long)(n))&0xFFF)<<4) -#define SDR0_CUST0_NDRSC_DECODE(n) ((((unsigned long)(n))>>4)&0xFFF) - -#define SDR0_CUST0_CHIPSELGAT_MASK 0x0000000F /* Chip Select Gating Mask */ -#define SDR0_CUST0_CHIPSELGAT_DIS 0x00000000 /* Chip Select Gating Disable */ -#define SDR0_CUST0_CHIPSELGAT_ENALL 0x0000000F /*All Chip Select Gating Enable*/ -#define SDR0_CUST0_CHIPSELGAT_EN0 0x00000008 /* Chip Select0 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN1 0x00000004 /* Chip Select1 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN2 0x00000002 /* Chip Select2 Gating Enable */ -#define SDR0_CUST0_CHIPSELGAT_EN3 0x00000001 /* Chip Select3 Gating Enable */ -#endif - -/*----------------------------------------------------------------------------- - | On-Chip Buses - +----------------------------------------------------------------------------*/ -/* TODO: as needed */ - -/*----------------------------------------------------------------------------- - | Clocking, Power Management and Chip Control - +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define CNTRL_DCR_BASE 0x160 -#else -#define CNTRL_DCR_BASE 0x0b0 -#endif - -#define CPC0_SYS0 (CNTRL_DCR_BASE+0x30) /* System configuration reg 0 */ -#define CPC0_SYS1 (CNTRL_DCR_BASE+0x31) /* System configuration reg 1 */ - -#define CPC0_STRP0 (CNTRL_DCR_BASE+0x34) /* Power-on config reg 0 (RO) */ -#define CPC0_STRP1 (CNTRL_DCR_BASE+0x35) /* Power-on config reg 1 (RO) */ - -#define CPC0_GPIO (CNTRL_DCR_BASE+0x38) /* GPIO config reg (440GP) */ - -#define CPC0_CR0 (CNTRL_DCR_BASE+0x3b) /* Control 0 register */ -#define CPC0_CR1 (CNTRL_DCR_BASE+0x3a) /* Control 1 register */ - -/*----------------------------------------------------------------------------- - | DMA - +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define DMA_DCR_BASE 0x200 -#else -#define DMA_DCR_BASE 0x100 -#endif -#define DMACR0 (DMA_DCR_BASE+0x00) /* DMA channel control register 0 */ -#define DMACT0 (DMA_DCR_BASE+0x01) /* DMA count register 0 */ -#define DMACR1 (DMA_DCR_BASE+0x08) /* DMA channel control register 1 */ -#define DMACT1 (DMA_DCR_BASE+0x09) /* DMA count register 1 */ -#define DMACR2 (DMA_DCR_BASE+0x10) /* DMA channel control register 2 */ -#define DMACT2 (DMA_DCR_BASE+0x11) /* DMA count register 2 */ -#define DMACR3 (DMA_DCR_BASE+0x18) /* DMA channel control register 2 */ -#define DMASR (DMA_DCR_BASE+0x20) /* DMA status register */ -#define DMASGC (DMA_DCR_BASE+0x23) /* DMA scatter/gather command register */ - -/*----------------------------------------------------------------------------- - | Memory Access Layer - +----------------------------------------------------------------------------*/ -#define MAL_DCR_BASE 0x180 -#define MAL0_CFG (MAL_DCR_BASE + 0x00) /* MAL Config reg */ -#define MAL0_ESR (MAL_DCR_BASE + 0x01) /* Error Status (Read/Clear) */ -#define MAL0_IER (MAL_DCR_BASE + 0x02) /* Interrupt enable */ -#define MAL0_TXCASR (MAL_DCR_BASE + 0x04) /* TX Channel active (set) */ -#define MAL0_TXCARR (MAL_DCR_BASE + 0x05) /* TX Channel active (reset) */ -#define MAL0_TXEOBISR (MAL_DCR_BASE + 0x06) /* TX End of buffer int status*/ -#define MAL0_TXDEIR (MAL_DCR_BASE + 0x07) /* TX Descr. Error Int */ -#define MAL0_TXBADDR (MAL_DCR_BASE + 0x09) /* TX descriptor base addr*/ -#define MAL0_RXCASR (MAL_DCR_BASE + 0x10) /* RX Channel active (set) */ -#define MAL0_RXCARR (MAL_DCR_BASE + 0x11) /* RX Channel active (reset) */ -#define MAL0_RXEOBISR (MAL_DCR_BASE + 0x12) /* RX End of buffer int status*/ -#define MAL0_RXDEIR (MAL_DCR_BASE + 0x13) /* RX Descr. Error Int */ -#define MAL0_RXBADDR (MAL_DCR_BASE + 0x15) /* RX descriptor base addr */ -#define MAL0_TXCTP0R (MAL_DCR_BASE + 0x20) /* TX 0 Channel table pointer */ -#define MAL0_TXCTP1R (MAL_DCR_BASE + 0x21) /* TX 1 Channel table pointer */ -#define MAL0_TXCTP2R (MAL_DCR_BASE + 0x22) /* TX 2 Channel table pointer */ -#define MAL0_TXCTP3R (MAL_DCR_BASE + 0x23) /* TX 3 Channel table pointer */ -#define MAL0_RXCTP0R (MAL_DCR_BASE + 0x40) /* RX 0 Channel table pointer */ -#define MAL0_RXCTP1R (MAL_DCR_BASE + 0x41) /* RX 1 Channel table pointer */ -#define MAL0_RCBS0 (MAL_DCR_BASE + 0x60) /* RX 0 Channel buffer size */ -#define MAL0_RCBS1 (MAL_DCR_BASE + 0x61) /* RX 1 Channel buffer size */ -#if defined(CONFIG_440GX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define MAL0_RXCTP2R (MAL_DCR_BASE + 0x42) /* RX 2 Channel table pointer */ -#define MAL0_RXCTP3R (MAL_DCR_BASE + 0x43) /* RX 3 Channel table pointer */ -#define MAL0_RXCTP8R (MAL_DCR_BASE + 0x48) /* RX 8 Channel table pointer */ -#define MAL0_RXCTP16R (MAL_DCR_BASE + 0x50) /* RX 16 Channel table pointer*/ -#define MAL0_RXCTP24R (MAL_DCR_BASE + 0x58) /* RX 24 Channel table pointer*/ -#define MAL0_RCBS2 (MAL_DCR_BASE + 0x62) /* RX 2 Channel buffer size */ -#define MAL0_RCBS3 (MAL_DCR_BASE + 0x63) /* RX 3 Channel buffer size */ -#define MAL0_RCBS8 (MAL_DCR_BASE + 0x68) /* RX 8 Channel buffer size */ -#define MAL0_RCBS16 (MAL_DCR_BASE + 0x70) /* RX 16 Channel buffer size */ -#define MAL0_RCBS24 (MAL_DCR_BASE + 0x78) /* RX 24 Channel buffer size */ -#endif /* CONFIG_440GX */ - -/*-----------------------------------------------------------------------------+ -| SDR0 Bit Settings -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_440SP) -#define SDR0_DDR0 0x00E1 -#define SDR0_DDR0_DPLLRST 0x80000000 -#define SDR0_DDR0_DDRM_MASK 0x60000000 -#define SDR0_DDR0_DDRM_DDR1 0x20000000 -#define SDR0_DDR0_DDRM_DDR2 0x40000000 -#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) -#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) -#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) -#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) -#endif - -#if defined(CONFIG_440SPE) || defined(CONFIG_460SX) -#define SDR0_CP440 0x0180 -#define SDR0_CP440_ERPN_MASK 0x30000000 -#define SDR0_CP440_ERPN_MASK_HI 0x3000 -#define SDR0_CP440_ERPN_MASK_LO 0x0000 -#define SDR0_CP440_ERPN_EBC 0x10000000 -#define SDR0_CP440_ERPN_EBC_HI 0x1000 -#define SDR0_CP440_ERPN_EBC_LO 0x0000 -#define SDR0_CP440_ERPN_PCI 0x20000000 -#define SDR0_CP440_ERPN_PCI_HI 0x2000 -#define SDR0_CP440_ERPN_PCI_LO 0x0000 -#define SDR0_CP440_ERPN_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) -#define SDR0_CP440_ERPN_DECODE(n) ((((unsigned long)(n))>>28)&0x03) -#define SDR0_CP440_NTO1_MASK 0x00000002 -#define SDR0_CP440_NTO1_NTOP 0x00000000 -#define SDR0_CP440_NTO1_NTO1 0x00000002 -#define SDR0_CP440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) -#define SDR0_CP440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) - -#define SDR0_SDSTP0 0x0020 -#define SDR0_SDSTP0_ENG_MASK 0x80000000 -#define SDR0_SDSTP0_ENG_PLLDIS 0x00000000 -#define SDR0_SDSTP0_ENG_PLLENAB 0x80000000 -#define SDR0_SDSTP0_ENG_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_SDSTP0_ENG_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_SDSTP0_SRC_MASK 0x40000000 -#define SDR0_SDSTP0_SRC_PLLOUTA 0x00000000 -#define SDR0_SDSTP0_SRC_PLLOUTB 0x40000000 -#define SDR0_SDSTP0_SRC_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_SDSTP0_SRC_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_SDSTP0_SEL_MASK 0x38000000 -#define SDR0_SDSTP0_SEL_PLLOUT 0x00000000 -#define SDR0_SDSTP0_SEL_CPU 0x08000000 -#define SDR0_SDSTP0_SEL_EBC 0x28000000 -#define SDR0_SDSTP0_SEL_ENCODE(n) ((((unsigned long)(n))&0x07)<<27) -#define SDR0_SDSTP0_SEL_DECODE(n) ((((unsigned long)(n))>>27)&0x07) -#define SDR0_SDSTP0_TUNE_MASK 0x07FE0000 -#define SDR0_SDSTP0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3FF)<<17) -#define SDR0_SDSTP0_TUNE_DECODE(n) ((((unsigned long)(n))>>17)&0x3FF) -#define SDR0_SDSTP0_FBDV_MASK 0x0001F000 -#define SDR0_SDSTP0_FBDV_ENCODE(n) ((((unsigned long)(n))&0x1F)<<12) -#define SDR0_SDSTP0_FBDV_DECODE(n) ((((((unsigned long)(n))>>12)-1)&0x1F)+1) -#define SDR0_SDSTP0_FWDVA_MASK 0x00000F00 -#define SDR0_SDSTP0_FWDVA_ENCODE(n) ((((unsigned long)(n))&0x0F)<<8) -#define SDR0_SDSTP0_FWDVA_DECODE(n) ((((((unsigned long)(n))>>8)-1)&0x0F)+1) -#define SDR0_SDSTP0_FWDVB_MASK 0x000000E0 -#define SDR0_SDSTP0_FWDVB_ENCODE(n) ((((unsigned long)(n))&0x07)<<5) -#define SDR0_SDSTP0_FWDVB_DECODE(n) ((((((unsigned long)(n))>>5)-1)&0x07)+1) -#define SDR0_SDSTP0_PRBDV0_MASK 0x0000001C -#define SDR0_SDSTP0_PRBDV0_ENCODE(n) ((((unsigned long)(n))&0x07)<<2) -#define SDR0_SDSTP0_PRBDV0_DECODE(n) ((((((unsigned long)(n))>>2)-1)&0x07)+1) -#define SDR0_SDSTP0_OPBDV0_MASK 0x00000003 -#define SDR0_SDSTP0_OPBDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<0) -#define SDR0_SDSTP0_OPBDV0_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0x03)+1) - - -#define SDR0_SDSTP1 0x0021 -#define SDR0_SDSTP1_LFBDV_MASK 0xFC000000 -#define SDR0_SDSTP1_LFBDV_ENCODE(n) ((((unsigned long)(n))&0x3F)<<26) -#define SDR0_SDSTP1_LFBDV_DECODE(n) ((((unsigned long)(n))>>26)&0x3F) -#define SDR0_SDSTP1_PERDV0_MASK 0x03000000 -#define SDR0_SDSTP1_PERDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<24) -#define SDR0_SDSTP1_PERDV0_DECODE(n) ((((unsigned long)(n))>>24)&0x03) -#define SDR0_SDSTP1_MALDV0_MASK 0x00C00000 -#define SDR0_SDSTP1_MALDV0_ENCODE(n) ((((unsigned long)(n))&0x03)<<22) -#define SDR0_SDSTP1_MALDV0_DECODE(n) ((((unsigned long)(n))>>22)&0x03) -#define SDR0_SDSTP1_DDR_MODE_MASK 0x00300000 -#define SDR0_SDSTP1_DDR1_MODE 0x00100000 -#define SDR0_SDSTP1_DDR2_MODE 0x00200000 -#define SDR0_SDSTP1_DDR_ENCODE(n) ((((unsigned long)(n))&0x03)<<20) -#define SDR0_SDSTP1_DDR_DECODE(n) ((((unsigned long)(n))>>20)&0x03) -#define SDR0_SDSTP1_ERPN_MASK 0x00080000 -#define SDR0_SDSTP1_ERPN_EBC 0x00000000 -#define SDR0_SDSTP1_ERPN_PCI 0x00080000 -#define SDR0_SDSTP1_PAE_MASK 0x00040000 -#define SDR0_SDSTP1_PAE_DISABLE 0x00000000 -#define SDR0_SDSTP1_PAE_ENABLE 0x00040000 -#define SDR0_SDSTP1_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) -#define SDR0_SDSTP1_PAE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) -#define SDR0_SDSTP1_PHCE_MASK 0x00020000 -#define SDR0_SDSTP1_PHCE_DISABLE 0x00000000 -#define SDR0_SDSTP1_PHCE_ENABLE 0x00020000 -#define SDR0_SDSTP1_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) -#define SDR0_SDSTP1_PHCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) -#define SDR0_SDSTP1_PISE_MASK 0x00010000 -#define SDR0_SDSTP1_PISE_DISABLE 0x00000000 -#define SDR0_SDSTP1_PISE_ENABLE 0x00001000 -#define SDR0_SDSTP1_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) -#define SDR0_SDSTP1_PISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) -#define SDR0_SDSTP1_PCWE_MASK 0x00008000 -#define SDR0_SDSTP1_PCWE_DISABLE 0x00000000 -#define SDR0_SDSTP1_PCWE_ENABLE 0x00008000 -#define SDR0_SDSTP1_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) -#define SDR0_SDSTP1_PCWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) -#define SDR0_SDSTP1_PPIM_MASK 0x00007800 -#define SDR0_SDSTP1_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) -#define SDR0_SDSTP1_PPIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) -#define SDR0_SDSTP1_PR64E_MASK 0x00000400 -#define SDR0_SDSTP1_PR64E_DISABLE 0x00000000 -#define SDR0_SDSTP1_PR64E_ENABLE 0x00000400 -#define SDR0_SDSTP1_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<10) -#define SDR0_SDSTP1_PR64E_DECODE(n) ((((unsigned long)(n))>>10)&0x01) -#define SDR0_SDSTP1_PXFS_MASK 0x00000300 -#define SDR0_SDSTP1_PXFS_100_133 0x00000000 -#define SDR0_SDSTP1_PXFS_66_100 0x00000100 -#define SDR0_SDSTP1_PXFS_50_66 0x00000200 -#define SDR0_SDSTP1_PXFS_0_50 0x00000300 -#define SDR0_SDSTP1_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define SDR0_SDSTP1_PXFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) -#define SDR0_SDSTP1_EBCW_MASK 0x00000080 /* SOP */ -#define SDR0_SDSTP1_EBCW_8_BITS 0x00000000 /* SOP */ -#define SDR0_SDSTP1_EBCW_16_BITS 0x00000080 /* SOP */ -#define SDR0_SDSTP1_DBGEN_MASK 0x00000030 /* $218C */ -#define SDR0_SDSTP1_DBGEN_FUNC 0x00000000 -#define SDR0_SDSTP1_DBGEN_TRACE 0x00000010 -#define SDR0_SDSTP1_DBGEN_ENCODE(n) ((((unsigned long)(n))&0x03)<<4) /* $218C */ -#define SDR0_SDSTP1_DBGEN_DECODE(n) ((((unsigned long)(n))>>4)&0x03) /* $218C */ -#define SDR0_SDSTP1_ETH_MASK 0x00000004 -#define SDR0_SDSTP1_ETH_10_100 0x00000000 -#define SDR0_SDSTP1_ETH_GIGA 0x00000004 -#define SDR0_SDSTP1_ETH_ENCODE(n) ((((unsigned long)(n))&0x01)<<2) -#define SDR0_SDSTP1_ETH_DECODE(n) ((((unsigned long)(n))>>2)&0x01) -#define SDR0_SDSTP1_NTO1_MASK 0x00000001 -#define SDR0_SDSTP1_NTO1_DISABLE 0x00000000 -#define SDR0_SDSTP1_NTO1_ENABLE 0x00000001 -#define SDR0_SDSTP1_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<0) -#define SDR0_SDSTP1_NTO1_DECODE(n) ((((unsigned long)(n))>>0)&0x01) - -#define SDR0_SDSTP2 0x0022 -#define SDR0_SDSTP2_P1AE_MASK 0x80000000 -#define SDR0_SDSTP2_P1AE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P1AE_ENABLE 0x80000000 -#define SDR0_SDSTP2_P1AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_SDSTP2_P1AE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_SDSTP2_P1HCE_MASK 0x40000000 -#define SDR0_SDSTP2_P1HCE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P1HCE_ENABLE 0x40000000 -#define SDR0_SDSTP2_P1HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_SDSTP2_P1HCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_SDSTP2_P1ISE_MASK 0x20000000 -#define SDR0_SDSTP2_P1ISE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P1ISE_ENABLE 0x20000000 -#define SDR0_SDSTP2_P1ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define SDR0_SDSTP2_P1ISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define SDR0_SDSTP2_P1CWE_MASK 0x10000000 -#define SDR0_SDSTP2_P1CWE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P1CWE_ENABLE 0x10000000 -#define SDR0_SDSTP2_P1CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) -#define SDR0_SDSTP2_P1CWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) -#define SDR0_SDSTP2_P1PIM_MASK 0x0F000000 -#define SDR0_SDSTP2_P1PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) -#define SDR0_SDSTP2_P1PIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#define SDR0_SDSTP2_P1R64E_MASK 0x00800000 -#define SDR0_SDSTP2_P1R64E_DISABLE 0x00000000 -#define SDR0_SDSTP2_P1R64E_ENABLE 0x00800000 -#define SDR0_SDSTP2_P1R64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) -#define SDR0_SDSTP2_P1R64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) -#define SDR0_SDSTP2_P1XFS_MASK 0x00600000 -#define SDR0_SDSTP2_P1XFS_100_133 0x00000000 -#define SDR0_SDSTP2_P1XFS_66_100 0x00200000 -#define SDR0_SDSTP2_P1XFS_50_66 0x00400000 -#define SDR0_SDSTP2_P1XFS_0_50 0x00600000 -#define SDR0_SDSTP2_P1XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) -#define SDR0_SDSTP2_P1XFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) -#define SDR0_SDSTP2_P2AE_MASK 0x00040000 -#define SDR0_SDSTP2_P2AE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P2AE_ENABLE 0x00040000 -#define SDR0_SDSTP2_P2AE_ENCODE(n) ((((unsigned long)(n))&0x01)<<18) -#define SDR0_SDSTP2_P2AE_DECODE(n) ((((unsigned long)(n))>>18)&0x01) -#define SDR0_SDSTP2_P2HCE_MASK 0x00020000 -#define SDR0_SDSTP2_P2HCE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P2HCE_ENABLE 0x00020000 -#define SDR0_SDSTP2_P2HCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<17) -#define SDR0_SDSTP2_P2HCE_DECODE(n) ((((unsigned long)(n))>>17)&0x01) -#define SDR0_SDSTP2_P2ISE_MASK 0x00010000 -#define SDR0_SDSTP2_P2ISE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P2ISE_ENABLE 0x00010000 -#define SDR0_SDSTP2_P2ISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<16) -#define SDR0_SDSTP2_P2ISE_DECODE(n) ((((unsigned long)(n))>>16)&0x01) -#define SDR0_SDSTP2_P2CWE_MASK 0x00008000 -#define SDR0_SDSTP2_P2CWE_DISABLE 0x00000000 -#define SDR0_SDSTP2_P2CWE_ENABLE 0x00008000 -#define SDR0_SDSTP2_P2CWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<15) -#define SDR0_SDSTP2_P2CWE_DECODE(n) ((((unsigned long)(n))>>15)&0x01) -#define SDR0_SDSTP2_P2PIM_MASK 0x00007800 -#define SDR0_SDSTP2_P2PIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<11) -#define SDR0_SDSTP2_P2PIM_DECODE(n) ((((unsigned long)(n))>>11)&0x0F) -#define SDR0_SDSTP2_P2XFS_MASK 0x00000300 -#define SDR0_SDSTP2_P2XFS_100_133 0x00000000 -#define SDR0_SDSTP2_P2XFS_66_100 0x00000100 -#define SDR0_SDSTP2_P2XFS_50_66 0x00000200 -#define SDR0_SDSTP2_P2XFS_0_50 0x00000100 -#define SDR0_SDSTP2_P2XFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<8) -#define SDR0_SDSTP2_P2XFS_DECODE(n) ((((unsigned long)(n))>>8)&0x03) - -#define SDR0_SDSTP3 0x0023 - -#define SDR0_PINSTP 0x0040 -#define SDR0_PINSTP_BOOTSTRAP_MASK 0xC0000000 /* Strap Bits */ -#define SDR0_PINSTP_BOOTSTRAP_SETTINGS0 0x00000000 /* Default strap settings 0 - (EBC boot) */ -#define SDR0_PINSTP_BOOTSTRAP_SETTINGS1 0x40000000 /* Default strap settings 1 - (PCI boot) */ -#define SDR0_PINSTP_BOOTSTRAP_IIC_54_EN 0x80000000 /* Serial Device Enabled - - Addr = 0x54 */ -#define SDR0_PINSTP_BOOTSTRAP_IIC_50_EN 0xC0000000 /* Serial Device Enabled - - Addr = 0x50 */ -#define SDR0_SDCS 0x0060 -#define SDR0_ECID0 0x0080 -#define SDR0_ECID1 0x0081 -#define SDR0_ECID2 0x0082 -#define SDR0_JTAG 0x00C0 - -#define SDR0_DDR0 0x00E1 -#define SDR0_DDR0_DPLLRST 0x80000000 -#define SDR0_DDR0_DDRM_MASK 0x60000000 -#define SDR0_DDR0_DDRM_DDR1 0x20000000 -#define SDR0_DDR0_DDRM_DDR2 0x40000000 -#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) -#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) -#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) -#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) - -#define SDR0_UART0 0x0120 -#define SDR0_UART1 0x0121 -#define SDR0_UART2 0x0122 -#define SDR0_SLPIPE 0x0220 - -#define SDR0_AMP0 0x0240 -#define SDR0_AMP0_PRIORITY 0xFFFF0000 -#define SDR0_AMP0_ALTERNATE_PRIORITY 0x0000FF00 -#define SDR0_AMP0_RESERVED_BITS_MASK 0x000000FF - -#define SDR0_AMP1 0x0241 -#define SDR0_AMP1_PRIORITY 0xFC000000 -#define SDR0_AMP1_ALTERNATE_PRIORITY 0x0000E000 -#define SDR0_AMP1_RESERVED_BITS_MASK 0x03FF1FFF - -#define SDR0_MIRQ0 0x0260 -#define SDR0_MIRQ1 0x0261 -#define SDR0_MALTBL 0x0280 -#define SDR0_MALRBL 0x02A0 -#define SDR0_MALTBS 0x02C0 -#define SDR0_MALRBS 0x02E0 - -/* Reserved for Customer Use */ -#define SDR0_CUST0 0x4000 -#define SDR0_CUST0_AUTONEG_MASK 0x8000000 -#define SDR0_CUST0_NO_AUTONEG 0x0000000 -#define SDR0_CUST0_AUTONEG 0x8000000 -#define SDR0_CUST0_ETH_FORCE_MASK 0x6000000 -#define SDR0_CUST0_ETH_FORCE_10MHZ 0x0000000 -#define SDR0_CUST0_ETH_FORCE_100MHZ 0x2000000 -#define SDR0_CUST0_ETH_FORCE_1000MHZ 0x4000000 -#define SDR0_CUST0_ETH_DUPLEX_MASK 0x1000000 -#define SDR0_CUST0_ETH_HALF_DUPLEX 0x0000000 -#define SDR0_CUST0_ETH_FULL_DUPLEX 0x1000000 - -#define SDR0_SDSTP4 0x4001 -#define SDR0_CUST1 0x4002 -#define SDR0_SDSTP5 0x4003 -#define SDR0_CUST2 0x4004 -#define SDR0_SDSTP6 0x4005 -#define SDR0_CUST3 0x4006 -#define SDR0_SDSTP7 0x4007 - -#define SDR0_PFC0 0x4100 -#define SDR0_PFC0_GPIO_0 0x80000000 -#define SDR0_PFC0_PCIX0REQ2_N 0x00000000 -#define SDR0_PFC0_GPIO_1 0x40000000 -#define SDR0_PFC0_PCIX0REQ3_N 0x00000000 -#define SDR0_PFC0_GPIO_2 0x20000000 -#define SDR0_PFC0_PCIX0GNT2_N 0x00000000 -#define SDR0_PFC0_GPIO_3 0x10000000 -#define SDR0_PFC0_PCIX0GNT3_N 0x00000000 -#define SDR0_PFC0_GPIO_4 0x08000000 -#define SDR0_PFC0_PCIX1REQ2_N 0x00000000 -#define SDR0_PFC0_GPIO_5 0x04000000 -#define SDR0_PFC0_PCIX1REQ3_N 0x00000000 -#define SDR0_PFC0_GPIO_6 0x02000000 -#define SDR0_PFC0_PCIX1GNT2_N 0x00000000 -#define SDR0_PFC0_GPIO_7 0x01000000 -#define SDR0_PFC0_PCIX1GNT3_N 0x00000000 -#define SDR0_PFC0_GPIO_8 0x00800000 -#define SDR0_PFC0_PERREADY 0x00000000 -#define SDR0_PFC0_GPIO_9 0x00400000 -#define SDR0_PFC0_PERCS1_N 0x00000000 -#define SDR0_PFC0_GPIO_10 0x00200000 -#define SDR0_PFC0_PERCS2_N 0x00000000 -#define SDR0_PFC0_GPIO_11 0x00100000 -#define SDR0_PFC0_IRQ0 0x00000000 -#define SDR0_PFC0_GPIO_12 0x00080000 -#define SDR0_PFC0_IRQ1 0x00000000 -#define SDR0_PFC0_GPIO_13 0x00040000 -#define SDR0_PFC0_IRQ2 0x00000000 -#define SDR0_PFC0_GPIO_14 0x00020000 -#define SDR0_PFC0_IRQ3 0x00000000 -#define SDR0_PFC0_GPIO_15 0x00010000 -#define SDR0_PFC0_IRQ4 0x00000000 -#define SDR0_PFC0_GPIO_16 0x00008000 -#define SDR0_PFC0_IRQ5 0x00000000 -#define SDR0_PFC0_GPIO_17 0x00004000 -#define SDR0_PFC0_PERBE0_N 0x00000000 -#define SDR0_PFC0_GPIO_18 0x00002000 -#define SDR0_PFC0_PCI0GNT0_N 0x00000000 -#define SDR0_PFC0_GPIO_19 0x00001000 -#define SDR0_PFC0_PCI0GNT1_N 0x00000000 -#define SDR0_PFC0_GPIO_20 0x00000800 -#define SDR0_PFC0_PCI0REQ0_N 0x00000000 -#define SDR0_PFC0_GPIO_21 0x00000400 -#define SDR0_PFC0_PCI0REQ1_N 0x00000000 -#define SDR0_PFC0_GPIO_22 0x00000200 -#define SDR0_PFC0_PCI1GNT0_N 0x00000000 -#define SDR0_PFC0_GPIO_23 0x00000100 -#define SDR0_PFC0_PCI1GNT1_N 0x00000000 -#define SDR0_PFC0_GPIO_24 0x00000080 -#define SDR0_PFC0_PCI1REQ0_N 0x00000000 -#define SDR0_PFC0_GPIO_25 0x00000040 -#define SDR0_PFC0_PCI1REQ1_N 0x00000000 -#define SDR0_PFC0_GPIO_26 0x00000020 -#define SDR0_PFC0_PCI2GNT0_N 0x00000000 -#define SDR0_PFC0_GPIO_27 0x00000010 -#define SDR0_PFC0_PCI2GNT1_N 0x00000000 -#define SDR0_PFC0_GPIO_28 0x00000008 -#define SDR0_PFC0_PCI2REQ0_N 0x00000000 -#define SDR0_PFC0_GPIO_29 0x00000004 -#define SDR0_PFC0_PCI2REQ1_N 0x00000000 -#define SDR0_PFC0_GPIO_30 0x00000002 -#define SDR0_PFC0_UART1RX 0x00000000 -#define SDR0_PFC0_GPIO_31 0x00000001 -#define SDR0_PFC0_UART1TX 0x00000000 - -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_UART1_CTS_RTS_MASK 0x02000000 -#define SDR0_PFC1_UART1_DSR_DTR 0x00000000 -#define SDR0_PFC1_UART1_CTS_RTS 0x02000000 -#define SDR0_PFC1_UART2_IN_SERVICE_MASK 0x01000000 -#define SDR0_PFC1_UART2_NOT_IN_SERVICE 0x00000000 -#define SDR0_PFC1_UART2_IN_SERVICE 0x01000000 -#define SDR0_PFC1_ETH_GIGA_MASK 0x00200000 -#define SDR0_PFC1_ETH_10_100 0x00000000 -#define SDR0_PFC1_ETH_GIGA 0x00200000 -#define SDR0_PFC1_ETH_GIGA_ENCODE(n) ((((unsigned long)(n))&0x1)<<21) -#define SDR0_PFC1_ETH_GIGA_DECODE(n) ((((unsigned long)(n))>>21)&0x01) -#define SDR0_PFC1_CPU_TRACE_MASK 0x00180000 /* $218C */ -#define SDR0_PFC1_CPU_NO_TRACE 0x00000000 -#define SDR0_PFC1_CPU_TRACE 0x00080000 -#define SDR0_PFC1_CPU_TRACE_ENCODE(n) ((((unsigned long)(n))&0x3)<<19) - /* $218C */ -#define SDR0_PFC1_CPU_TRACE_DECODE(n) ((((unsigned long)(n))>>19)&0x03) - /* $218C */ - -#define SDR0_MFR 0x4300 -#endif /* CONFIG_440SPE */ - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -/* Pin Function Control Register 0 (SDR0_PFC0) */ -#define SDR0_PFC0 0x4100 -#define SDR0_PFC0_DBG 0x00008000 /* debug enable */ -#define SDR0_PFC0_G49E 0x00004000 /* GPIO 49 enable */ -#define SDR0_PFC0_G50E 0x00002000 /* GPIO 50 enable */ -#define SDR0_PFC0_G51E 0x00001000 /* GPIO 51 enable */ -#define SDR0_PFC0_G52E 0x00000800 /* GPIO 52 enable */ -#define SDR0_PFC0_G53E 0x00000400 /* GPIO 53 enable */ -#define SDR0_PFC0_G54E 0x00000200 /* GPIO 54 enable */ -#define SDR0_PFC0_G55E 0x00000100 /* GPIO 55 enable */ -#define SDR0_PFC0_G56E 0x00000080 /* GPIO 56 enable */ -#define SDR0_PFC0_G57E 0x00000040 /* GPIO 57 enable */ -#define SDR0_PFC0_G58E 0x00000020 /* GPIO 58 enable */ -#define SDR0_PFC0_G59E 0x00000010 /* GPIO 59 enable */ -#define SDR0_PFC0_G60E 0x00000008 /* GPIO 60 enable */ -#define SDR0_PFC0_G61E 0x00000004 /* GPIO 61 enable */ -#define SDR0_PFC0_G62E 0x00000002 /* GPIO 62 enable */ -#define SDR0_PFC0_G63E 0x00000001 /* GPIO 63 enable */ - -/* Pin Function Control Register 1 (SDR0_PFC1) */ -#define SDR0_PFC1 0x4101 -#define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ -#define SDR0_PFC1_U1ME_DSR_DTR 0x00000000 /* UART1 in DSR/DTR Mode */ -#define SDR0_PFC1_U1ME_CTS_RTS 0x02000000 /* UART1 in CTS/RTS Mode */ -#define SDR0_PFC1_U0ME_MASK 0x00080000 /* UART0 Mode Enable */ -#define SDR0_PFC1_U0ME_DSR_DTR 0x00000000 /* UART0 in DSR/DTR Mode */ -#define SDR0_PFC1_U0ME_CTS_RTS 0x00080000 /* UART0 in CTS/RTS Mode */ -#define SDR0_PFC1_U0IM_MASK 0x00040000 /* UART0 Interface Mode */ -#define SDR0_PFC1_U0IM_8PINS 0x00000000 /* UART0 Interface Mode 8 pins*/ -#define SDR0_PFC1_U0IM_4PINS 0x00040000 /* UART0 Interface Mode 4 pins*/ -#define SDR0_PFC1_SIS_MASK 0x00020000 /* SCP or IIC1 Selection */ -#define SDR0_PFC1_SIS_SCP_SEL 0x00000000 /* SCP Selected */ -#define SDR0_PFC1_SIS_IIC1_SEL 0x00020000 /* IIC1 Selected */ - -#define SDR0_ECID0 0x0080 -#define SDR0_ECID1 0x0081 -#define SDR0_ECID2 0x0082 -#define SDR0_ECID3 0x0083 - -/* Ethernet PLL Configuration Register (SDR0_ETH_PLL) */ -#define SDR0_ETH_PLL 0x4102 -#define SDR0_ETH_PLL_PLLLOCK 0x80000000 /*Ethernet PLL lock indication*/ -#define SDR0_ETH_PLL_REF_CLK_SEL 0x10000000 /* Ethernet reference clock */ -#define SDR0_ETH_PLL_BYPASS 0x08000000 /* bypass mode enable */ -#define SDR0_ETH_PLL_STOPCLK 0x04000000 /* output clock disable */ -#define SDR0_ETH_PLL_TUNE_MASK 0x03FF0000 /* loop stability tuning bits */ -#define SDR0_ETH_PLL_TUNE_ENCODE(n) ((((unsigned long)(n))&0x3ff)<<16) -#define SDR0_ETH_PLL_MULTI_MASK 0x0000FF00 /* frequency multiplication */ -#define SDR0_ETH_PLL_MULTI_ENCODE(n) ((((unsigned long)(n))&0xff)<<8) -#define SDR0_ETH_PLL_RANGEB_MASK 0x000000F0 /* PLLOUTB/C frequency */ -#define SDR0_ETH_PLL_RANGEB_ENCODE(n) ((((unsigned long)(n))&0x0f)<<4) -#define SDR0_ETH_PLL_RANGEA_MASK 0x0000000F /* PLLOUTA frequency */ -#define SDR0_ETH_PLL_RANGEA_ENCODE(n) (((unsigned long)(n))&0x0f) - -/* Ethernet Configuration Register (SDR0_ETH_CFG) */ -#define SDR0_ETH_CFG 0x4103 -#define SDR0_ETH_CFG_SGMII3_LPBK 0x00800000 /*SGMII3 port loopback - enable */ -#define SDR0_ETH_CFG_SGMII2_LPBK 0x00400000 /*SGMII2 port loopback - enable */ -#define SDR0_ETH_CFG_SGMII1_LPBK 0x00200000 /*SGMII1 port loopback - enable */ -#define SDR0_ETH_CFG_SGMII0_LPBK 0x00100000 /*SGMII0 port loopback - enable */ -#define SDR0_ETH_CFG_SGMII_MASK 0x00070000 /*SGMII Mask */ -#define SDR0_ETH_CFG_SGMII2_ENABLE 0x00040000 /*SGMII2 port enable */ -#define SDR0_ETH_CFG_SGMII1_ENABLE 0x00020000 /*SGMII1 port enable */ -#define SDR0_ETH_CFG_SGMII0_ENABLE 0x00010000 /*SGMII0 port enable */ -#define SDR0_ETH_CFG_TAHOE1_BYPASS 0x00002000 /*TAHOE1 Bypass selector */ -#define SDR0_ETH_CFG_TAHOE0_BYPASS 0x00001000 /*TAHOE0 Bypass selector */ -#define SDR0_ETH_CFG_EMAC3_PHY_CLK_SEL 0x00000800 /*EMAC 3 PHY clock selector*/ -#define SDR0_ETH_CFG_EMAC2_PHY_CLK_SEL 0x00000400 /*EMAC 2 PHY clock selector*/ -#define SDR0_ETH_CFG_EMAC1_PHY_CLK_SEL 0x00000200 /*EMAC 1 PHY clock selector*/ -#define SDR0_ETH_CFG_EMAC0_PHY_CLK_SEL 0x00000100 /*EMAC 0 PHY clock selector*/ -#define SDR0_ETH_CFG_EMAC_2_1_SWAP 0x00000080 /*Swap EMAC2 with EMAC1 */ -#define SDR0_ETH_CFG_EMAC_0_3_SWAP 0x00000040 /*Swap EMAC0 with EMAC3 */ -#define SDR0_ETH_CFG_MDIO_SEL_MASK 0x00000030 /*MDIO source selector mask*/ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC0 0x00000000 /*MDIO source - EMAC0 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC1 0x00000010 /*MDIO source - EMAC1 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC2 0x00000020 /*MDIO source - EMAC2 */ -#define SDR0_ETH_CFG_MDIO_SEL_EMAC3 0x00000030 /*MDIO source - EMAC3 */ -#define SDR0_ETH_CFG_ZMII_MODE_MASK 0x0000000C /*ZMII bridge mode selector - mask */ -#define SDR0_ETH_CFG_ZMII_SEL_MII 0x00000000 /*ZMII bridge mode - MII */ -#define SDR0_ETH_CFG_ZMII_SEL_SMII 0x00000004 /*ZMII bridge mode - SMII */ -#define SDR0_ETH_CFG_ZMII_SEL_RMII_10 0x00000008 /*ZMII bridge mode - RMII - (10 Mbps) */ -#define SDR0_ETH_CFG_ZMII_SEL_RMII_100 0x0000000C /*ZMII bridge mode - RMII - (100 Mbps) */ -#define SDR0_ETH_CFG_GMC1_BRIDGE_SEL 0x00000002 /*GMC Port 1 bridge - selector */ -#define SDR0_ETH_CFG_GMC0_BRIDGE_SEL 0x00000001 /*GMC Port 0 bridge - selector */ - -#define SDR0_ETH_CFG_ZMII_MODE_SHIFT 4 -#define SDR0_ETH_CFG_ZMII_MII_MODE 0x00 -#define SDR0_ETH_CFG_ZMII_SMII_MODE 0x01 -#define SDR0_ETH_CFG_ZMII_RMII_MODE_10M 0x10 -#define SDR0_ETH_CFG_ZMII_RMII_MODE_100M 0x11 - -/* Ethernet Status Register */ -#define SDR0_ETH_STS 0x4104 - -/* Miscealleneaous Function Reg. (SDR0_MFR) */ -#define SDR0_MFR 0x4300 -#define SDR0_MFR_T0TxFL 0x00800000 /* force parity error TAHOE0 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_T0TxFH 0x00400000 /* force parity error TAHOE0 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_T1TxFL 0x00200000 /* force parity error TAHOE1 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_T1TxFH 0x00100000 /* force parity error TAHOE1 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_E0TxFL 0x00008000 /* force parity error EMAC0 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_E0TxFH 0x00004000 /* force parity error EMAC0 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_E0RxFL 0x00002000 /* force parity error EMAC0 Rx - FIFO bits 0:63 */ -#define SDR0_MFR_E0RxFH 0x00001000 /* force parity error EMAC0 Rx - FIFO bits 64:127 */ -#define SDR0_MFR_E1TxFL 0x00000800 /* force parity error EMAC1 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_E1TxFH 0x00000400 /* force parity error EMAC1 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_E1RxFL 0x00000200 /* force parity error EMAC1 Rx - FIFO bits 0:63 */ -#define SDR0_MFR_E1RxFH 0x00000100 /* force parity error EMAC1 Rx - FIFO bits 64:127 */ -#define SDR0_MFR_E2TxFL 0x00000080 /* force parity error EMAC2 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_E2TxFH 0x00000040 /* force parity error EMAC2 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_E2RxFL 0x00000020 /* force parity error EMAC2 Rx - FIFO bits 0:63 */ -#define SDR0_MFR_E2RxFH 0x00000010 /* force parity error EMAC2 Rx - FIFO bits 64:127 */ -#define SDR0_MFR_E3TxFL 0x00000008 /* force parity error EMAC3 Tx - FIFO bits 0:63 */ -#define SDR0_MFR_E3TxFH 0x00000004 /* force parity error EMAC3 Tx - FIFO bits 64:127 */ -#define SDR0_MFR_E3RxFL 0x00000002 /* force parity error EMAC3 Rx - FIFO bits 0:63 */ -#define SDR0_MFR_E3RxFH 0x00000001 /* force parity error EMAC3 Rx - FIFO bits 64:127 */ - -/* EMACx TX Status Register (SDR0_EMACxTXST)*/ -#define SDR0_EMAC0TXST 0x4400 -#define SDR0_EMAC1TXST 0x4401 -#define SDR0_EMAC2TXST 0x4402 -#define SDR0_EMAC3TXST 0x4403 - -#define SDR0_EMACxTXST_FUR 0x02000000 /*TX FIFO underrun */ -#define SDR0_EMACxTXST_BC 0x01000000 /*broadcase address */ -#define SDR0_EMACxTXST_MC 0x00800000 /*multicast address */ -#define SDR0_EMACxTXST_UC 0x00400000 /*unicast address */ -#define SDR0_EMACxTXST_FP 0x00200000 /*frame paused by control packet */ -#define SDR0_EMACxTXST_BFCS 0x00100000 /*bad FCS in the transmitted frame */ -#define SDR0_EMACxTXST_CPF 0x00080000 /*TX control pause frame */ -#define SDR0_EMACxTXST_CF 0x00040000 /*TX control frame */ -#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ -#define SDR0_EMACxTXST_1023 0x00010000 /*512-1023 bytes transmitted */ -#define SDR0_EMACxTXST_511 0x00008000 /*256-511 bytes transmitted */ -#define SDR0_EMACxTXST_255 0x00004000 /*128-255 bytes transmitted */ -#define SDR0_EMACxTXST_127 0x00002000 /*65-127 bytes transmitted */ -#define SDR0_EMACxTXST_64 0x00001000 /*64 bytes transmitted */ -#define SDR0_EMACxTXST_SQE 0x00000800 /*SQE indication */ -#define SDR0_EMACxTXST_LOC 0x00000400 /*loss of carrier sense */ -#define SDR0_EMACxTXST_IERR 0x00000080 /*EMAC internal error */ -#define SDR0_EMACxTXST_EDF 0x00000040 /*excessive deferral */ -#define SDR0_EMACxTXST_ECOL 0x00000020 /*excessive collisions */ -#define SDR0_EMACxTXST_LCOL 0x00000010 /*late collision */ -#define SDR0_EMACxTXST_DFFR 0x00000008 /*deferred frame */ -#define SDR0_EMACxTXST_MCOL 0x00000004 /*multiple collision frame */ -#define SDR0_EMACxTXST_SCOL 0x00000002 /*single collision frame */ -#define SDR0_EMACxTXST_TXOK 0x00000001 /*transmit OK */ - -/* EMACx RX Status Register (SDR0_EMACxRXST)*/ -#define SDR0_EMAC0RXST 0x4404 -#define SDR0_EMAC1RXST 0x4405 -#define SDR0_EMAC2RXST 0x4406 -#define SDR0_EMAC3RXST 0x4407 - -#define SDR0_EMACxRXST_FOR 0x20000000 /* RX FIFO overrun */ -#define SDR0_EMACxRXST_BC 0x10000000 /* broadcast address */ -#define SDR0_EMACxRXST_MC 0x08000000 /* multicast address */ -#define SDR0_EMACxRXST_UC 0x04000000 /* unicast address */ -#define SDR0_EMACxRXST_UPR_MASK 0x03800000 /* user priority field */ -#define SDR0_EMACxRXST_UPR_ENCODE(n) ((((unsigned long)(n))&0x07)<<23) -#define SDR0_EMACxRXST_VLAN 0x00400000 /* RX VLAN tagged frame */ -#define SDR0_EMACxRXST_LOOP 0x00200000 /* received in loop-back mode */ -#define SDR0_EMACxRXST_UOP 0x00100000 /* RX unsupported opcode */ -#define SDR0_EMACxRXST_CPF 0x00080000 /* RX control pause frame */ -#define SDR0_EMACxRXST_CF 0x00040000 /* RX control frame*/ -#define SDR0_EMACxRXST_MSIZ 0x00020000 /* 1024-MaxSize bytes recieved*/ -#define SDR0_EMACxRXST_1023 0x00010000 /* 512-1023 bytes received */ -#define SDR0_EMACxRXST_511 0x00008000 /* 128-511 bytes received */ -#define SDR0_EMACxRXST_255 0x00004000 /* 128-255 bytes received */ -#define SDR0_EMACxRXST_127 0x00002000 /* 65-127 bytes received */ -#define SDR0_EMACxRXST_64 0x00001000 /* 64 bytes received */ -#define SDR0_EMACxRXST_RUNT 0x00000800 /* runt frame */ -#define SDR0_EMACxRXST_SEVT 0x00000400 /* short event */ -#define SDR0_EMACxRXST_AERR 0x00000200 /* alignment error */ -#define SDR0_EMACxRXST_SERR 0x00000100 /* received with symbol error */ -#define SDR0_EMACxRXST_BURST 0x00000040 /* received burst */ -#define SDR0_EMACxRXST_F2L 0x00000020 /* frame is to long */ -#define SDR0_EMACxRXST_OERR 0x00000010 /* out of range length error */ -#define SDR0_EMACxRXST_IERR 0x00000008 /* in range length error */ -#define SDR0_EMACxRXST_LOST 0x00000004 /* frame lost due to internal - EMAC receive error */ -#define SDR0_EMACxRXST_BFCS 0x00000002 /* bad FCS in the recieved frame */ -#define SDR0_EMACxRXST_RXOK 0x00000001 /* Recieve OK */ - -/* EMACx TX Status Register (SDR0_EMACxREJCNT)*/ -#define SDR0_EMAC0REJCNT 0x4408 -#define SDR0_EMAC1REJCNT 0x4409 -#define SDR0_EMAC2REJCNT 0x440A -#define SDR0_EMAC3REJCNT 0x440B - -#define SDR0_DDR0 0x00E1 -#define SDR0_DDR0_DPLLRST 0x80000000 -#define SDR0_DDR0_DDRM_MASK 0x60000000 -#define SDR0_DDR0_DDRM_DDR1 0x20000000 -#define SDR0_DDR0_DDRM_DDR2 0x40000000 -#define SDR0_DDR0_DDRM_ENCODE(n) ((((unsigned long)(n))&0x03)<<29) -#define SDR0_DDR0_DDRM_DECODE(n) ((((unsigned long)(n))>>29)&0x03) -#define SDR0_DDR0_TUNE_ENCODE(n) ((((unsigned long)(n))&0x2FF)<<0) -#define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) - -#define AHB_TOP 0xA4 -#define AHB_BOT 0xA5 -#define SDR0_AHB_CFG 0x370 -#define SDR0_USB2HOST_CFG 0x371 -#endif /* CONFIG_460EX || CONFIG_460GT */ - -#define SDR0_SDCS_SDD (0x80000000 >> 31) - -#if defined(CONFIG_440GP) -#define CPC0_STRP1_PAE_MASK (0x80000000 >> 11) -#define CPC0_STRP1_PISE_MASK (0x80000000 >> 13) -#endif /* defined(CONFIG_440GP) */ -#if defined(CONFIG_440GX) || defined(CONFIG_440SP) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 13) -#define SDR0_SDSTP1_PISE_MASK (0x80000000 >> 15) -#endif /* defined(CONFIG_440GX) || defined(CONFIG_440SP) */ -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_SDSTP1_PAE_MASK (0x80000000 >> 21) -#define SDR0_SDSTP1_PAME_MASK (0x80000000 >> 27) -#endif /* defined(CONFIG_440EP) || defined(CONFIG_440GR) */ - -#define SDR0_UARTX_UXICS_MASK 0xF0000000 -#define SDR0_UARTX_UXICS_PLB 0x20000000 -#define SDR0_UARTX_UXEC_MASK 0x00800000 -#define SDR0_UARTX_UXEC_INT 0x00000000 -#define SDR0_UARTX_UXEC_EXT 0x00800000 -#define SDR0_UARTX_UXDTE_MASK 0x00400000 -#define SDR0_UARTX_UXDTE_DISABLE 0x00000000 -#define SDR0_UARTX_UXDTE_ENABLE 0x00400000 -#define SDR0_UARTX_UXDRE_MASK 0x00200000 -#define SDR0_UARTX_UXDRE_DISABLE 0x00000000 -#define SDR0_UARTX_UXDRE_ENABLE 0x00200000 -#define SDR0_UARTX_UXDC_MASK 0x00100000 -#define SDR0_UARTX_UXDC_NOTCLEARED 0x00000000 -#define SDR0_UARTX_UXDC_CLEARED 0x00100000 -#define SDR0_UARTX_UXDIV_MASK 0x000000FF -#define SDR0_UARTX_UXDIV_ENCODE(n) ((((unsigned long)(n))&0xFF)<<0) -#define SDR0_UARTX_UXDIV_DECODE(n) ((((((unsigned long)(n))>>0)-1)&0xFF)+1) - -#define SDR0_CPU440_EARV_MASK 0x30000000 -#define SDR0_CPU440_EARV_EBC 0x10000000 -#define SDR0_CPU440_EARV_PCI 0x20000000 -#define SDR0_CPU440_EARV_ENCODE(n) ((((unsigned long)(n))&0x03)<<28) -#define SDR0_CPU440_EARV_DECODE(n) ((((unsigned long)(n))>>28)&0x03) -#define SDR0_CPU440_NTO1_MASK 0x00000002 -#define SDR0_CPU440_NTO1_NTOP 0x00000000 -#define SDR0_CPU440_NTO1_NTO1 0x00000002 -#define SDR0_CPU440_NTO1_ENCODE(n) ((((unsigned long)(n))&0x01)<<1) -#define SDR0_CPU440_NTO1_DECODE(n) ((((unsigned long)(n))>>1)&0x01) - -#define SDR0_XCR_PAE_MASK 0x80000000 -#define SDR0_XCR_PAE_DISABLE 0x00000000 -#define SDR0_XCR_PAE_ENABLE 0x80000000 -#define SDR0_XCR_PAE_ENCODE(n) ((((unsigned long)(n))&0x01)<<31) -#define SDR0_XCR_PAE_DECODE(n) ((((unsigned long)(n))>>31)&0x01) -#define SDR0_XCR_PHCE_MASK 0x40000000 -#define SDR0_XCR_PHCE_DISABLE 0x00000000 -#define SDR0_XCR_PHCE_ENABLE 0x40000000 -#define SDR0_XCR_PHCE_ENCODE(n) ((((unsigned long)(n))&0x01)<<30) -#define SDR0_XCR_PHCE_DECODE(n) ((((unsigned long)(n))>>30)&0x01) -#define SDR0_XCR_PISE_MASK 0x20000000 -#define SDR0_XCR_PISE_DISABLE 0x00000000 -#define SDR0_XCR_PISE_ENABLE 0x20000000 -#define SDR0_XCR_PISE_ENCODE(n) ((((unsigned long)(n))&0x01)<<29) -#define SDR0_XCR_PISE_DECODE(n) ((((unsigned long)(n))>>29)&0x01) -#define SDR0_XCR_PCWE_MASK 0x10000000 -#define SDR0_XCR_PCWE_DISABLE 0x00000000 -#define SDR0_XCR_PCWE_ENABLE 0x10000000 -#define SDR0_XCR_PCWE_ENCODE(n) ((((unsigned long)(n))&0x01)<<28) -#define SDR0_XCR_PCWE_DECODE(n) ((((unsigned long)(n))>>28)&0x01) -#define SDR0_XCR_PPIM_MASK 0x0F000000 -#define SDR0_XCR_PPIM_ENCODE(n) ((((unsigned long)(n))&0x0F)<<24) -#define SDR0_XCR_PPIM_DECODE(n) ((((unsigned long)(n))>>24)&0x0F) -#define SDR0_XCR_PR64E_MASK 0x00800000 -#define SDR0_XCR_PR64E_DISABLE 0x00000000 -#define SDR0_XCR_PR64E_ENABLE 0x00800000 -#define SDR0_XCR_PR64E_ENCODE(n) ((((unsigned long)(n))&0x01)<<23) -#define SDR0_XCR_PR64E_DECODE(n) ((((unsigned long)(n))>>23)&0x01) -#define SDR0_XCR_PXFS_MASK 0x00600000 -#define SDR0_XCR_PXFS_HIGH 0x00000000 -#define SDR0_XCR_PXFS_MED 0x00200000 -#define SDR0_XCR_PXFS_LOW 0x00400000 -#define SDR0_XCR_PXFS_ENCODE(n) ((((unsigned long)(n))&0x03)<<21) -#define SDR0_XCR_PXFS_DECODE(n) ((((unsigned long)(n))>>21)&0x03) -#define SDR0_XCR_PDM_MASK 0x00000040 -#define SDR0_XCR_PDM_MULTIPOINT 0x00000000 -#define SDR0_XCR_PDM_P2P 0x00000040 -#define SDR0_XCR_PDM_ENCODE(n) ((((unsigned long)(n))&0x01)<<19) -#define SDR0_XCR_PDM_DECODE(n) ((((unsigned long)(n))>>19)&0x01) - -#define SDR0_PFC0_UART1_DSR_CTS_EN_MASK 0x00030000 -#define SDR0_PFC0_GEIE_MASK 0x00003E00 -#define SDR0_PFC0_GEIE_TRE 0x00003E00 -#define SDR0_PFC0_GEIE_NOTRE 0x00000000 -#define SDR0_PFC0_TRE_MASK 0x00000100 -#define SDR0_PFC0_TRE_DISABLE 0x00000000 -#define SDR0_PFC0_TRE_ENABLE 0x00000100 -#define SDR0_PFC0_TRE_ENCODE(n) ((((unsigned long)(n))&0x01)<<8) -#define SDR0_PFC0_TRE_DECODE(n) ((((unsigned long)(n))>>8)&0x01) - -#define SDR0_PFC1_UART1_DSR_CTS_MASK 0x02000000 -#define SDR0_PFC1_EPS_MASK 0x01C00000 -#define SDR0_PFC1_EPS_GROUP0 0x00000000 -#define SDR0_PFC1_EPS_GROUP1 0x00400000 -#define SDR0_PFC1_EPS_GROUP2 0x00800000 -#define SDR0_PFC1_EPS_GROUP3 0x00C00000 -#define SDR0_PFC1_EPS_GROUP4 0x01000000 -#define SDR0_PFC1_EPS_GROUP5 0x01400000 -#define SDR0_PFC1_EPS_GROUP6 0x01800000 -#define SDR0_PFC1_EPS_GROUP7 0x01C00000 -#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) -#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) -#define SDR0_PFC1_RMII_MASK 0x00200000 -#define SDR0_PFC1_RMII_100MBIT 0x00000000 -#define SDR0_PFC1_RMII_10MBIT 0x00200000 -#define SDR0_PFC1_RMII_ENCODE(n) ((((unsigned long)(n))&0x01)<<21) -#define SDR0_PFC1_RMII_DECODE(n) ((((unsigned long)(n))>>21)&0x01) -#define SDR0_PFC1_CTEMS_MASK 0x00100000 -#define SDR0_PFC1_CTEMS_EMS 0x00000000 -#define SDR0_PFC1_CTEMS_CPUTRACE 0x00100000 - -#define SDR0_MFR_TAH0_MASK 0x80000000 -#define SDR0_MFR_TAH0_ENABLE 0x00000000 -#define SDR0_MFR_TAH0_DISABLE 0x80000000 -#define SDR0_MFR_TAH1_MASK 0x40000000 -#define SDR0_MFR_TAH1_ENABLE 0x00000000 -#define SDR0_MFR_TAH1_DISABLE 0x40000000 -#define SDR0_MFR_PCM_MASK 0x20000000 -#define SDR0_MFR_PCM_PPC440GX 0x00000000 -#define SDR0_MFR_PCM_PPC440GP 0x20000000 -#define SDR0_MFR_ECS_MASK 0x10000000 -#define SDR0_MFR_ECS_INTERNAL 0x10000000 - -#define SDR0_MFR_ETH0_CLK_SEL 0x08000000 /* Ethernet0 Clock Select */ -#define SDR0_MFR_ETH1_CLK_SEL 0x04000000 /* Ethernet1 Clock Select */ -#define SDR0_MFR_ZMII_MODE_MASK 0x03000000 /* ZMII Mode Mask */ -#define SDR0_MFR_ZMII_MODE_MII 0x00000000 /* ZMII Mode MII */ -#define SDR0_MFR_ZMII_MODE_SMII 0x01000000 /* ZMII Mode SMII */ -#define SDR0_MFR_ZMII_MODE_RMII_10M 0x02000000 /* ZMII Mode RMII - 10 Mbs */ -#define SDR0_MFR_ZMII_MODE_RMII_100M 0x03000000 /* ZMII Mode RMII - 100 Mbs*/ -#define SDR0_MFR_ZMII_MODE_BIT0 0x02000000 /* ZMII Mode Bit0 */ -#define SDR0_MFR_ZMII_MODE_BIT1 0x01000000 /* ZMII Mode Bit1 */ -#define SDR0_MFR_ERRATA3_EN0 0x00800000 -#define SDR0_MFR_ERRATA3_EN1 0x00400000 -#if defined(CONFIG_440GX) /* test-only: only 440GX or 440SPE??? */ -#define SDR0_MFR_PKT_REJ_MASK 0x00300000 /* Pkt Rej. Enable Mask */ -#define SDR0_MFR_PKT_REJ_EN 0x00300000 /* Pkt Rej. Enable on both EMAC3 - 0-1 */ -#define SDR0_MFR_PKT_REJ_EN0 0x00200000 /* Pkt Rej. Enable on EMAC3(0) */ -#define SDR0_MFR_PKT_REJ_EN1 0x00100000 /* Pkt Rej. Enable on EMAC3(1) */ -#define SDR0_MFR_PKT_REJ_POL 0x00080000 /* Packet Reject Polarity */ -#endif - - -#if defined(CONFIG_440EPX) -#define CPM0_ER 0x000000B0 -#define CPM1_ER 0x000000F0 -#define PLB4A0_ACR 0x00000081 -#define PLB4A1_ACR 0x00000089 -#define PLB3A0_ACR 0x00000077 -#define OPB2PLB40_BCTRL 0x00000350 -#define P4P3BO0_CFG 0x00000026 -#define SPI0_MODE 0xEF600090 /* SPI Mode Regsgiter */ - -#endif - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_PFC1_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<22) -#define SDR0_PFC1_EPS_DECODE(n) ((((unsigned long)(n))>>22)&0x07) -#define SDR0_PFC2_EPS_ENCODE(n) ((((unsigned long)(n))&0x07)<<29) -#define SDR0_PFC2_EPS_DECODE(n) ((((unsigned long)(n))>>29)&0x07) -#endif - -#define SDR0_MFR_ECS_MASK 0x10000000 -#define SDR0_MFR_ECS_INTERNAL 0x10000000 - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define SDR0_SRST0 0x200 -#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ -#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ -#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ -#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ -#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ - transmitter 0 */ -#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ - transmitter 1 */ -#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ -#define SDR0_SRST0_USB2H 0x01000000 /* USB2.0 Host */ -#define SDR0_SRST0_GPIO 0x00800000 /* General purpose I/O */ -#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ -#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ -#define SDR0_SRST0_PCI 0x00100000 /* PCI */ -#define SDR0_SRST0_EMAC0 0x00080000 /* Ethernet media access controller 0 */ -#define SDR0_SRST0_EMAC1 0x00040000 /* Ethernet media access controller 1 */ -#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ -#define SDR0_SRST0_ZMII 0x00010000 /* ZMII bridge */ -#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0 */ -#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1 */ -#define SDR0_SRST0_IIC1 0x00002000 /* Inter integrated circuit 1 */ -#define SDR0_SRST0_SCP 0x00001000 /* Serial communications port */ -#define SDR0_SRST0_BGI 0x00000800 /* OPB to PLB bridge */ -#define SDR0_SRST0_DMA 0x00000400 /* Direct memory access controller */ -#define SDR0_SRST0_DMAC 0x00000200 /* DMA channel */ -#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ -#define SDR0_SRST0_USB2D 0x00000080 /* USB2.0 device */ -#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ -#define SDR0_SRST0_P4P3 0x00000010 /* PLB4 to PLB3 bridge */ -#define SDR0_SRST0_P3P4 0x00000008 /* PLB3 to PLB4 bridge */ -#define SDR0_SRST0_PLB3 0x00000004 /* PLB3 arbiter */ -#define SDR0_SRST0_UART2 0x00000002 /* Universal asynchronous receiver/ - transmitter 2 */ -#define SDR0_SRST0_UART3 0x00000001 /* Universal asynchronous receiver/ - transmitter 3 */ - -#define SDR0_SRST1 0x201 -#define SDR0_SRST1_NDFC 0x80000000 /* Nand flash controller */ -#define SDR0_SRST1_OPBA1 0x40000000 /* OPB Arbiter attached to PLB4 */ -#define SDR0_SRST1_P4OPB0 0x20000000 /* PLB4 to OPB Bridge0 */ -#define SDR0_SRST1_PLB42OPB0 SDR0_SRST1_P4OPB0 -#define SDR0_SRST1_DMA4 0x10000000 /* DMA to PLB4 */ -#define SDR0_SRST1_DMA4CH 0x08000000 /* DMA Channel to PLB4 */ -#define SDR0_SRST1_OPBA2 0x04000000 /* OPB Arbiter attached to PLB4 - USB 2.0 Host */ -#define SDR0_SRST1_OPB2PLB40 0x02000000 /* OPB to PLB4 Bridge attached to - USB 2.0 Host */ -#define SDR0_SRST1_PLB42OPB1 0x01000000 /* PLB4 to OPB Bridge attached to - USB 2.0 Host */ -#define SDR0_SRST1_CPM1 0x00800000 /* Clock and Power management 1 */ -#define SDR0_SRST1_UIC2 0x00400000 /* Universal Interrupt Controller 2*/ -#define SDR0_SRST1_CRYP0 0x00200000 /* Security Engine */ -#define SDR0_SRST1_USB20PHY 0x00100000 /* USB 2.0 Phy */ -#define SDR0_SRST1_USB2HUTMI 0x00080000 /* USB 2.0 Host UTMI Interface */ -#define SDR0_SRST1_USB2HPHY 0x00040000 /* USB 2.0 Host Phy Interface */ -#define SDR0_SRST1_SRAM0 0x00020000 /* Internal SRAM Controller */ -#define SDR0_SRST1_RGMII0 0x00010000 /* RGMII Bridge */ -#define SDR0_SRST1_ETHPLL 0x00008000 /* Ethernet PLL */ -#define SDR0_SRST1_FPU 0x00004000 /* Floating Point Unit */ -#define SDR0_SRST1_KASU0 0x00002000 /* Kasumi Engine */ - -#define SDR0_EMAC0RXST 0x00004301 /* */ -#define SDR0_EMAC0TXST 0x00004302 /* */ -#define SDR0_CRYP0 0x00004500 -#define SDR0_EBC0 0x00000100 -#define SDR0_SDSTP2 0x00004001 -#define SDR0_SDSTP3 0x00004001 -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) - -#define SDR0_SRST0 SDR0_SRST /* for compatability reasons */ -#define SDR0_SRST0_BGO 0x80000000 /* PLB to OPB bridge */ -#define SDR0_SRST0_PLB4 0x40000000 /* PLB4 arbiter */ -#define SDR0_SRST0_EBC 0x20000000 /* External bus controller */ -#define SDR0_SRST0_OPB 0x10000000 /* OPB arbiter */ -#define SDR0_SRST0_UART0 0x08000000 /* Universal asynchronous receiver/ - transmitter 0 */ -#define SDR0_SRST0_UART1 0x04000000 /* Universal asynchronous receiver/ - transmitter 1 */ -#define SDR0_SRST0_IIC0 0x02000000 /* Inter integrated circuit 0 */ -#define SDR0_SRST0_IIC1 0x01000000 /* Inter integrated circuit 1 */ -#define SDR0_SRST0_GPIO0 0x00800000 /* General purpose I/O 0 */ -#define SDR0_SRST0_GPT 0x00400000 /* General purpose timer */ -#define SDR0_SRST0_DMC 0x00200000 /* DDR SDRAM memory controller */ -#define SDR0_SRST0_PCI 0x00100000 /* PCI */ -#define SDR0_SRST0_CPM0 0x00020000 /* Clock and power management */ -#define SDR0_SRST0_IMU 0x00010000 /* I2O DMA */ -#define SDR0_SRST0_UIC0 0x00008000 /* Universal interrupt controller 0*/ -#define SDR0_SRST0_UIC1 0x00004000 /* Universal interrupt controller 1*/ -#define SDR0_SRST0_SRAM 0x00002000 /* Universal interrupt controller 0*/ -#define SDR0_SRST0_UIC2 0x00001000 /* Universal interrupt controller 2*/ -#define SDR0_SRST0_UIC3 0x00000800 /* Universal interrupt controller 3*/ -#define SDR0_SRST0_OCM 0x00000400 /* Universal interrupt controller 0*/ -#define SDR0_SRST0_UART2 0x00000200 /* Universal asynchronous receiver/ - transmitter 2 */ -#define SDR0_SRST0_MAL 0x00000100 /* Media access layer */ -#define SDR0_SRST0_GPTR 0x00000040 /* General purpose timer */ -#define SDR0_SRST0_L2CACHE 0x00000004 /* L2 Cache */ -#define SDR0_SRST0_UART3 0x00000002 /* Universal asynchronous receiver/ - transmitter 3 */ -#define SDR0_SRST0_GPIO1 0x00000001 /* General purpose I/O 1 */ - -#define SDR0_SRST1 0x201 -#define SDR0_SRST1_RLL 0x80000000 /* SRIO RLL */ -#define SDR0_SRST1_SCP 0x40000000 /* Serial communications port */ -#define SDR0_SRST1_PLBARB 0x20000000 /* PLB Arbiter */ -#define SDR0_SRST1_EIPPKP 0x10000000 /* EIPPPKP */ -#define SDR0_SRST1_EIP94 0x08000000 /* EIP 94 */ -#define SDR0_SRST1_EMAC0 0x04000000 /* Ethernet media access - controller 0 */ -#define SDR0_SRST1_EMAC1 0x02000000 /* Ethernet media access - controller 1 */ -#define SDR0_SRST1_EMAC2 0x01000000 /* Ethernet media access - controller 2 */ -#define SDR0_SRST1_EMAC3 0x00800000 /* Ethernet media access - controller 3 */ -#define SDR0_SRST1_ZMII 0x00400000 /* Ethernet ZMII/RMII/SMII */ -#define SDR0_SRST1_RGMII0 0x00200000 /* Ethernet RGMII/RTBI 0 */ -#define SDR0_SRST1_RGMII1 0x00100000 /* Ethernet RGMII/RTBI 1 */ -#define SDR0_SRST1_DMA4 0x00080000 /* DMA to PLB4 */ -#define SDR0_SRST1_DMA4CH 0x00040000 /* DMA Channel to PLB4 */ -#define SDR0_SRST1_SATAPHY 0x00020000 /* Serial ATA PHY */ -#define SDR0_SRST1_SRIODEV 0x00010000 /* Serial Rapid IO core, PCS, and - serdes */ -#define SDR0_SRST1_SRIOPCS 0x00008000 /* Serial Rapid IO core and PCS */ -#define SDR0_SRST1_NDFC 0x00004000 /* Nand flash controller */ -#define SDR0_SRST1_SRIOPLB 0x00002000 /* Serial Rapid IO PLB */ -#define SDR0_SRST1_ETHPLL 0x00001000 /* Ethernet PLL */ -#define SDR0_SRST1_TAHOE1 0x00000800 /* Ethernet Tahoe 1 */ -#define SDR0_SRST1_TAHOE0 0x00000400 /* Ethernet Tahoe 0 */ -#define SDR0_SRST1_SGMII0 0x00000200 /* Ethernet SGMII 0 */ -#define SDR0_SRST1_SGMII1 0x00000100 /* Ethernet SGMII 1 */ -#define SDR0_SRST1_SGMII2 0x00000080 /* Ethernet SGMII 2 */ -#define SDR0_SRST1_AHB 0x00000040 /* PLB4XAHB bridge */ -#define SDR0_SRST1_USBOTGPHY 0x00000020 /* USB 2.0 OTG PHY */ -#define SDR0_SRST1_USBOTG 0x00000010 /* USB 2.0 OTG controller */ -#define SDR0_SRST1_USBHOST 0x00000008 /* USB 2.0 Host controller */ -#define SDR0_SRST1_AHBDMAC 0x00000004 /* AHB DMA controller */ -#define SDR0_SRST1_AHBICM 0x00000002 /* AHB inter-connect matrix */ -#define SDR0_SRST1_SATA 0x00000001 /* Serial ATA controller */ - -#else - -#define SDR0_SRST_BGO 0x80000000 -#define SDR0_SRST_PLB 0x40000000 -#define SDR0_SRST_EBC 0x20000000 -#define SDR0_SRST_OPB 0x10000000 -#define SDR0_SRST_UART0 0x08000000 -#define SDR0_SRST_UART1 0x04000000 -#define SDR0_SRST_IIC0 0x02000000 -#define SDR0_SRST_IIC1 0x01000000 -#define SDR0_SRST_GPIO 0x00800000 -#define SDR0_SRST_GPT 0x00400000 -#define SDR0_SRST_DMC 0x00200000 -#define SDR0_SRST_PCI 0x00100000 -#define SDR0_SRST_EMAC0 0x00080000 -#define SDR0_SRST_EMAC1 0x00040000 -#define SDR0_SRST_CPM 0x00020000 -#define SDR0_SRST_IMU 0x00010000 -#define SDR0_SRST_UIC01 0x00008000 -#define SDR0_SRST_UICB2 0x00004000 -#define SDR0_SRST_SRAM 0x00002000 -#define SDR0_SRST_EBM 0x00001000 -#define SDR0_SRST_BGI 0x00000800 -#define SDR0_SRST_DMA 0x00000400 -#define SDR0_SRST_DMAC 0x00000200 -#define SDR0_SRST_MAL 0x00000100 -#define SDR0_SRST_ZMII 0x00000080 -#define SDR0_SRST_GPTR 0x00000040 -#define SDR0_SRST_PPM 0x00000020 -#define SDR0_SRST_EMAC2 0x00000010 -#define SDR0_SRST_EMAC3 0x00000008 -#define SDR0_SRST_RGMII 0x00000001 - -#endif - -/*-----------------------------------------------------------------------------+ -| Clocking -+-----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ -#define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ -#define PLLSYS0_OPB_DIV_MASK 0x0c000000 /* OPB Divisor */ -#define PLLSYS0_PLBEDV0_DIV_MASK 0xe0000000 /* PLB Early Clock Divisor */ -#define PLLSYS0_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS0_SEL_MASK 0x18000000 /* 0 = PLL, 1 = PerClk */ -#elif !defined (CONFIG_440GX) && \ - !defined(CONFIG_440EP) && !defined(CONFIG_440GR) && \ - !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) && \ - !defined(CONFIG_440SP) && !defined(CONFIG_440SPE) -#define PLLSYS0_TUNE_MASK 0xffc00000 /* PLL TUNE bits */ -#define PLLSYS0_FB_DIV_MASK 0x003c0000 /* Feedback divisor */ -#define PLLSYS0_FWD_DIV_A_MASK 0x00038000 /* Forward divisor A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x00007000 /* Forward divisor B */ -#define PLLSYS0_OPB_DIV_MASK 0x00000c00 /* OPB divisor */ -#define PLLSYS0_EPB_DIV_MASK 0x00000300 /* EPB divisor */ -#define PLLSYS0_EXTSL_MASK 0x00000080 /* PerClk feedback path */ -#define PLLSYS0_RW_MASK 0x00000060 /* ROM width */ -#define PLLSYS0_RL_MASK 0x00000010 /* ROM location */ -#define PLLSYS0_ZMII_SEL_MASK 0x0000000c /* ZMII selection */ -#define PLLSYS0_BYPASS_MASK 0x00000002 /* Bypass PLL */ -#define PLLSYS0_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ - -#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ -#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ -#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ -#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ -#else /* !CONFIG_440GX or CONFIG_440EP or CONFIG_440GR */ -#define PLLSYS0_ENG_MASK 0x80000000 /* 0 = SysClk, 1 = PLL VCO */ -#define PLLSYS0_SRC_MASK 0x40000000 /* 0 = PLL A, 1 = PLL B */ -#define PLLSYS0_SEL_MASK 0x38000000 /* 0 = PLL, 1 = CPU, 5 = PerClk */ -#define PLLSYS0_TUNE_MASK 0x07fe0000 /* PLL Tune bits */ -#define PLLSYS0_FB_DIV_MASK 0x0001f000 /* Feedback divisor */ -#define PLLSYS0_FWD_DIV_A_MASK 0x00000f00 /* Fwd Div A */ -#define PLLSYS0_FWD_DIV_B_MASK 0x000000e0 /* Fwd Div B */ -#define PLLSYS0_PRI_DIV_B_MASK 0x0000001c /* PLL Primary Divisor B */ -#define PLLSYS0_OPB_DIV_MASK 0x00000003 /* OPB Divisor */ - -#define PLLC_ENG_MASK 0x20000000 /* PLL primary forward divisor source */ -#define PLLC_SRC_MASK 0x20000000 /* PLL feedback source */ -#define PLLD_FBDV_MASK 0x1f000000 /* PLL Feedback Divisor */ -#define PLLD_FWDVA_MASK 0x000f0000 /* PLL Forward Divisor A */ -#define PLLD_FWDVB_MASK 0x00000700 /* PLL Forward Divisor B */ -#define PLLD_LFBDV_MASK 0x0000003f /* PLL Local Feedback Divisor */ - -#define OPBDDV_MASK 0x03000000 /* OPB Clock Divisor Register */ -#define PERDV_MASK 0x07000000 /* Periferal Clock Divisor */ -#define PRADV_MASK 0x07000000 /* Primary Divisor A */ -#define PRBDV_MASK 0x07000000 /* Primary Divisor B */ -#define SPCID_MASK 0x03000000 /* Sync PCI Divisor */ - -#define PLL_VCO_FREQ_MIN 500 /* Min VCO freq (MHz) */ -#define PLL_VCO_FREQ_MAX 1000 /* Max VCO freq (MHz) */ -#define PLL_CPU_FREQ_MAX 400 /* Max CPU freq (MHz) */ -#define PLL_PLB_FREQ_MAX 133 /* Max PLB freq (MHz) */ - -/* Strap 1 Register */ -#define PLLSYS1_LF_DIV_MASK 0xfc000000 /* PLL Local Feedback Divisor */ -#define PLLSYS1_PERCLK_DIV_MASK 0x03000000 /* Peripheral Clk Divisor */ -#define PLLSYS1_MAL_DIV_MASK 0x00c00000 /* MAL Clk Divisor */ -#define PLLSYS1_RW_MASK 0x00300000 /* ROM width */ -#define PLLSYS1_EAR_MASK 0x00080000 /* ERAP Addres reset vector */ -#define PLLSYS1_PAE_MASK 0x00040000 /* PCI arbitor enable */ -#define PLLSYS1_PCHE_MASK 0x00020000 /* PCI host config enable */ -#define PLLSYS1_PISE_MASK 0x00010000 /* PCI init seq. enable */ -#define PLLSYS1_PCWE_MASK 0x00008000 /* PCI local cpu wait enable */ -#define PLLSYS1_PPIM_MASK 0x00007800 /* PCI inbound map */ -#define PLLSYS1_PR64E_MASK 0x00000400 /* PCI init Req64 enable */ -#define PLLSYS1_PXFS_MASK 0x00000300 /* PCI-X Freq Sel */ -#define PLLSYS1_RSVD_MASK 0x00000080 /* RSVD */ -#define PLLSYS1_PDM_MASK 0x00000040 /* PCI-X Driver Mode */ -#define PLLSYS1_EPS_MASK 0x00000038 /* Ethernet Pin Select */ -#define PLLSYS1_RMII_MASK 0x00000004 /* RMII Mode */ -#define PLLSYS1_TRE_MASK 0x00000002 /* GPIO Trace Enable */ -#define PLLSYS1_NTO1_MASK 0x00000001 /* CPU:PLB N-to-1 ratio */ -#endif /* CONFIG_440GX */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define CPR0_ICFG_RLI_MASK 0x80000000 -#define CPR0_ICFG_ICS_MASK 0x00000007 -#define CPR0_SPCID_SPCIDV0_MASK 0x03000000 -#define CPR0_SPCID_SPCIDV0_DIV1 0x01000000 -#define CPR0_SPCID_SPCIDV0_DIV2 0x02000000 -#define CPR0_SPCID_SPCIDV0_DIV3 0x03000000 -#define CPR0_SPCID_SPCIDV0_DIV4 0x00000000 -#define CPR0_PERD_PERDV0_MASK 0x07000000 -#endif - -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CPR0_ICFG_RLI_MASK 0x80000000 - -#define CPR0_PLLC_RST 0x80000000 -#define CPR0_PLLC_ENG 0x40000000 -#endif - -/*----------------------------------------------------------------------------- -| PCI Internal Registers et. al. (accessed via plb) -+----------------------------------------------------------------------------*/ -#define PCIL0_CFGADR (CONFIG_SYS_PCI_BASE + 0x0ec00000) -#define PCIL0_CFGDATA (CONFIG_SYS_PCI_BASE + 0x0ec00004) -#define PCIL0_CFGBASE (CONFIG_SYS_PCI_BASE + 0x0ec80000) -#define PCIL0_IOBASE (CONFIG_SYS_PCI_BASE + 0x08000000) - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* PCI Local Configuration Registers - --------------------------------- */ -#define PCI_MMIO_LCR_BASE (CONFIG_SYS_PCI_BASE + 0x0f400000) /* Real => - 0x0EF400000 */ - -/* PCI Master Local Configuration Registers */ -#define PCIL0_PMM0LA (PCI_MMIO_LCR_BASE + 0x00) /* PMM0 Local Address */ -#define PCIL0_PMM0MA (PCI_MMIO_LCR_BASE + 0x04) /* PMM0 Mask/Attribute */ -#define PCIL0_PMM0PCILA (PCI_MMIO_LCR_BASE + 0x08) /* PMM0 PCI Low Address */ -#define PCIL0_PMM0PCIHA (PCI_MMIO_LCR_BASE + 0x0C) /* PMM0 PCI High Address */ -#define PCIL0_PMM1LA (PCI_MMIO_LCR_BASE + 0x10) /* PMM1 Local Address */ -#define PCIL0_PMM1MA (PCI_MMIO_LCR_BASE + 0x14) /* PMM1 Mask/Attribute */ -#define PCIL0_PMM1PCILA (PCI_MMIO_LCR_BASE + 0x18) /* PMM1 PCI Low Address */ -#define PCIL0_PMM1PCIHA (PCI_MMIO_LCR_BASE + 0x1C) /* PMM1 PCI High Address */ -#define PCIL0_PMM2LA (PCI_MMIO_LCR_BASE + 0x20) /* PMM2 Local Address */ -#define PCIL0_PMM2MA (PCI_MMIO_LCR_BASE + 0x24) /* PMM2 Mask/Attribute */ -#define PCIL0_PMM2PCILA (PCI_MMIO_LCR_BASE + 0x28) /* PMM2 PCI Low Address */ -#define PCIL0_PMM2PCIHA (PCI_MMIO_LCR_BASE + 0x2C) /* PMM2 PCI High Address */ - -/* PCI Target Local Configuration Registers */ -#define PCIL0_PTM1MS (PCI_MMIO_LCR_BASE + 0x30) /* PTM1 Memory Size/ - Attribute */ -#define PCIL0_PTM1LA (PCI_MMIO_LCR_BASE + 0x34) /* PTM1 Local Addr. Reg */ -#define PCIL0_PTM2MS (PCI_MMIO_LCR_BASE + 0x38) /* PTM2 Memory Size/ - Attribute */ -#define PCIL0_PTM2LA (PCI_MMIO_LCR_BASE + 0x3C) /* PTM2 Local Addr. Reg */ - -#else - -#define PCIL0_VENDID (PCIL0_CFGBASE + PCI_VENDOR_ID ) -#define PCIL0_DEVID (PCIL0_CFGBASE + PCI_DEVICE_ID ) -#define PCIL0_CMD (PCIL0_CFGBASE + PCI_COMMAND ) -#define PCIL0_STATUS (PCIL0_CFGBASE + PCI_STATUS ) -#define PCIL0_REVID (PCIL0_CFGBASE + PCI_REVISION_ID ) -#define PCIL0_CLS (PCIL0_CFGBASE + PCI_CLASS_CODE) -#define PCIL0_CACHELS (PCIL0_CFGBASE + PCI_CACHE_LINE_SIZE ) -#define PCIL0_LATTIM (PCIL0_CFGBASE + PCI_LATENCY_TIMER ) -#define PCIL0_HDTYPE (PCIL0_CFGBASE + PCI_HEADER_TYPE ) -#define PCIL0_BIST (PCIL0_CFGBASE + PCI_BIST ) -#define PCIL0_BAR0 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_0 ) -#define PCIL0_BAR1 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_1 ) -#define PCIL0_BAR2 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_2 ) -#define PCIL0_BAR3 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_3 ) -#define PCIL0_BAR4 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_4 ) -#define PCIL0_BAR5 (PCIL0_CFGBASE + PCI_BASE_ADDRESS_5 ) -#define PCIL0_CISPTR (PCIL0_CFGBASE + PCI_CARDBUS_CIS ) -#define PCIL0_SBSYSVID (PCIL0_CFGBASE + PCI_SUBSYSTEM_VENDOR_ID ) -#define PCIL0_SBSYSID (PCIL0_CFGBASE + PCI_SUBSYSTEM_ID ) -#define PCIL0_EROMBA (PCIL0_CFGBASE + PCI_ROM_ADDRESS ) -#define PCIL0_CAP (PCIL0_CFGBASE + PCI_CAPABILITY_LIST ) -#define PCIL0_RES0 (PCIL0_CFGBASE + 0x0035 ) -#define PCIL0_RES1 (PCIL0_CFGBASE + 0x0036 ) -#define PCIL0_RES2 (PCIL0_CFGBASE + 0x0038 ) -#define PCIL0_INTLN (PCIL0_CFGBASE + PCI_INTERRUPT_LINE ) -#define PCIL0_INTPN (PCIL0_CFGBASE + PCI_INTERRUPT_PIN ) -#define SDR0_EMACxTXST_FUR 0x02000000 /* TX FIFO underrun */ -#define SDR0_EMACxTXST_BC 0x01000000 /* broadcase address */ -#define SDR0_EMACxTXST_MC 0x00800000 /* multicast address */ -#define SDR0_EMACxTXST_UC 0x00400000 /* unicast address */ -#define SDR0_EMACxTXST_FP 0x00200000 /* frame paused by control packet */ -#define SDR0_EMACxTXST_BFCS 0x00100000 /* bad FCS in the transmitted frame*/ -#define SDR0_EMACxTXST_CPF 0x00080000 /* TX control pause frame */ -#define SDR0_EMACxTXST_CF 0x00040000 /* TX control frame */ -#define SDR0_EMACxTXST_MSIZ 0x00020000 /* 1024-maxsize bytes transmitted */ -#define SDR0_EMACxTXST_1023 0x00010000 /* 512-1023 bytes transmitted */ -#define SDR0_EMACxTXST_511 0x00008000 /* 256-511 bytes transmitted */ -#define SDR0_EMACxTXST_255 0x00004000 /* 128-255 bytes transmitted */ -#define SDR0_EMACxTXST_127 0x00002000 /* 65-127 bytes transmitted */ -#define SDR0_EMACxTXST_64 0x00001000 /* 64 bytes transmitted */ -#define SDR0_EMACxTXST_SQE 0x00000800 /* SQE indication */ -#define SDR0_EMACxTXST_LOC 0x00000400 /* loss of carrier sense */ -#define SDR0_EMACxTXST_IERR 0x00000080 /* EMAC internal error */ -#define SDR0_EMACxTXST_EDF 0x00000040 /* excessive deferral */ -#define SDR0_EMACxTXST_ECOL 0x00000020 /* excessive collisions */ -#define SDR0_EMACxTXST_LCOL 0x00000010 /* late collision */ -#define SDR0_EMACxTXST_DFFR 0x00000008 /* deferred frame */ -#define SDR0_EMACxTXST_MCOL 0x00000004 /* multiple collision frame */ -#define SDR0_EMACxTXST_SCOL 0x00000002 /* single collision frame */ -#define SDR0_EMACxTXST_TXOK 0x00000001 /* transmit OK */ - -#define PCIL0_MINGNT (PCIL0_CFGBASE + PCI_MIN_GNT ) -#define PCIL0_MAXLTNCY (PCIL0_CFGBASE + PCI_MAX_LAT ) - -#define PCIL0_BRDGOPT1 (PCIL0_CFGBASE + 0x0040) -#define PCIL0_BRDGOPT2 (PCIL0_CFGBASE + 0x0044) - -#define PCIL0_POM0LAL (PCIL0_CFGBASE + 0x0068) -#define PCIL0_POM0LAH (PCIL0_CFGBASE + 0x006c) -#define PCIL0_POM0SA (PCIL0_CFGBASE + 0x0070) -#define PCIL0_POM0PCIAL (PCIL0_CFGBASE + 0x0074) -#define PCIL0_POM0PCIAH (PCIL0_CFGBASE + 0x0078) -#define PCIL0_POM1LAL (PCIL0_CFGBASE + 0x007c) -#define PCIL0_POM1LAH (PCIL0_CFGBASE + 0x0080) -#define PCIL0_POM1SA (PCIL0_CFGBASE + 0x0084) -#define PCIL0_POM1PCIAL (PCIL0_CFGBASE + 0x0088) -#define PCIL0_POM1PCIAH (PCIL0_CFGBASE + 0x008c) -#define PCIL0_POM2SA (PCIL0_CFGBASE + 0x0090) - -#define PCIL0_PIM0SA (PCIL0_CFGBASE + 0x0098) -#define PCIL0_PIM0LAL (PCIL0_CFGBASE + 0x009c) -#define PCIL0_PIM0LAH (PCIL0_CFGBASE + 0x00a0) -#define PCIL0_PIM1SA (PCIL0_CFGBASE + 0x00a4) -#define PCIL0_PIM1LAL (PCIL0_CFGBASE + 0x00a8) -#define PCIL0_PIM1LAH (PCIL0_CFGBASE + 0x00ac) -#define PCIL0_PIM2SA (PCIL0_CFGBASE + 0x00b0) -#define PCIL0_PIM2LAL (PCIL0_CFGBASE + 0x00b4) -#define PCIL0_PIM2LAH (PCIL0_CFGBASE + 0x00b8) - -#define PCIL0_STS (PCIL0_CFGBASE + 0x00e0) - -#endif /* !defined(CONFIG_440EP) !defined(CONFIG_440GR) */ - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) - -/* USB2.0 Device */ -#define USB2D0_BASE CONFIG_SYS_USB2D0_BASE - -#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) - -#define USB2D0_INTRIN (USB2D0_BASE + 0x00000000) /* Interrupt register for - Endpoint 0 plus IN Endpoints 1 to 3 */ -#define USB2D0_POWER (USB2D0_BASE + 0x00000000) /* Power management - register */ -#define USB2D0_FADDR (USB2D0_BASE + 0x00000000) /* Function address - register */ -#define USB2D0_INTRINE (USB2D0_BASE + 0x00000000) /* Interrupt enable - register for USB2D0_INTRIN */ -#define USB2D0_INTROUT (USB2D0_BASE + 0x00000000) /* Interrupt register for - OUT Endpoints 1 to 3 */ -#define USB2D0_INTRUSBE (USB2D0_BASE + 0x00000000) /* Interrupt enable - register for USB2D0_INTRUSB */ -#define USB2D0_INTRUSB (USB2D0_BASE + 0x00000000) /* Interrupt register for - common USB interrupts */ -#define USB2D0_INTROUTE (USB2D0_BASE + 0x00000000) /* Interrupt enable - register for IntrOut */ -#define USB2D0_TSTMODE (USB2D0_BASE + 0x00000000) /* Enables the USB 2.0 - test modes */ -#define USB2D0_INDEX (USB2D0_BASE + 0x00000000) /* Index register for - selecting the Endpoint status/control registers */ -#define USB2D0_FRAME (USB2D0_BASE + 0x00000000) /* Frame number */ -#define USB2D0_INCSR0 (USB2D0_BASE + 0x00000000) /* Control Status - register for Endpoint 0. (Index register set to select Endpoint 0) */ -#define USB2D0_INCSR (USB2D0_BASE + 0x00000000) /* Control Status - register for IN Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_INMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet - size for IN Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTCSR (USB2D0_BASE + 0x00000000) /* Control Status - register for OUT Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTMAXP (USB2D0_BASE + 0x00000000) /* Maximum packet - size for OUT Endpoint. (Index register set to select Endpoints 13) */ -#define USB2D0_OUTCOUNT0 (USB2D0_BASE + 0x00000000) /* Number of received - bytes in Endpoint 0 FIFO. (Index register set to select Endpoint 0) */ -#define USB2D0_OUTCOUNT (USB2D0_BASE + 0x00000000) /* Number of bytes in - OUT Endpoint FIFO. (Index register set to select Endpoints 13) */ -#endif - -/****************************************************************************** - * GPIO macro register defines - ******************************************************************************/ -#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460SX) -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000700) - -#define GPIO0_OR (GPIO0_BASE+0x0) -#define GPIO0_TCR (GPIO0_BASE+0x4) -#define GPIO0_ODR (GPIO0_BASE+0x18) -#define GPIO0_IR (GPIO0_BASE+0x1C) -#endif /* CONFIG_440GP */ - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define GPIO0_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000B00) -#define GPIO1_BASE (CONFIG_SYS_PERIPHERAL_BASE+0x00000C00) - -#define GPIO0_OR (GPIO0_BASE+0x0) -#define GPIO0_TCR (GPIO0_BASE+0x4) -#define GPIO0_OSRL (GPIO0_BASE+0x8) -#define GPIO0_OSRH (GPIO0_BASE+0xC) -#define GPIO0_TSRL (GPIO0_BASE+0x10) -#define GPIO0_TSRH (GPIO0_BASE+0x14) -#define GPIO0_ODR (GPIO0_BASE+0x18) -#define GPIO0_IR (GPIO0_BASE+0x1C) -#define GPIO0_RR1 (GPIO0_BASE+0x20) -#define GPIO0_RR2 (GPIO0_BASE+0x24) -#define GPIO0_RR3 (GPIO0_BASE+0x28) -#define GPIO0_ISR1L (GPIO0_BASE+0x30) -#define GPIO0_ISR1H (GPIO0_BASE+0x34) -#define GPIO0_ISR2L (GPIO0_BASE+0x38) -#define GPIO0_ISR2H (GPIO0_BASE+0x3C) -#define GPIO0_ISR3L (GPIO0_BASE+0x40) -#define GPIO0_ISR3H (GPIO0_BASE+0x44) - -#define GPIO1_OR (GPIO1_BASE+0x0) -#define GPIO1_TCR (GPIO1_BASE+0x4) -#define GPIO1_OSRL (GPIO1_BASE+0x8) -#define GPIO1_OSRH (GPIO1_BASE+0xC) -#define GPIO1_TSRL (GPIO1_BASE+0x10) -#define GPIO1_TSRH (GPIO1_BASE+0x14) -#define GPIO1_ODR (GPIO1_BASE+0x18) -#define GPIO1_IR (GPIO1_BASE+0x1C) -#define GPIO1_RR1 (GPIO1_BASE+0x20) -#define GPIO1_RR2 (GPIO1_BASE+0x24) -#define GPIO1_RR3 (GPIO1_BASE+0x28) -#define GPIO1_ISR1L (GPIO1_BASE+0x30) -#define GPIO1_ISR1H (GPIO1_BASE+0x34) -#define GPIO1_ISR2L (GPIO1_BASE+0x38) -#define GPIO1_ISR2H (GPIO1_BASE+0x3C) -#define GPIO1_ISR3L (GPIO1_BASE+0x40) -#define GPIO1_ISR3H (GPIO1_BASE+0x44) -#endif - -#ifndef __ASSEMBLY__ - -#endif /* _ASMLANGUAGE */ - -#endif /* __PPC440_H__ */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h deleted file mode 100644 index 5238d04..0000000 --- a/include/ppc4xx.h +++ /dev/null @@ -1,235 +0,0 @@ -/*----------------------------------------------------------------------------+ -| This source code is dual-licensed. You may use it under the terms of -| the GNU General Public License version 2, or under the license below. -| -| This source code has been made available to you by IBM on an AS-IS -| basis. Anyone receiving this source is licensed under IBM -| copyrights to use it in any way he or she deems fit, including -| copying it, modifying it, compiling it, and redistributing it either -| with or without modifications. No license under IBM patents or -| patent applications is to be implied by the copyright license. -| -| Any user of this software should understand that IBM cannot provide -| technical support for this software and will not be responsible for -| any consequences resulting from the use of this software. -| -| Any person who transfers this source code or any derivative work -| must include the IBM copyright notice, this paragraph, and the -| preceding two paragraphs in the transferred software. -| -| COPYRIGHT I B M CORPORATION 1999 -| LICENSED MATERIAL - PROGRAM PROPERTY OF I B M -+----------------------------------------------------------------------------*/ - -#ifndef __PPC4XX_H__ -#define __PPC4XX_H__ - -/* - * Configure which SDRAM/DDR/DDR2 controller is equipped - */ -#if defined(CONFIG_405GP) || defined(CONFIG_405CR) || defined(CONFIG_405EP) || \ - defined(CONFIG_AP1000) || defined(CONFIG_ML2) -#define CONFIG_SDRAM_PPC4xx_IBM_SDRAM /* IBM SDRAM controller */ -#endif - -#if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440GR) -#define CONFIG_SDRAM_PPC4xx_IBM_DDR /* IBM DDR controller */ -#endif - -#if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) -#define CONFIG_SDRAM_PPC4xx_DENALI_DDR2 /* Denali DDR(2) controller */ -#endif - -#if defined(CONFIG_405EX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) -#define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ -#endif - -#if defined(CONFIG_440EP) || defined(CONFIG_440GR) || \ - defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_405EZ) || defined(CONFIG_405EX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) -#define CONFIG_NAND_NDFC -#endif - -/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */ -#if defined(CONFIG_405EX) || \ - defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ - defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ - defined(CONFIG_460SX) - -#define PLB_ARBITER_BASE 0x80 - -#define PLB0_ACR (PLB_ARBITER_BASE + 0x01) -#define PLB0_ACR_PPM_MASK 0xF0000000 -#define PLB0_ACR_PPM_FIXED 0x00000000 -#define PLB0_ACR_PPM_FAIR 0xD0000000 -#define PLB0_ACR_HBU_MASK 0x08000000 -#define PLB0_ACR_HBU_DISABLED 0x00000000 -#define PLB0_ACR_HBU_ENABLED 0x08000000 -#define PLB0_ACR_RDP_MASK 0x06000000 -#define PLB0_ACR_RDP_DISABLED 0x00000000 -#define PLB0_ACR_RDP_2DEEP 0x02000000 -#define PLB0_ACR_RDP_3DEEP 0x04000000 -#define PLB0_ACR_RDP_4DEEP 0x06000000 -#define PLB0_ACR_WRP_MASK 0x01000000 -#define PLB0_ACR_WRP_DISABLED 0x00000000 -#define PLB0_ACR_WRP_2DEEP 0x01000000 - -#define PLB1_ACR (PLB_ARBITER_BASE + 0x09) -#define PLB1_ACR_PPM_MASK 0xF0000000 -#define PLB1_ACR_PPM_FIXED 0x00000000 -#define PLB1_ACR_PPM_FAIR 0xD0000000 -#define PLB1_ACR_HBU_MASK 0x08000000 -#define PLB1_ACR_HBU_DISABLED 0x00000000 -#define PLB1_ACR_HBU_ENABLED 0x08000000 -#define PLB1_ACR_RDP_MASK 0x06000000 -#define PLB1_ACR_RDP_DISABLED 0x00000000 -#define PLB1_ACR_RDP_2DEEP 0x02000000 -#define PLB1_ACR_RDP_3DEEP 0x04000000 -#define PLB1_ACR_RDP_4DEEP 0x06000000 -#define PLB1_ACR_WRP_MASK 0x01000000 -#define PLB1_ACR_WRP_DISABLED 0x00000000 -#define PLB1_ACR_WRP_2DEEP 0x01000000 - -#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ - -/* - * Define ns16550 register offset for all PPC4xx SoC's. Some - * mostly FPGA based PPC4xx implementations use a different - * offset. So let's give them a chance to define their offset - * in the board config header. - */ -#if !defined(CONFIG_SYS_NS16550_REG_SIZE) -#define CONFIG_SYS_NS16550_REG_SIZE 1 -#endif - -#if defined(CONFIG_440) -#include <ppc440.h> -#else -#include <ppc405.h> -#endif - -#include <asm/ppc4xx-sdram.h> -#include <asm/ppc4xx-ebc.h> -#if !defined(CONFIG_XILINX_440) -#include <asm/ppc4xx-uic.h> -#endif - -/* - * Macro for generating register field mnemonics - */ -#define PPC_REG_BITS 32 -#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) - -/* - * Elide casts when assembling register mnemonics - */ -#ifndef __ASSEMBLY__ -#define static_cast(type, val) (type)(val) -#else -#define static_cast(type, val) (val) -#endif - -/* - * Common stuff for 4xx (405 and 440) - */ - -#define EXC_OFF_SYS_RESET 0x0100 /* System reset */ -#define _START_OFFSET (EXC_OFF_SYS_RESET + 0x2000) - -#define RESET_VECTOR 0xfffffffc -#define CACHELINE_MASK (CONFIG_SYS_CACHELINE_SIZE - 1) /* Address mask for - cache line aligned data. */ - -#define CPR0_DCR_BASE 0x0C -#define CPR0_CFGADDR (CPR0_DCR_BASE + 0x0) -#define CPR0_CFGDATA (CPR0_DCR_BASE + 0x1) - -#define SDR_DCR_BASE 0x0E -#define SDR0_CFGADDR (SDR_DCR_BASE + 0x0) -#define SDR0_CFGDATA (SDR_DCR_BASE + 0x1) - -#define SDRAM_DCR_BASE 0x10 -#define SDRAM0_CFGADDR (SDRAM_DCR_BASE + 0x0) -#define SDRAM0_CFGDATA (SDRAM_DCR_BASE + 0x1) - -#define EBC_DCR_BASE 0x12 -#define EBC0_CFGADDR (EBC_DCR_BASE + 0x0) -#define EBC0_CFGDATA (EBC_DCR_BASE + 0x1) - -/* - * Macros for indirect DCR access - */ -#define mtcpr(reg, d) \ - do { mtdcr(CPR0_CFGADDR, reg); mtdcr(CPR0_CFGDATA, d); } while (0) -#define mfcpr(reg, d) \ - do { mtdcr(CPR0_CFGADDR, reg); d = mfdcr(CPR0_CFGDATA); } while (0) - -#define mtebc(reg, d) \ - do { mtdcr(EBC0_CFGADDR, reg); mtdcr(EBC0_CFGDATA, d); } while (0) -#define mfebc(reg, d) \ - do { mtdcr(EBC0_CFGADDR, reg); d = mfdcr(EBC0_CFGDATA); } while (0) - -#define mtsdram(reg, d) \ - do { mtdcr(SDRAM0_CFGADDR, reg); mtdcr(SDRAM0_CFGDATA, d); } while (0) -#define mfsdram(reg, d) \ - do { mtdcr(SDRAM0_CFGADDR, reg); d = mfdcr(SDRAM0_CFGDATA); } while (0) - -#define mtsdr(reg, d) \ - do { mtdcr(SDR0_CFGADDR, reg); mtdcr(SDR0_CFGDATA, d); } while (0) -#define mfsdr(reg, d) \ - do { mtdcr(SDR0_CFGADDR, reg); d = mfdcr(SDR0_CFGDATA); } while (0) - -#ifndef __ASSEMBLY__ - -typedef struct -{ - unsigned long freqDDR; - unsigned long freqEBC; - unsigned long freqOPB; - unsigned long freqPCI; - unsigned long freqPLB; - unsigned long freqTmrClk; - unsigned long freqUART; - unsigned long freqProcessor; - unsigned long freqVCOHz; - unsigned long freqVCOMhz; /* in MHz */ - unsigned long pciClkSync; /* PCI clock is synchronous */ - unsigned long pciIntArbEn; /* Internal PCI arbiter is enabled */ - unsigned long pllExtBusDiv; - unsigned long pllFbkDiv; - unsigned long pllFwdDiv; - unsigned long pllFwdDivA; - unsigned long pllFwdDivB; - unsigned long pllOpbDiv; - unsigned long pllPciDiv; - unsigned long pllPlbDiv; -} PPC4xx_SYS_INFO; - -static inline u32 get_mcsr(void) -{ - u32 val; - - asm volatile("mfspr %0, 0x23c" : "=r" (val) :); - return val; -} - -static inline void set_mcsr(u32 val) -{ - asm volatile("mtspr 0x23c, %0" : "=r" (val) :); -} - -int ppc4xx_pci_sync_clock_config(u32 async); - -#endif /* __ASSEMBLY__ */ - -/* for multi-cpu support */ -#define NA_OR_UNKNOWN_CPU -1 - -#endif /* __PPC4XX_H__ */ diff --git a/include/search.h b/include/search.h new file mode 100644 index 0000000..fccc757 --- /dev/null +++ b/include/search.h @@ -0,0 +1,106 @@ +/* + * Declarations for System V style searching functions. + * Copyright (C) 1995-1999, 2000 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * + * The GNU C Library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * The GNU C Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with the GNU C Library; if not, write to the Free + * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307 USA. + */ + +/* + * Based on code from uClibc-0.9.30.3 + * Extensions for use within U-Boot + * Copyright (C) 2010 Wolfgang Denk <wd@denx.de> + */ + +#ifndef _SEARCH_H +#define _SEARCH_H 1 + +#include <stddef.h> + +#define __set_errno(val) do { errno = val; } while (0) + +/* + * Prototype structure for a linked-list data structure. + * This is the type used by the `insque' and `remque' functions. + */ + +/* For use with hsearch(3). */ +typedef int (*__compar_fn_t) (__const void *, __const void *); +typedef __compar_fn_t comparison_fn_t; + +/* Action which shall be performed in the call the hsearch. */ +typedef enum { + FIND, + ENTER +} ACTION; + +typedef struct entry { + char *key; + char *data; +} ENTRY; + +/* Opaque type for internal use. */ +struct _ENTRY; + +/* + * Family of hash table handling functions. The functions also + * have reentrant counterparts ending with _r. The non-reentrant + * functions all work on a signle internal hashing table. + */ + +/* Data type for reentrant functions. */ +struct hsearch_data { + struct _ENTRY *table; + unsigned int size; + unsigned int filled; +}; + +/* Create a new hashing table which will at most contain NEL elements. */ +extern int hcreate(size_t __nel); +extern int hcreate_r(size_t __nel, struct hsearch_data *__htab); + +/* Destroy current internal hashing table. */ +extern void hdestroy(void); +extern void hdestroy_r(struct hsearch_data *__htab); + +/* + * Search for entry matching ITEM.key in internal hash table. If + * ACTION is `FIND' return found entry or signal error by returning + * NULL. If ACTION is `ENTER' replace existing data (if any) with + * ITEM.data. + * */ +extern ENTRY *hsearch(ENTRY __item, ACTION __action); +extern int hsearch_r(ENTRY __item, ACTION __action, ENTRY ** __retval, + struct hsearch_data *__htab); + +/* Search and delete entry matching ITEM.key in internal hash table. */ +extern int hdelete(const char *__key); +extern int hdelete_r(const char *__key, struct hsearch_data *__htab); + +extern ssize_t hexport(const char __sep, char **__resp, size_t __size); +extern ssize_t hexport_r(struct hsearch_data *__htab, + const char __sep, char **__resp, size_t __size); + +extern int himport(const char *__env, size_t __size, const char __sep, + int __flag); +extern int himport_r(struct hsearch_data *__htab, + const char *__env, size_t __size, const char __sep, + int __flag); + +/* Flags for himport() / himport_r() */ +#define H_NOCLEAR 1 /* do not clear hash table before importing */ + +#endif /* search.h */ diff --git a/include/status_led.h b/include/status_led.h index f213595..b39ca64 100644 --- a/include/status_led.h +++ b/include/status_led.h @@ -43,7 +43,7 @@ void status_led_tick (unsigned long timestamp); void status_led_set (int led, int state); /***** TQM8xxL ********************************************************/ -#if defined(CONFIG_TQM8xxL) && !defined(CONFIG_HMI10) +#if defined(CONFIG_TQM8xxL) # define STATUS_LED_PAR im_cpm.cp_pbpar # define STATUS_LED_DIR im_cpm.cp_pbdir # define STATUS_LED_ODR im_cpm.cp_pbodr @@ -318,21 +318,6 @@ void status_led_set (int led, int state); # define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ -/***** HMI10 **********************************************************/ -#elif defined(CONFIG_HMI10) -# define STATUS_LED_PAR im_ioport.iop_papar -# define STATUS_LED_DIR im_ioport.iop_padir -# define STATUS_LED_ODR im_ioport.iop_paodr -# define STATUS_LED_DAT im_ioport.iop_padat - -# define STATUS_LED_BIT 0x00000001 /* LED is on PA15 */ -# define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) -# define STATUS_LED_STATE STATUS_LED_BLINKING - -# define STATUS_LED_ACTIVE 1 /* LED on for bit == 1 */ - -# define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ - /***** NetPhone ********************************************************/ #elif defined(CONFIG_NETPHONE) || defined(CONFIG_NETTA2) /* XXX empty just to avoid the error */ diff --git a/lib/Makefile b/lib/Makefile index c45f07c..a8de3e1 100644 --- a/lib/Makefile +++ b/lib/Makefile @@ -37,11 +37,14 @@ COBJS-y += crc32.o COBJS-y += ctype.o COBJS-y += display_options.o COBJS-y += div64.o +COBJS-y += errno.o COBJS-$(CONFIG_GZIP) += gunzip.o +COBJS-y += hashtable.o COBJS-$(CONFIG_LMB) += lmb.o COBJS-y += ldiv.o COBJS-$(CONFIG_MD5) += md5.o COBJS-y += net_utils.o +COBJS-y += qsort.o COBJS-$(CONFIG_SHA1) += sha1.o COBJS-$(CONFIG_SHA256) += sha256.o COBJS-y += string.o diff --git a/lib/errno.c b/lib/errno.c new file mode 100644 index 0000000..8330a8f --- /dev/null +++ b/lib/errno.c @@ -0,0 +1 @@ +int errno = 0; diff --git a/lib/hashtable.c b/lib/hashtable.c new file mode 100644 index 0000000..b747f1f --- /dev/null +++ b/lib/hashtable.c @@ -0,0 +1,735 @@ +/* + * This implementation is based on code from uClibc-0.9.30.3 but was + * modified and extended for use within U-Boot. + * + * Copyright (C) 2010 Wolfgang Denk <wd@denx.de> + * + * Original license header: + * + * Copyright (C) 1993, 1995, 1996, 1997, 2002 Free Software Foundation, Inc. + * This file is part of the GNU C Library. + * Contributed by Ulrich Drepper <drepper@gnu.ai.mit.edu>, 1993. + * + * The GNU C Library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * The GNU C Library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with the GNU C Library; if not, write to the Free + * Software Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA + * 02111-1307 USA. + */ + +#include <errno.h> +#include <malloc.h> + +#ifdef USE_HOSTCC /* HOST build */ +# include <string.h> +# include <assert.h> + +# ifndef debug +# ifdef DEBUG +# define debug(fmt,args...) printf(fmt ,##args) +# else +# define debug(fmt,args...) +# endif +# endif +#else /* U-Boot build */ +# include <common.h> +# include <linux/string.h> +#endif + +#ifndef CONFIG_ENV_MAX_ENTRIES /* maximum number of entries */ +#define CONFIG_ENV_MAX_ENTRIES 512 +#endif + +#include "search.h" + +/* + * [Aho,Sethi,Ullman] Compilers: Principles, Techniques and Tools, 1986 + * [Knuth] The Art of Computer Programming, part 3 (6.4) + */ + +/* + * The non-reentrant version use a global space for storing the hash table. + */ +static struct hsearch_data htab; + +/* + * The reentrant version has no static variables to maintain the state. + * Instead the interface of all functions is extended to take an argument + * which describes the current status. + */ +typedef struct _ENTRY { + unsigned int used; + ENTRY entry; +} _ENTRY; + + +/* + * hcreate() + */ + +/* + * For the used double hash method the table size has to be a prime. To + * correct the user given table size we need a prime test. This trivial + * algorithm is adequate because + * a) the code is (most probably) called a few times per program run and + * b) the number is small because the table must fit in the core + * */ +static int isprime(unsigned int number) +{ + /* no even number will be passed */ + unsigned int div = 3; + + while (div * div < number && number % div != 0) + div += 2; + + return number % div != 0; +} + +int hcreate(size_t nel) +{ + return hcreate_r(nel, &htab); +} + +/* + * Before using the hash table we must allocate memory for it. + * Test for an existing table are done. We allocate one element + * more as the found prime number says. This is done for more effective + * indexing as explained in the comment for the hsearch function. + * The contents of the table is zeroed, especially the field used + * becomes zero. + */ +int hcreate_r(size_t nel, struct hsearch_data *htab) +{ + /* Test for correct arguments. */ + if (htab == NULL) { + __set_errno(EINVAL); + return 0; + } + + /* There is still another table active. Return with error. */ + if (htab->table != NULL) + return 0; + + /* Change nel to the first prime number not smaller as nel. */ + nel |= 1; /* make odd */ + while (!isprime(nel)) + nel += 2; + + htab->size = nel; + htab->filled = 0; + + /* allocate memory and zero out */ + htab->table = (_ENTRY *) calloc(htab->size + 1, sizeof(_ENTRY)); + if (htab->table == NULL) + return 0; + + /* everything went alright */ + return 1; +} + + +/* + * hdestroy() + */ +void hdestroy(void) +{ + hdestroy_r(&htab); +} + +/* + * After using the hash table it has to be destroyed. The used memory can + * be freed and the local static variable can be marked as not used. + */ +void hdestroy_r(struct hsearch_data *htab) +{ + int i; + + /* Test for correct arguments. */ + if (htab == NULL) { + __set_errno(EINVAL); + return; + } + + /* free used memory */ + for (i = 1; i <= htab->size; ++i) { + if (htab->table[i].used) { + ENTRY *ep = &htab->table[i].entry; + + free(ep->key); + free(ep->data); + } + } + free(htab->table); + + /* the sign for an existing table is an value != NULL in htable */ + htab->table = NULL; +} + +/* + * hsearch() + */ + +/* + * This is the search function. It uses double hashing with open addressing. + * The argument item.key has to be a pointer to an zero terminated, most + * probably strings of chars. The function for generating a number of the + * strings is simple but fast. It can be replaced by a more complex function + * like ajw (see [Aho,Sethi,Ullman]) if the needs are shown. + * + * We use an trick to speed up the lookup. The table is created by hcreate + * with one more element available. This enables us to use the index zero + * special. This index will never be used because we store the first hash + * index in the field used where zero means not used. Every other value + * means used. The used field can be used as a first fast comparison for + * equality of the stored and the parameter value. This helps to prevent + * unnecessary expensive calls of strcmp. + * + * This implementation differs from the standard library version of + * this function in a number of ways: + * + * - While the standard version does not make any assumptions about + * the type of the stored data objects at all, this implementation + * works with NUL terminated strings only. + * - Instead of storing just pointers to the original objects, we + * create local copies so the caller does not need to care about the + * data any more. + * - The standard implementation does not provide a way to update an + * existing entry. This version will create a new entry or update an + * existing one when both "action == ENTER" and "item.data != NULL". + * - Instead of returning 1 on success, we return the index into the + * internal hash table, which is also guaranteed to be positive. + * This allows us direct access to the found hash table slot for + * example for functions like hdelete(). + */ + +ENTRY *hsearch(ENTRY item, ACTION action) +{ + ENTRY *result; + + (void) hsearch_r(item, action, &result, &htab); + + return result; +} + +int hsearch_r(ENTRY item, ACTION action, ENTRY ** retval, + struct hsearch_data *htab) +{ + unsigned int hval; + unsigned int count; + unsigned int len = strlen(item.key); + unsigned int idx; + + /* Compute an value for the given string. Perhaps use a better method. */ + hval = len; + count = len; + while (count-- > 0) { + hval <<= 4; + hval += item.key[count]; + } + + /* + * First hash function: + * simply take the modul but prevent zero. + */ + hval %= htab->size; + if (hval == 0) + ++hval; + + /* The first index tried. */ + idx = hval; + + if (htab->table[idx].used) { + /* + * Further action might be required according to the + * action value. + */ + unsigned hval2; + + if (htab->table[idx].used == hval + && strcmp(item.key, htab->table[idx].entry.key) == 0) { + /* Overwrite existing value? */ + if ((action == ENTER) && (item.data != NULL)) { + free(htab->table[idx].entry.data); + htab->table[idx].entry.data = + strdup(item.data); + if (!htab->table[idx].entry.data) { + __set_errno(ENOMEM); + *retval = NULL; + return 0; + } + } + /* return found entry */ + *retval = &htab->table[idx].entry; + return idx; + } + + /* + * Second hash function: + * as suggested in [Knuth] + */ + hval2 = 1 + hval % (htab->size - 2); + + do { + /* + * Because SIZE is prime this guarantees to + * step through all available indices. + */ + if (idx <= hval2) + idx = htab->size + idx - hval2; + else + idx -= hval2; + + /* + * If we visited all entries leave the loop + * unsuccessfully. + */ + if (idx == hval) + break; + + /* If entry is found use it. */ + if ((htab->table[idx].used == hval) + && strcmp(item.key, htab->table[idx].entry.key) == 0) { + /* Overwrite existing value? */ + if ((action == ENTER) && (item.data != NULL)) { + free(htab->table[idx].entry.data); + htab->table[idx].entry.data = + strdup(item.data); + if (!htab->table[idx].entry.data) { + __set_errno(ENOMEM); + *retval = NULL; + return 0; + } + } + /* return found entry */ + *retval = &htab->table[idx].entry; + return idx; + } + } + while (htab->table[idx].used); + } + + /* An empty bucket has been found. */ + if (action == ENTER) { + /* + * If table is full and another entry should be + * entered return with error. + */ + if (htab->filled == htab->size) { + __set_errno(ENOMEM); + *retval = NULL; + return 0; + } + + /* + * Create new entry; + * create copies of item.key and item.data + */ + htab->table[idx].used = hval; + htab->table[idx].entry.key = strdup(item.key); + htab->table[idx].entry.data = strdup(item.data); + if (!htab->table[idx].entry.key || + !htab->table[idx].entry.data) { + __set_errno(ENOMEM); + *retval = NULL; + return 0; + } + + ++htab->filled; + + /* return new entry */ + *retval = &htab->table[idx].entry; + return 1; + } + + __set_errno(ESRCH); + *retval = NULL; + return 0; +} + + +/* + * hdelete() + */ + +/* + * The standard implementation of hsearch(3) does not provide any way + * to delete any entries from the hash table. We extend the code to + * do that. + */ + +int hdelete(const char *key) +{ + return hdelete_r(key, &htab); +} + +int hdelete_r(const char *key, struct hsearch_data *htab) +{ + ENTRY e, *ep; + int idx; + + debug("hdelete: DELETE key \"%s\"\n", key); + + e.key = (char *)key; + + if ((idx = hsearch_r(e, FIND, &ep, htab)) == 0) { + __set_errno(ESRCH); + return 0; /* not found */ + } + + /* free used ENTRY */ + debug("hdelete: DELETING key \"%s\"\n", key); + + free(ep->key); + free(ep->data); + htab->table[idx].used = 0; + + --htab->filled; + + return 1; +} + +/* + * hexport() + */ + +/* + * Export the data stored in the hash table in linearized form. + * + * Entries are exported as "name=value" strings, separated by an + * arbitrary (non-NUL, of course) separator character. This allows to + * use this function both when formatting the U-Boot environment for + * external storage (using '\0' as separator), but also when using it + * for the "printenv" command to print all variables, simply by using + * as '\n" as separator. This can also be used for new features like + * exporting the environment data as text file, including the option + * for later re-import. + * + * The entries in the result list will be sorted by ascending key + * values. + * + * If the separator character is different from NUL, then any + * separator characters and backslash characters in the values will + * be escaped by a preceeding backslash in output. This is needed for + * example to enable multi-line values, especially when the output + * shall later be parsed (for example, for re-import). + * + * There are several options how the result buffer is handled: + * + * *resp size + * ----------- + * NULL 0 A string of sufficient length will be allocated. + * NULL >0 A string of the size given will be + * allocated. An error will be returned if the size is + * not sufficient. Any unused bytes in the string will + * be '\0'-padded. + * !NULL 0 The user-supplied buffer will be used. No length + * checking will be performed, i. e. it is assumed that + * the buffer size will always be big enough. DANGEROUS. + * !NULL >0 The user-supplied buffer will be used. An error will + * be returned if the size is not sufficient. Any unused + * bytes in the string will be '\0'-padded. + */ + +ssize_t hexport(const char sep, char **resp, size_t size) +{ + return hexport_r(&htab, sep, resp, size); +} + +static int cmpkey(const void *p1, const void *p2) +{ + ENTRY *e1 = *(ENTRY **) p1; + ENTRY *e2 = *(ENTRY **) p2; + + return (strcmp(e1->key, e2->key)); +} + +ssize_t hexport_r(struct hsearch_data *htab, const char sep, + char **resp, size_t size) +{ + ENTRY *list[htab->size]; + char *res, *p; + size_t totlen; + int i, n; + + /* Test for correct arguments. */ + if ((resp == NULL) || (htab == NULL)) { + __set_errno(EINVAL); + return (-1); + } + + debug("EXPORT table = %p, htab.size = %d, htab.filled = %d, size = %d\n", + htab, htab->size, htab->filled, size); + /* + * Pass 1: + * search used entries, + * save addresses and compute total length + */ + for (i = 1, n = 0, totlen = 0; i <= htab->size; ++i) { + + if (htab->table[i].used) { + ENTRY *ep = &htab->table[i].entry; + + list[n++] = ep; + + totlen += strlen(ep->key) + 2; + + if (sep == '\0') { + totlen += strlen(ep->data); + } else { /* check if escapes are needed */ + char *s = ep->data; + + while (*s) { + ++totlen; + /* add room for needed escape chars */ + if ((*s == sep) || (*s == '\\')) + ++totlen; + ++s; + } + } + totlen += 2; /* for '=' and 'sep' char */ + } + } + +#ifdef DEBUG + /* Pass 1a: print unsorted list */ + printf("Unsorted: n=%d\n", n); + for (i = 0; i < n; ++i) { + printf("\t%3d: %p ==> %-10s => %s\n", + i, list[i], list[i]->key, list[i]->data); + } +#endif + + /* Sort list by keys */ + qsort(list, n, sizeof(ENTRY *), cmpkey); + + /* Check if the user supplied buffer size is sufficient */ + if (size) { + if (size < totlen + 1) { /* provided buffer too small */ + debug("### buffer too small: %d, but need %d\n", + size, totlen + 1); + __set_errno(ENOMEM); + return (-1); + } + } else { + size = totlen + 1; + } + + /* Check if the user provided a buffer */ + if (*resp) { + /* yes; clear it */ + res = *resp; + memset(res, '\0', size); + } else { + /* no, allocate and clear one */ + *resp = res = calloc(1, size); + if (res == NULL) { + __set_errno(ENOMEM); + return (-1); + } + } + /* + * Pass 2: + * export sorted list of result data + */ + for (i = 0, p = res; i < n; ++i) { + char *s; + + s = list[i]->key; + while (*s) + *p++ = *s++; + *p++ = '='; + + s = list[i]->data; + + while (*s) { + if ((*s == sep) || (*s == '\\')) + *p++ = '\\'; /* escape */ + *p++ = *s++; + } + *p++ = sep; + } + *p = '\0'; /* terminate result */ + + return size; +} + + +/* + * himport() + */ + +/* + * Import linearized data into hash table. + * + * This is the inverse function to hexport(): it takes a linear list + * of "name=value" pairs and creates hash table entries from it. + * + * Entries without "value", i. e. consisting of only "name" or + * "name=", will cause this entry to be deleted from the hash table. + * + * The "flag" argument can be used to control the behaviour: when the + * H_NOCLEAR bit is set, then an existing hash table will kept, i. e. + * new data will be added to an existing hash table; otherwise, old + * data will be discarded and a new hash table will be created. + * + * The separator character for the "name=value" pairs can be selected, + * so we both support importing from externally stored environment + * data (separated by NUL characters) and from plain text files + * (entries separated by newline characters). + * + * To allow for nicely formatted text input, leading white space + * (sequences of SPACE and TAB chars) is ignored, and entries starting + * (after removal of any leading white space) with a '#' character are + * considered comments and ignored. + * + * [NOTE: this means that a variable name cannot start with a '#' + * character.] + * + * When using a non-NUL separator character, backslash is used as + * escape character in the value part, allowing for example for + * multi-line values. + * + * In theory, arbitrary separator characters can be used, but only + * '\0' and '\n' have really been tested. + */ + +int himport(const char *env, size_t size, const char sep, int flag) +{ + return himport_r(&htab, env, size, sep, flag); +} + +int himport_r(struct hsearch_data *htab, + const char *env, size_t size, const char sep, int flag) +{ + char *data, *sp, *dp, *name, *value; + + /* Test for correct arguments. */ + if (htab == NULL) { + __set_errno(EINVAL); + return 0; + } + + /* we allocate new space to make sure we can write to the array */ + if ((data = malloc(size)) == NULL) { + debug("himport_r: can't malloc %d bytes\n", size); + __set_errno(ENOMEM); + return 0; + } + memcpy(data, env, size); + dp = data; + + if ((flag & H_NOCLEAR) == 0) { + /* Destroy old hash table if one exists */ + debug("Destroy Hash Table: %p table = %p\n", htab, + htab->table); + if (htab->table) + hdestroy_r(htab); + } + + /* + * Create new hash table (if needed). The computation of the hash + * table size is based on heuristics: in a sample of some 70+ + * existing systems we found an average size of 39+ bytes per entry + * in the environment (for the whole key=value pair). Assuming a + * size of 8 per entry (= safety factor of ~5) should provide enough + * safety margin for any existing environment definitions and still + * allow for more than enough dynamic additions. Note that the + * "size" argument is supposed to give the maximum enviroment size + * (CONFIG_ENV_SIZE). This heuristics will result in + * unreasonably large numbers (and thus memory footprint) for + * big flash environments (>8,000 entries for 64 KB + * envrionment size), so we clip it to a reasonable value + * (which can be overwritten in the board config file if + * needed). + */ + + if (!htab->table) { + int nent = size / 8; + + if (nent > CONFIG_ENV_MAX_ENTRIES) + nent = CONFIG_ENV_MAX_ENTRIES; + + debug("Create Hash Table: N=%d\n", nent); + + if (hcreate_r(nent, htab) == 0) { + free(data); + return 0; + } + } + + /* Parse environment; allow for '\0' and 'sep' as separators */ + do { + ENTRY e, *rv; + + /* skip leading white space */ + while ((*dp == ' ') || (*dp == '\t')) + ++dp; + + /* skip comment lines */ + if (*dp == '#') { + while (*dp && (*dp != sep)) + ++dp; + ++dp; + continue; + } + + /* parse name */ + for (name = dp; *dp != '=' && *dp && *dp != sep; ++dp) + ; + + /* deal with "name" and "name=" entries (delete var) */ + if (*dp == '\0' || *(dp + 1) == '\0' || + *dp == sep || *(dp + 1) == sep) { + if (*dp == '=') + *dp++ = '\0'; + *dp++ = '\0'; /* terminate name */ + + debug("DELETE CANDIDATE: \"%s\"\n", name); + + if (hdelete_r(name, htab) == 0) + debug("DELETE ERROR ##############################\n"); + + continue; + } + *dp++ = '\0'; /* terminate name */ + + /* parse value; deal with escapes */ + for (value = sp = dp; *dp && (*dp != sep); ++dp) { + if ((*dp == '\\') && *(dp + 1)) + ++dp; + *sp++ = *dp; + } + *sp++ = '\0'; /* terminate value */ + ++dp; + + /* enter into hash table */ + e.key = name; + e.data = value; + + hsearch_r(e, ENTER, &rv, htab); + if (rv == NULL) { + printf("himport_r: can't insert \"%s=%s\" into hash table\n", + name, value); + return 0; + } + + debug("INSERT: table %p, filled %d/%d rv %p ==> name=\"%s\" value=\"%s\"\n", + htab, htab->filled, htab->size, + rv, name, value); + } while ((dp < data + size) && *dp); /* size check needed for text */ + /* without '\0' termination */ + debug("INSERT: free(data = %p)\n", data); + free(data); + + debug("INSERT: done\n"); + return 1; /* everything OK */ +} diff --git a/lib/qsort.c b/lib/qsort.c new file mode 100644 index 0000000..bb47319 --- /dev/null +++ b/lib/qsort.c @@ -0,0 +1,69 @@ +/* + * Code adapted from uClibc-0.9.30.3 + * + * It is therefore covered by the GNU LESSER GENERAL PUBLIC LICENSE + * Version 2.1, February 1999 + * + * Wolfgang Denk <wd@denx.de> + */ + +/* This code is derived from a public domain shell sort routine by + * Ray Gardner and found in Bob Stout's snippets collection. The + * original code is included below in an #if 0/#endif block. + * + * I modified it to avoid the possibility of overflow in the wgap + * calculation, as well as to reduce the generated code size with + * bcc and gcc. */ + +#include <linux/types.h> +#if 0 +#include <assert.h> +#else +#define assert(arg) +#endif + +void qsort(void *base, + size_t nel, + size_t width, + int (*comp)(const void *, const void *)) +{ + size_t wgap, i, j, k; + char tmp; + + if ((nel > 1) && (width > 0)) { + assert(nel <= ((size_t)(-1)) / width); /* check for overflow */ + wgap = 0; + do { + wgap = 3 * wgap + 1; + } while (wgap < (nel-1)/3); + /* From the above, we know that either wgap == 1 < nel or */ + /* ((wgap-1)/3 < (int) ((nel-1)/3) <= (nel-1)/3 ==> wgap < nel. */ + wgap *= width; /* So this can not overflow if wnel doesn't. */ + nel *= width; /* Convert nel to 'wnel' */ + do { + i = wgap; + do { + j = i; + do { + register char *a; + register char *b; + + j -= wgap; + a = j + ((char *)base); + b = a + wgap; + if ((*comp)(a, b) <= 0) { + break; + } + k = width; + do { + tmp = *a; + *a++ = *b; + *b++ = tmp; + } while (--k); + } while (j >= wgap); + i += width; + } while (i < nel); + wgap = (wgap - width)/3; + } while (wgap); + } +} diff --git a/nand_spl/board/amcc/bamboo/sdram.c b/nand_spl/board/amcc/bamboo/sdram.c index 9fec5ca..504a02b 100644 --- a/nand_spl/board/amcc/bamboo/sdram.c +++ b/nand_spl/board/amcc/bamboo/sdram.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/processor.h> #include <asm/io.h> diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c index ed1888c..f71ecfb9 100644 --- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c +++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c @@ -22,7 +22,7 @@ */ #include <common.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> #include <asm/io.h> #include <asm/processor.h> @@ -57,7 +57,7 @@ static void ddr_init_common(void) /* * Reset the DDR-SDRAM controller. */ - mtsdr(SDR0_SRST, (0x80000000 >> 10)); + mtsdr(SDR0_SRST, SDR0_SRST0_DMC); mtsdr(SDR0_SRST, 0x00000000); /* diff --git a/nand_spl/board/karo/tx25/u-boot.lds b/nand_spl/board/karo/tx25/u-boot.lds index 423bed3..c572557 100644 --- a/nand_spl/board/karo/tx25/u-boot.lds +++ b/nand_spl/board/karo/tx25/u-boot.lds @@ -41,11 +41,23 @@ SECTIONS .rodata : { *(.rodata) } . = ALIGN(4); - .data : { *(.data) } + .data : { + *(.data) + __datarel_start = .; + *(.data.rel) + __datarelrolocal_start = .; + *(.data.rel.ro.local) + __datarellocal_start = .; + *(.data.rel.local) + __datarelro_start = .; + *(.data.rel.ro) + } + __got_start = .; . = ALIGN(4); .got : { *(.got) } + __got_end = .; . = .; __u_boot_cmd_start = .; .u_boot_cmd : { *(.u_boot_cmd) } diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index b9fd6f5..0580dbf 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -221,6 +221,13 @@ static int nand_load(struct mtd_info *mtd, unsigned int offs, return 0; } +#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +void board_init_f (ulong bootflag) +{ + relocate_code (TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE); +} +#endif + /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image diff --git a/nand_spl/nand_boot_fsl_nfc.c b/nand_spl/nand_boot_fsl_nfc.c index bfae30e..f89d542 100644 --- a/nand_spl/nand_boot_fsl_nfc.c +++ b/nand_spl/nand_boot_fsl_nfc.c @@ -34,7 +34,7 @@ #include <asm/io.h> #include <fsl_nfc.h> -struct fsl_nfc_regs *nfc; +static struct fsl_nfc_regs *const nfc = (void *)NFC_BASE_ADDR; static void nfc_wait_ready(void) { @@ -228,8 +228,6 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) unsigned int maxpages = CONFIG_SYS_NAND_SIZE / CONFIG_SYS_NAND_PAGE_SIZE; - nfc = (void *)NFC_BASE_ADDR; - nfc_nand_init(); /* Convert to page number */ @@ -265,6 +263,13 @@ static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) return 0; } +#if defined(CONFIG_ARM) && !defined(CONFIG_SYS_ARM_WITHOUT_RELOC) +void board_init_f (ulong bootflag) +{ + relocate_code (TEXT_BASE - TOTAL_MALLOC_LEN, NULL, TEXT_BASE); +} +#endif + /* * The main entry for NAND booting. It's necessary that SDRAM is already * configured and available since this code loads the main U-Boot image @@ -274,8 +279,6 @@ void nand_boot(void) { __attribute__((noreturn)) void (*uboot)(void); - nfc = (void *)NFC_BASE_ADDR; - /* * CONFIG_SYS_NAND_U_BOOT_OFFS and CONFIG_SYS_NAND_U_BOOT_SIZE must * be aligned to full pages diff --git a/post/board/lwmon5/watchdog.c b/post/board/lwmon5/watchdog.c index 44f0488..f181506 100644 --- a/post/board/lwmon5/watchdog.c +++ b/post/board/lwmon5/watchdog.c @@ -34,7 +34,7 @@ #if CONFIG_POST & CONFIG_SYS_POST_WATCHDOG #include <watchdog.h> -#include <asm/gpio.h> +#include <asm/ppc4xx-gpio.h> #include <asm/io.h> static uint watchdog_magic_read(void) diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c index 6ab1593..50ae7fb 100644 --- a/post/cpu/ppc4xx/denali_ecc.c +++ b/post/cpu/ppc4xx/denali_ecc.c @@ -45,7 +45,7 @@ #include <asm/processor.h> #include <asm/mmu.h> #include <asm/io.h> -#include <ppc440.h> +#include <asm/ppc440.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index a58db04..7f44f38 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -44,8 +44,8 @@ #include <asm/cache.h> #include <asm/io.h> #include <asm/processor.h> -#include <405_mal.h> -#include <ppc4xx_enet.h> +#include <asm/ppc4xx-mal.h> +#include <asm/ppc4xx-emac.h> #include <malloc.h> DECLARE_GLOBAL_DATA_PTR; diff --git a/post/cpu/ppc4xx/fpu.c b/post/cpu/ppc4xx/fpu.c index e9b96dd..9f49690 100644 --- a/post/cpu/ppc4xx/fpu.c +++ b/post/cpu/ppc4xx/fpu.c @@ -29,7 +29,7 @@ defined(CONFIG_440EPX) #include <asm/processor.h> -#include <ppc4xx.h> +#include <asm/ppc4xx.h> int fpu_status(void) diff --git a/tools/.gitignore b/tools/.gitignore index cb067a4..07f21a3 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -9,3 +9,8 @@ /ubsha1 /inca-swap-bytes /*.exe +/easylogo/easylogo +/env/crc32.c +/env/fw_printenv +/gdb/gdbcont +/gdb/gdbsend diff --git a/tools/Makefile b/tools/Makefile index b2e73b2..8ec92d2 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -41,6 +41,7 @@ include $(TOPDIR)/config.mk # Enable all the config-independent tools ifneq ($(HOST_TOOLS_ALL),) CONFIG_LCD_LOGO = y +CONFIG_CMD_LOADS = y CONFIG_CMD_NET = y CONFIG_INCA_IP = y CONFIG_NETCONSOLE = y @@ -115,6 +116,9 @@ endif ifeq ($(VENDOR),esd) LOGO_BMP= logos/esd.bmp endif +ifeq ($(VENDOR),freescale) +LOGO_BMP= logos/freescale.bmp +endif ifeq ($(VENDOR),ronetix) LOGO_BMP= logos/ronetix.bmp endif diff --git a/tools/env/Makefile b/tools/env/Makefile index 2df631e..f893040 100644 --- a/tools/env/Makefile +++ b/tools/env/Makefile @@ -26,16 +26,16 @@ include $(TOPDIR)/config.mk SRCS := $(obj)crc32.c fw_env.c fw_env_main.c HEADERS := fw_env.h -CPPFLAGS := -Wall -DUSE_HOSTCC -I$(SRCTREE)/include +HOSTCFLAGS += -Wall -DUSE_HOSTCC -I$(SRCTREE)/include ifeq ($(MTD_VERSION),old) -CPPFLAGS += -DMTD_OLD +HOSTCFLAGS += -DMTD_OLD endif all: $(obj)fw_printenv $(obj)fw_printenv: $(SRCS) $(HEADERS) - $(CROSS_COMPILE)gcc $(CPPFLAGS) $(SRCS) -o $(obj)fw_printenv + $(HOSTCC) $(HOSTCFLAGS) $(HOSTLDFLAGS) -o $@ $(SRCS) clean: rm -f $(obj)fw_printenv $(obj)crc32.c diff --git a/tools/logos/freescale.bmp b/tools/logos/freescale.bmp Binary files differnew file mode 100644 index 0000000..1589e80 --- /dev/null +++ b/tools/logos/freescale.bmp |
