diff options
119 files changed, 1278 insertions, 1570 deletions
diff --git a/CREDITS b/CREDITS deleted file mode 100644 index 43d4764..0000000 --- a/CREDITS +++ /dev/null @@ -1,536 +0,0 @@ -# -# Parts of the development effort for this project have been -# sponsored by SIEMENS AG, Austria. Thanks to SIEMENS for -# supporting an Open Source project! -# -# -# This is at least a partial credits-file of individual people that -# have contributed to the U-Boot project. It is sorted by name and -# formatted to allow easy grepping and beautification by scripts. -# The fields are: name (N), email (E), web-address (W), PGP key ID -# and fingerprint (P), description (D), and snail-mail address (S). -# Thanks, -# -# Wolfgang Denk -#---------- - -N: Dr. Bruno Achauer -E: bruno@exet-ag.de -D: Support for NetBSD (both as host and target system) - -N: Guillaume Alexandre -E: guillaume.alexandre@gespac.ch -D: Add PCIPPC6 configuration - -N: Pantelis Antoniou -E: panto@intracom.gr -D: NETVIA & NETPHONE board support, ARTOS support. -D: Support for Silicon Turnkey eXpress XTc - -N: Pierre Aubert -E: <p.aubert@staubli.com> -D: Support for RPXClassic board - -N: Yuli Barcohen -E: yuli@arabellasw.com -D: Unified support for Motorola MPC826xADS/MPC8272ADS/PQ2FADS boards. -D: Support for Zephyr Engineering ZPC.1900 board. -D: Support for Interphase iSPAN boards. -D: Support for Analogue&Micro Adder boards. -D: Support for Analogue&Micro Rattler boards. -W: http://www.arabellasw.com - -N: Jerry van Baren -E: <vanbaren@cideas.com> -D: BedBug port to 603e core (MPC82xx). Code for enhanced memory test. - -N: Pavel Bartusek -E: <pba@sysgo.com> -D: Reiserfs support -W: http://www.elinos.com - -N: Andre Beaudin -E: <andre.beaudin@colubris.com> -D: PCMCIA, Ethernet, TFTP - -N: Jon Benediktsson -E: jonb@marel.is -D: Support for Marel V37 board - -N: Raphael Bossek -E: raphael.bossek@solutions4linux.de -D: 8xxrom-0.3.0 - -N: Cliff Brake -E: cliff.brake@gmail.com -D: Port to Vibren PXA255 IDP platform -W: http://www.vibren.com -W: http://bec-systems.com - -N: Rick Bronson -E: rick@efn.org -D: Atmel AT91RM9200DK and NAND support - -N: David Brown -E: DBrown03@harris.com -D: Extensions to 8xxrom-0.3.0 - -N: Oliver Brown -E: obrown@adventnetworks.com -D: Port to the gw8260 board - -N: Jonathan De Bruyne -E: jonathan.debruyne@siemens.atea.be -D: Port to Siemens IAD210 board - -N: Ken Chou -E: kchou@ieee.org -D: Support for A3000 SBC board - -N: Conn Clark -E: clark@esteem.com -D: ESTEEM192E support - -N: Magnus Damm -E: damm@opensource.se -D: 8xxrom - -N: Richard Danter -E: richard.danter@windriver.com -D: Support for Wind River PPMC 7xx/74xx boards - -N: George G. Davis -E: gdavis@mvista.com -D: Board ports for ADS GraphicsClient+ and Intel Assabet - -N: Arun Dharankar -E: ADharankar@ATTBI.Com -D: threads / scheduler example code - -N: K?ri Dav??sson -E: kd@flaga.is -D: FLAGA DM Support - -N: Wolfgang Denk -E: wd@denx.de -D: U-Boot initial version, continuing maintenance, ARMBoot merge -W: http://www.denx.de - -N: Dan A. Dickey -E: ddickey@charter.net -D: FADS Support - -N: Mike Dunn -E: mikedunn@newsguy.com -D: Palmtreo680 board, docg4 nand flash driver - -N: Dave Ellis -E: DGE@sixnetio.com -D: EEPROM Speedup - -N: Daniel Engstr?m -E: daniel@omicron.se -D: x86 port, Support for sc520_cdp board - -N: Hayden Fraser -E: Hayden.Fraser@freescale.com -D: Support for ColdFire MCF5253 -W: www.freescale.com - -N: Dr. Wolfgang Grandegger -E: wg@denx.de -D: Support for Interphase 4539 T1/E1/J1 PMC, CCM, SCM boards -W: www.denx.de - -N: Peter Figuli -E: peposh@etc.sk -D: Support for WEP EP250 (PXA) board - -N: Thomas Frieden -E: ThomasF@hyperion-entertainment.com -D: Support for AmigaOne - -N: Paul Gortmaker -E: paul.gortmaker@windriver.com -D: Support for WRS SBC8347/8349 boards - -N: Frank Gottschling -E: fgottschling@eltec.de -D: Support for ELTEC MHPC/ELPPC boards, cfb-console, i8042, SMI LynxEM -W: www.eltec.de - -N: Marius Groeger -E: mgroeger@sysgo.de -D: MBX Support, board specific function interface, EST SBC8260 support; initial support for StrongARM (LART), ARM720TDMI (implementa A7) -W: www.elinos.com - -N: Kirk Haderlie -E: khaderlie@vividimage.com -D: Added TFTP to 8xxrom (-> 0.3.1) - -N: Chris Hallinan -E: clh@net1plus.com -D: DHCP Support - -N: Anne-Sophie Harnois -E: Anne-Sophie.Harnois@nextream.fr -D: Port to Walnut405 board - -N: Andreas Heppel -E: aheppel@sysgo.de -D: CPU Support for MPC 75x - -N: Josh Huber -E: huber@alum.wpi.edu -D: Port to the Galileo Evaluation Board, and the MPC74xx cpu series. -W: http://www.mclx.com/ - -H: Stuart Hughes -E: stuarth@lineo.com -D: Port to MPC8260ADS board - -H: Rich Ireland -E: r.ireland@computer.org -D: FPGA device configuration driver - -H: Mark Jackson -E: mpfj@mimc.co.uk -D: Port to MIMC200 board - -N: Gary Jennejohn -E: garyj@jennejohn.org -D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" -W: www.denx.de - -N: Murray Jensen -E: Murray.Jensen@csiro.au -D: Initial 8260 support; GDB support -D: Port to Cogent+Hymod boards; Hymod Board Database - -N: Yoo. Jonghoon -E: yooth@ipone.co.kr -D: Added port to the RPXlite board - -N: Mark Jonas -E: mark.jonas@freescale.com -D: Support for Freescale Total5200 platform -W: http://www.mobilegt.com/ - -N: Mark Jonas -E: mark.jonas@de.bosch.com -D: Support for MPR2 board - -N: Sam Song -E: samsongshu@yahoo.com.cn -D: Port to the RPXlite_DW board - -N: Brad Kemp -E: Brad.Kemp@seranoa.com -D: Port to Windriver ppmc8260 board - -N: Sangmoon Kim -E: dogoil@etinsys.com -D: Support for debris board -D: Support for KVME080 board - -N: Frederick W. Klatt -E: fred.klatt@windriver.com -D: Support for Wind River SBC8540/SBC8560 boards - -N: Thomas Koeller -E: tkoeller@gmx.net -D: Port to Motorola Sandpoint 3 (MPC8240) - -N: Raghu Krishnaprasad -E: Raghu.Krishnaprasad@fci.com -D: Support for Adder-II MPC852T evaluation board -W: http://www.forcecomputers.com - -N: Sergey Kubushyn -E: ksi@koi8.net -D: Support for various TI DaVinci based boards. - -N: Bernhard Kuhn -E: bkuhn@metrowerks.com -D Support for Coldfire CPU; Support for Motorola M5272C3 and M5282EVB boards - -N: Prakash Kumar -E: prakash@embedx.com -D Support for Intrinsyc CERF PXA250 board. - -N: Thomas Lange -E: thomas@corelatus.se -D: Support for GTH, GTH2 and dbau1x00 boards; lots of PCMCIA fixes - -N: The LEOX team -E: team@leox.org -D: Support for LEOX boards, DS164x RTC -W: http://www.leox.org - -N: TsiChung Liew -E: Tsi-Chung.Liew@freescale.com -D: Support for ColdFire MCF523x, MCF532x, MCF5445x, MCF547x_8x -W: www.freescale.com - -N: Leif Lindholm -E: leif.lindholm@i3micro.com -D: Support for AMD dbau1550 board. - -N: Stephan Linz -E: linz@li-pro.net -D: Support for Nios Stratix Development Kit (DK-1S10) -D: Support for SSV ADNP/ESC1 (Nios Cyclone) -W: http://www.li-pro.net - -N: Dave Liu -E: daveliu@freescale.com -D: Support for MPC8315, MPC832x, MPC8360, MPC837x -W: www.freescale.com - -N: Raymond Lo -E: lo@routefree.com -D: Support for DOS partitions - -N: James MacAulay -E: james.macaulay@amirix.com -D: Suppport for Amirix AP1000 -W: www.amirix.com - -N: Dan Malek -E: dan@embeddedalley.com -D: FADSROM, the grandfather of all of this -D: Support for Silicon Turnkey eXpress XTc - -N: Andrea "llandre" Marson -E: andrea.marson@dave-tech.it -D: Port to PPChameleonEVB board -W: www.dave-tech.it - -N: Reinhard Meyer -E: r.meyer@emk-elektronik.de -D: Port to EMK TOP860 Module - -N: Jay Monkman -E: jtm@smoothsmoothie.com -D: EST SBC8260 support - -N: Frank Morauf -E: frank.morauf@salzbrenner.com -D: Support for Embedded Planet RPX Super Board - -N: David M?ller -E: d.mueller@elsoft.ch -D: Support for Samsung ARM920T SMDK2410 eval board - -N: Scott McNutt -E: smcnutt@psyent.com -D: Support for Altera Nios-32 CPU -D: Support for Altera Nios-II CPU -D: Support for Nios Cyclone Development Kit (DK-1C20) -W: http://www.psyent.com - -N: Rolf Offermanns -E: rof@sysgo.de -D: Initial support for SSV-DNP1110, SMC91111 driver -W: www.elinos.com - -N: John Otken -E: jotken@softadvances.com -D: Support for AMCC Luan 440SP board - -N: Tolunay Orkun -E: torkun@nextio.com -D: Support for Cogent CSB272 & CSB472 boards - -N: Keith Outwater -E: keith_outwater@mvis.com -D: Support for generic/custom MPC860T boards (GEN860T, GEN860T_SC) - -N: Frank Panno -E: fpanno@delphintech.com -D: Support for Embedded Planet EP8260 Board - -N: Denis Peter -E: d.peter@mpl.ch -D: Support for 4xx SCSI, floppy, CDROM, CT69000 video, ... -D: Support for PIP405 board -D: Support for MIP405 board - -N: Dave Peverley -E: dpeverley@mpc-data.co.uk -W: http://www.mpc-data.co.uk -D: OMAP730 P2 board support - -N: Bill Pitts -E: wlp@mindspring.com -D: BedBug embedded debugger code - -N: Daniel Poirot -E: dan.poirot@windriver.com -D: Support for the Wind River sbc405, sbc8240 board -W: http://www.windriver.com - -N: Stelian Pop -E: stelian@popies.net -D: Atmel AT91CAP9ADK support - -N: Ricardo Ribalda Delgado -E: ricardo.ribalda@uam.es -D: PPC440x5 (Virtex5), ML507 Board, eeprom_simul, adt7460, v5fx30teval -D: Virtex ppc440 generic architecture -D: Virtex ppc405 generic architecture -W: http://www.ii.uam.es/~rribalda - -N: Stefan Roese -E: sr@denx.de -D: AMCC PPC4xx Support -W: http://www.denx.de - -N: Erwin Rol -E: erwin@muffin.org -D: boot support for RTEMS - -N: Paul Ruhland -E: pruhland@rochester.rr.com -D: Port to Logic Zoom LH7A40x SDK board(s) - -N: Neil Russell -E: caret@c-side.com -D: Author of LiMon-1.4.2, which contributed some ideas - -N: Travis B. Sawyer -E: travis.sawyer@sandburst.com -D: Support for AMCC PPC440GX, XES XPedite1000 440GX PrPMC board. AMCC 440gx Ref Platform (Ocotea) - -N: Paolo Scaffardi -E: arsenio@tin.it -D: FADS823 configuration, MPC823 video support, I2C, wireless keyboard, lots more - -N: Andre Schwarz -E: andre.schwarz@matrix-vision.de -D: Support for Matrix Vision boards (MVBLM7/MVBC_P/MVSMR) - -N: Robert Schwebel -E: r.schwebel@pengutronix.de -D: Support for csb226 and innokom boards (PXA2xx) - -N: Aaron Sells -E: sellsa@embeddedplanet.com -D: Support for EP82xxM - -N: Art Shipkowski -E: art@videon-central.com -D: Support for NetSilicon NS7520 -D: Support for ColdFire MCF5275 - -N: Jeremy C. Andrus -E: jeremy@jeremya.com -D: ColdFire MCF5249 initialization code -W: jeremya.com - -N: Michal Simek -E: monstr@monstr.eu -D: Support for Microblaze, ML401, XUPV2P board -W: www.monstr.eu - -N: Yasushi Shoji -E: yashi@atmark-techno.com -D: Support for Xilinx MicroBlaze, for Atmark Techno SUZAKU FPGA board - -N: Kurt Stremerch -E: kurt@exys.be -D: Support for Exys XSEngine board - -N: Andrea Scian -E: andrea.scian@dave-tech.it -D: Port to B2 board -W: www.dave-tech.it - -N: Timur Tabi -E: timur@freescale.com -D: Support for MPC8349E-mITX -W: www.freescale.com - -N: Rob Taylor -E: robt@flyingpig.com -D: Port to MBX860T and Sandpoint8240 - -N: Erik Theisen -E: etheisen@mindspring.com -D: MBX8xx and many other patches - -N: Jim Thompson -E: jim@musenki.com -D: Support for MUSENKI board - -N: Rune Torgersen -E: <runet@innovsys.com> -D: Support for Motorola MPC8266ADS board - -N: Greg Ungerer -E: greg.ungerer@opengear.com -D: Support for ks8695 CPU, and OpenGear cmXXXX boards - -N: David Updegraff -E: dave@cray.com -D: Port to Cray L1 board; DHCP vendor extensions - -N: Christian Vejlbo -E: christian.vejlbo@tellabs.com -D: FADS860T ethernet support - -N: Robert Whaley -E: rwhaley@applieddata.net -D: Port to ARM PXA27x adsvix SBC - -N: Martin Winistoerfer -E: martinwinistoerfer@gmx.ch -D: Port to MPC555/556 microcontrollers and support for cmi board - -N: David Wu -E: support@arcturusnetworks.com -D: Mercury Security EP2500 -W: http://www.arcturusnetworks.com - -N: Ming-Len Wu -E: minglen_wu@techware.com.tw -D: Motorola MX1ADS board support -W: http://www.techware.com.tw/ - -N: Xianghua Xiao -E: x.xiao@motorola.com -D: Support for Motorola 85xx(PowerQUICC III) chip, MPC8540ADS and MPC8560ADS boards. - -N: John Zhan -E: zhanz@sinovee.com -D: Support for SinoVee Microsystems SC8xx SBC - -N: Alex Zuepke -E: azu@sysgo.de -D: Overall improvements on StrongARM, ARM720TDMI; Support for Tuxscreen; initial PCMCIA support for ARM -W: www.elinos.com - -N: Nobuhiro Iwamatsu -E: iwamatsu@nigauri.org -D: Support for SuperH, MS7750SE01 and MS7722SE01 boards. -W: http://www.nigauri.org/~iwamatsu/ - -N: Alan Lu -E: alnalu001@gmail.com -D: Support for Artila M-501 starter kit -W: http://www.artila.com/ - -N: Kimmo Leppala -E: kimmo.leppala@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Timo Tuunainen -E: timo.tuunainen@sysart.fi -D: Support for Artila M-501 starter kit -W: http://www.sysart.fi/ - -N: Philip Balister -E: philip@opensdr.com -D: Port to Lyrtech SFFSDR development board. -W: www.opensdr.com @@ -107,6 +107,12 @@ config SYS_EXTRA_OPTIONS configuration to Kconfig. Since this option will be removed sometime, new boards should not use this option. +config SYS_TEXT_BASE + depends on SPARC + hex "Text Base" + help + TODO: Move CONFIG_SYS_TEXT_BASE for all the architecture + endmenu # Boot images source "arch/Kconfig" diff --git a/MAINTAINERS b/MAINTAINERS index fd346c9..4e2f8a9 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -253,7 +253,7 @@ T: git git://git.denx.de/u-boot-mips.git F: arch/mips/ MMC -M: Pantelis Antoniou <panto.antoniou-consulting.com> +M: Pantelis Antoniou <panto@antoniou-consulting.com> S: Maintained T: git git://git.denx.de/u-boot-mmc.git F: drivers/mmc/ diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 171ad03..43700c3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -177,10 +177,6 @@ config TARGET_ETHERNUT5 bool "Support ethernut5" select CPU_ARM926EJS -config TARGET_TOP9000 - bool "Support top9000" - select CPU_ARM926EJS - config TARGET_MEESC bool "Support meesc" select CPU_ARM926EJS diff --git a/arch/arm/cpu/arm926ejs/cache.c b/arch/arm/cpu/arm926ejs/cache.c index e86c2ed..8d7873c 100644 --- a/arch/arm/cpu/arm926ejs/cache.c +++ b/arch/arm/cpu/arm926ejs/cache.c @@ -99,7 +99,4 @@ void flush_cache(unsigned long start, unsigned long size) /* * Stub implementations for l2 cache operations */ -void __l2_cache_disable(void) {} - -void l2_cache_disable(void) - __attribute__((weak, alias("__l2_cache_disable"))); +__weak void l2_cache_disable(void) {} diff --git a/arch/arm/cpu/armv7/uniphier/Kconfig b/arch/arm/cpu/armv7/uniphier/Kconfig index 524b193..f013dc3 100644 --- a/arch/arm/cpu/armv7/uniphier/Kconfig +++ b/arch/arm/cpu/armv7/uniphier/Kconfig @@ -23,4 +23,13 @@ config MACH_PH1_SLD8 endchoice +config CMD_PINMON + bool "Enable boot mode pins monitor command" + depends on !SPL_BUILD + default y + help + The command "pinmon" shows the state of the boot mode pins. + The boot mode pins are latched when the system reset is deasserted + and determine which device the system should load a boot image from. + endmenu diff --git a/arch/arm/cpu/armv7/uniphier/Makefile b/arch/arm/cpu/armv7/uniphier/Makefile index 7ceddda..dd57469 100644 --- a/arch/arm/cpu/armv7/uniphier/Makefile +++ b/arch/arm/cpu/armv7/uniphier/Makefile @@ -12,7 +12,7 @@ obj-y += dram_init.o obj-$(CONFIG_DISPLAY_CPUINFO) += cpu_info.o obj-$(CONFIG_BOARD_LATE_INIT) += board_late_init.o obj-$(CONFIG_UNIPHIER_SMP) += smp.o -obj-$(if $(CONFIG_SPL_BUILD),,y) += cmd_pinmon.o +obj-$(CONFIG_CMD_PINMON) += cmd_pinmon.o obj-y += board_common.o obj-$(CONFIG_PFC_MICRO_SUPPORT_CARD) += support_card.o diff --git a/arch/arm/include/asm/arch-at91/at91_shdwn.h b/arch/arm/include/asm/arch-at91/at91_shdwn.h deleted file mode 100644 index 18d9ea6..0000000 --- a/arch/arm/include/asm/arch-at91/at91_shdwn.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (C) 2010 - * Reinhard Meyer, reinhard.meyer@emk-elektronik.de - * - * Shutdown Controller - * Based on AT91SAM9XE datasheet - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#ifndef AT91_SHDWN_H -#define AT91_SHDWN_H - -#ifndef __ASSEMBLY__ - -struct at91_shdwn { - u32 cr; /* Control Rer. WO */ - u32 mr; /* Mode Register RW 0x00000003 */ - u32 sr; /* Status Register RO 0x00000000 */ -}; - -#endif /* __ASSEMBLY__ */ - -#define AT91_SHDW_CR_KEY 0xa5000000 -#define AT91_SHDW_CR_SHDW 0x00000001 - -#define AT91_SHDW_MR_RTTWKEN 0x00010000 -#define AT91_SHDW_MR_CPTWK0 0x000000f0 -#define AT91_SHDW_MR_WKMODE0H2L 0x00000002 -#define AT91_SHDW_MR_WKMODE0L2H 0x00000001 - -#define AT91_SHDW_SR_RTTWK 0x00010000 -#define AT91_SHDW_SR_WAKEUP0 0x00000001 - -#endif diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index ba71714..78aceef 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -29,6 +29,8 @@ #define EXYNOS4_MIU_BASE 0x10600000 #define EXYNOS4_ACE_SFR_BASE 0x10830000 #define EXYNOS4_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4_GPIO_PART2_0 0x11000000 /* GPJ0 */ +#define EXYNOS4_GPIO_PART2_1 0x11000c00 /* GPX0 */ #define EXYNOS4_GPIO_PART1_BASE 0x11400000 #define EXYNOS4_FIMD_BASE 0x11C00000 #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 @@ -70,7 +72,14 @@ #define EXYNOS4X12_GPIO_PART4_BASE 0x106E0000 #define EXYNOS4X12_ACE_SFR_BASE 0x10830000 #define EXYNOS4X12_GPIO_PART2_BASE 0x11000000 +#define EXYNOS4X12_GPIO_PART2_0 0x11000000 +#define EXYNOS4X12_GPIO_PART2_1 0x11000040 /* GPK0 */ +#define EXYNOS4X12_GPIO_PART2_2 0x11000260 /* GPM0 */ +#define EXYNOS4X12_GPIO_PART2_3 0x11000c00 /* GPX0 */ #define EXYNOS4X12_GPIO_PART1_BASE 0x11400000 +#define EXYNOS4X12_GPIO_PART1_0 0x11400000 /* GPA0 */ +#define EXYNOS4X12_GPIO_PART1_1 0x11400180 /* GPF0 */ +#define EXYNOS4X12_GPIO_PART1_2 0x11400240 /* GPJ0 */ #define EXYNOS4X12_FIMD_BASE 0x11C00000 #define EXYNOS4X12_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4X12_USBOTG_BASE 0x12480000 diff --git a/arch/arm/include/asm/arch-exynos/gpio.h b/arch/arm/include/asm/arch-exynos/gpio.h index ad2ece6..02287de 100644 --- a/arch/arm/include/asm/arch-exynos/gpio.h +++ b/arch/arm/include/asm/arch-exynos/gpio.h @@ -284,7 +284,10 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_Y65, EXYNOS4_GPIO_Y66, EXYNOS4_GPIO_Y67, - EXYNOS4_GPIO_X00, /* 256 0x100 */ + + /* GPIO_PART2_1 STARTS */ + EXYNOS4_GPIO_MAX_PORT_PART_2_0, /* 256 0x100 */ + EXYNOS4_GPIO_X00 = EXYNOS4_GPIO_MAX_PORT_PART_2_0, EXYNOS4_GPIO_X01, EXYNOS4_GPIO_X02, EXYNOS4_GPIO_X03, @@ -318,8 +321,8 @@ enum exynos4_gpio_pin { EXYNOS4_GPIO_X37, /* GPIO_PART3_STARTS */ - EXYNOS4_GPIO_MAX_PORT_PART_2, /* 288 0x120 */ - EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2, + EXYNOS4_GPIO_MAX_PORT_PART_2_1, /* 288 0x120 */ + EXYNOS4_GPIO_Z0 = EXYNOS4_GPIO_MAX_PORT_PART_2_1, EXYNOS4_GPIO_Z1, EXYNOS4_GPIO_Z2, EXYNOS4_GPIO_Z3, @@ -332,7 +335,7 @@ enum exynos4_gpio_pin { }; enum exynos4X12_gpio_pin { - /* GPIO_PART1_STARTS */ + /* EXYNOS4X12_GPIO_PART1_0 starts here */ EXYNOS4X12_GPIO_A00, /* 0 */ EXYNOS4X12_GPIO_A01, EXYNOS4X12_GPIO_A02, @@ -389,7 +392,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_D15, EXYNOS4X12_GPIO_D16, EXYNOS4X12_GPIO_D17, - EXYNOS4X12_GPIO_F00, /* 56 0x38 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, /* 56 0x38 */ + /* EXYNOS4X12_GPIO_PART1_1 starts here */ + EXYNOS4X12_GPIO_F00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_0, EXYNOS4X12_GPIO_F01, EXYNOS4X12_GPIO_F02, EXYNOS4X12_GPIO_F03, @@ -421,7 +426,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_F35, EXYNOS4X12_GPIO_F36, EXYNOS4X12_GPIO_F37, - EXYNOS4X12_GPIO_J00, /* 88 0x58 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, /* 88 0x58 */ + /* EXYNOS4X12_GPIO_PART1_2 starts here */ + EXYNOS4X12_GPIO_J00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_1, EXYNOS4X12_GPIO_J01, EXYNOS4X12_GPIO_J02, EXYNOS4X12_GPIO_J03, @@ -438,9 +445,12 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_J16, EXYNOS4X12_GPIO_J17, - /* GPIO_PART2_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_1,/* 104 0x66 */ - EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1, + /** + * EXYNOS4X12_GPIO_PART2_0 is not used + * EXYNOS4X12_GPIO_PART2_1 starts here + */ + EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, /* 104 0x66 */ + EXYNOS4X12_GPIO_K00 = EXYNOS4X12_GPIO_MAX_PORT_PART_1_2, EXYNOS4X12_GPIO_K01, EXYNOS4X12_GPIO_K02, EXYNOS4X12_GPIO_K03, @@ -552,7 +562,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Y65, EXYNOS4X12_GPIO_Y66, EXYNOS4X12_GPIO_Y67, - EXYNOS4X12_GPIO_M00, /* 216 0xd8 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, /* 216 0xd8 */ + /* EXYNOS4X12_GPIO_PART2_2 starts here */ + EXYNOS4X12_GPIO_M00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_1, EXYNOS4X12_GPIO_M01, EXYNOS4X12_GPIO_M02, EXYNOS4X12_GPIO_M03, @@ -592,7 +604,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_M45, EXYNOS4X12_GPIO_M46, EXYNOS4X12_GPIO_M47, - EXYNOS4X12_GPIO_X00, /* 256 0x100 */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, /* 256 0x100 */ + /* EXYNOS4X12_GPIO_PART2_3 starts here */ + EXYNOS4X12_GPIO_X00 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_2, EXYNOS4X12_GPIO_X01, EXYNOS4X12_GPIO_X02, EXYNOS4X12_GPIO_X03, @@ -625,9 +639,9 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_X36, EXYNOS4X12_GPIO_X37, - /* GPIO_PART3_STARTS */ - EXYNOS4X12_GPIO_MAX_PORT_PART_2,/* 288 0x120 */ - EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2, + /* EXYNOS4X12_GPIO_PART3 starts here */ + EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, /* 288 0x120 */ + EXYNOS4X12_GPIO_Z0 = EXYNOS4X12_GPIO_MAX_PORT_PART_2_3, EXYNOS4X12_GPIO_Z1, EXYNOS4X12_GPIO_Z2, EXYNOS4X12_GPIO_Z3, @@ -636,7 +650,7 @@ enum exynos4X12_gpio_pin { EXYNOS4X12_GPIO_Z6, EXYNOS4X12_GPIO_Z7, - /* GPIO_PART4_STARTS */ + /* EXYNOS4X12_GPIO_PART4 starts here */ EXYNOS4X12_GPIO_MAX_PORT_PART_3,/* 296 0x128 */ EXYNOS4X12_GPIO_V00 = EXYNOS4X12_GPIO_MAX_PORT_PART_3, EXYNOS4X12_GPIO_V01, @@ -1339,17 +1353,22 @@ struct gpio_info { unsigned int max_gpio; /* Maximum GPIO in this part */ }; -#define EXYNOS4_GPIO_NUM_PARTS 3 +#define EXYNOS4_GPIO_NUM_PARTS 4 static struct gpio_info exynos4_gpio_data[EXYNOS4_GPIO_NUM_PARTS] = { { EXYNOS4_GPIO_PART1_BASE, EXYNOS4_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4_GPIO_PART2_BASE, EXYNOS4_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4_GPIO_PART2_0, EXYNOS4_GPIO_MAX_PORT_PART_2_0 }, + { EXYNOS4_GPIO_PART2_1, EXYNOS4_GPIO_MAX_PORT_PART_2_1 }, { EXYNOS4_GPIO_PART3_BASE, EXYNOS4_GPIO_MAX_PORT }, }; -#define EXYNOS4X12_GPIO_NUM_PARTS 4 +#define EXYNOS4X12_GPIO_NUM_PARTS 8 static struct gpio_info exynos4x12_gpio_data[EXYNOS4X12_GPIO_NUM_PARTS] = { - { EXYNOS4X12_GPIO_PART1_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_1 }, - { EXYNOS4X12_GPIO_PART2_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_2 }, + { EXYNOS4X12_GPIO_PART1_0, EXYNOS4X12_GPIO_MAX_PORT_PART_1_0 }, + { EXYNOS4X12_GPIO_PART1_1, EXYNOS4X12_GPIO_MAX_PORT_PART_1_1 }, + { EXYNOS4X12_GPIO_PART1_2, EXYNOS4X12_GPIO_MAX_PORT_PART_1_2 }, + { EXYNOS4X12_GPIO_PART2_1, EXYNOS4X12_GPIO_MAX_PORT_PART_2_1 }, + { EXYNOS4X12_GPIO_PART2_2, EXYNOS4X12_GPIO_MAX_PORT_PART_2_2 }, + { EXYNOS4X12_GPIO_PART2_3, EXYNOS4X12_GPIO_MAX_PORT_PART_2_3 }, { EXYNOS4X12_GPIO_PART3_BASE, EXYNOS4X12_GPIO_MAX_PORT_PART_3 }, { EXYNOS4X12_GPIO_PART4_BASE, EXYNOS4X12_GPIO_MAX_PORT }, }; diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig index 9b72bab..4991da2 100644 --- a/arch/mips/Kconfig +++ b/arch/mips/Kconfig @@ -4,6 +4,10 @@ menu "MIPS architecture" config SYS_ARCH default "mips" +config SYS_CPU + default "mips32" if CPU_MIPS32_R1 || CPU_MIPS32_R2 + default "mips64" if CPU_MIPS64_R1 || CPU_MIPS64_R2 + config USE_PRIVATE_LIBGCC default y @@ -12,21 +16,39 @@ choice config TARGET_QEMU_MIPS bool "Support qemu-mips" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 + select SUPPORTS_CPU_MIPS64_R1 + select SUPPORTS_CPU_MIPS64_R2 config TARGET_MALTA bool "Support malta" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 config TARGET_VCT bool "Support vct" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 config TARGET_DBAU1X00 bool "Support dbau1x00" + select SUPPORTS_BIG_ENDIAN + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 config TARGET_PB1X00 bool "Support pb1x00" + select SUPPORTS_LITTLE_ENDIAN + select SUPPORTS_CPU_MIPS32_R1 + select SUPPORTS_CPU_MIPS32_R2 -config TARGET_QEMU_MIPS64 - bool "Support qemu-mips64" endchoice @@ -36,4 +58,88 @@ source "board/micronas/vct/Kconfig" source "board/pb1x00/Kconfig" source "board/qemu-mips/Kconfig" +if MIPS + +choice + prompt "Endianness selection" + help + Some MIPS boards can be configured for either little or big endian + byte order. These modes require different U-Boot images. In general there + is one preferred byteorder for a particular system but some systems are + just as commonly used in the one or the other endianness. + +config SYS_BIG_ENDIAN + bool "Big endian" + depends on SUPPORTS_BIG_ENDIAN + +config SYS_LITTLE_ENDIAN + bool "Little endian" + depends on SUPPORTS_LITTLE_ENDIAN + +endchoice + +choice + prompt "CPU selection" + default CPU_MIPS32_R2 + +config CPU_MIPS32_R1 + bool "MIPS32 Release 1" + depends on SUPPORTS_CPU_MIPS32_R1 + select 32BIT + help + Choose this option to build an U-Boot for release 1 or later of the + MIPS32 architecture. + +config CPU_MIPS32_R2 + bool "MIPS32 Release 2" + depends on SUPPORTS_CPU_MIPS32_R2 + select 32BIT + help + Choose this option to build an U-Boot for release 2 or later of the + MIPS32 architecture. + +config CPU_MIPS64_R1 + bool "MIPS64 Release 1" + depends on SUPPORTS_CPU_MIPS64_R1 + select 64BIT + help + Choose this option to build a kernel for release 1 or later of the + MIPS64 architecture. + +config CPU_MIPS64_R2 + bool "MIPS64 Release 2" + depends on SUPPORTS_CPU_MIPS64_R2 + select 64BIT + help + Choose this option to build a kernel for release 2 or later of the + MIPS64 architecture. + +endchoice + +config SUPPORTS_BIG_ENDIAN + bool + +config SUPPORTS_LITTLE_ENDIAN + bool + +config SUPPORTS_CPU_MIPS32_R1 + bool + +config SUPPORTS_CPU_MIPS32_R2 + bool + +config SUPPORTS_CPU_MIPS64_R1 + bool + +config SUPPORTS_CPU_MIPS64_R2 + bool + +config 32BIT + bool + +config 64BIT + bool + +endif + endmenu diff --git a/arch/mips/config.mk b/arch/mips/config.mk index a2d07af..4dc88f4 100644 --- a/arch/mips/config.mk +++ b/arch/mips/config.mk @@ -5,25 +5,41 @@ # SPDX-License-Identifier: GPL-2.0+ # -ifeq ($(CROSS_COMPILE),) -CROSS_COMPILE := mips_4KC- +ifdef CONFIG_SYS_BIG_ENDIAN +32bit-emul := elf32btsmip +64bit-emul := elf64btsmip +32bit-bfd := elf32-tradbigmips +64bit-bfd := elf64-tradbigmips +PLATFORM_CPPFLAGS += -EB +PLATFORM_LDFLAGS += -EB endif -# Handle special prefix in ELDK 4.0 toolchain -ifneq (,$(findstring 4KCle,$(CROSS_COMPILE))) -ENDIANNESS := -EL +ifdef CONFIG_SYS_LITTLE_ENDIAN +32bit-emul := elf32ltsmip +64bit-emul := elf64ltsmip +32bit-bfd := elf32-tradlittlemips +64bit-bfd := elf64-tradlittlemips +PLATFORM_CPPFLAGS += -EL +PLATFORM_LDFLAGS += -EL endif -ifdef CONFIG_SYS_LITTLE_ENDIAN -ENDIANNESS := -EL +ifdef CONFIG_32BIT +PLATFORM_CPPFLAGS += -mabi=32 +PLATFORM_LDFLAGS += -m $(32bit-emul) +OBJCOPYFLAGS += -O $(32bit-bfd) endif -ifdef CONFIG_SYS_BIG_ENDIAN -ENDIANNESS := -EB +ifdef CONFIG_64BIT +PLATFORM_CPPFLAGS += -mabi=64 +PLATFORM_LDFLAGS += -m$(64bit-emul) +OBJCOPYFLAGS += -O $(64bit-bfd) endif -# Default to EB if no endianess is configured -ENDIANNESS ?= -EB +cpuflags-$(CONFIG_CPU_MIPS32_R1) += -march=mips32 -Wa,-mips32 +cpuflags-$(CONFIG_CPU_MIPS32_R2) += -march=mips32r2 -Wa,-mips32r2 +cpuflags-$(CONFIG_CPU_MIPS64_R1) += -march=mips64 -Wa,-mips64 +cpuflags-$(CONFIG_CPU_MIPS64_R2) += -march=mips64r2 -Wa,-mips64r2 +PLATFORM_CPPFLAGS += $(cpuflags-y) PLATFORM_CPPFLAGS += -D__MIPS__ @@ -49,10 +65,10 @@ __HAVE_ARCH_GENERIC_BOARD := y # On the other hand, we want PIC in the U-Boot code to relocate it from ROM # to RAM. $28 is always used as gp. # -PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic $(ENDIANNESS) +PLATFORM_CPPFLAGS += -G 0 -mabicalls -fpic PLATFORM_CPPFLAGS += -msoft-float -PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib $(ENDIANNESS) +PLATFORM_LDFLAGS += -G 0 -static -n -nostdlib PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections LDFLAGS_FINAL += --gc-sections -pie OBJCOPYFLAGS += -j .text -j .rodata -j .data -j .got -OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn +OBJCOPYFLAGS += -j .u_boot_list -j .rel.dyn -j .padding diff --git a/arch/mips/cpu/mips32/config.mk b/arch/mips/cpu/mips32/config.mk index 332cd62..4257c56 100644 --- a/arch/mips/cpu/mips32/config.mk +++ b/arch/mips/cpu/mips32/config.mk @@ -5,19 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# -# Default optimization level for MIPS32 -# -# Note: Toolchains with binutils prior to v2.16 -# are no longer supported by U-Boot MIPS tree! -# -PLATFORM_CPPFLAGS += -DCONFIG_MIPS32 -march=mips32r2 -PLATFORM_CPPFLAGS += -mabi=32 -DCONFIG_32BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf32btsmip -else -PLATFORM_LDFLAGS += -m elf32ltsmip -endif - CONFIG_STANDALONE_LOAD_ADDR ?= 0x80200000 \ -T $(srctree)/examples/standalone/mips.lds diff --git a/arch/mips/cpu/mips64/config.mk b/arch/mips/cpu/mips64/config.mk index c55eb7f..96eb829 100644 --- a/arch/mips/cpu/mips64/config.mk +++ b/arch/mips/cpu/mips64/config.mk @@ -5,19 +5,5 @@ # SPDX-License-Identifier: GPL-2.0+ # -# -# Default optimization level for MIPS64 -# -# Note: Toolchains with binutils prior to v2.16 -# are no longer supported by U-Boot MIPS tree! -# -PLATFORM_CPPFLAGS += -DCONFIG_MIPS64 -march=mips64 -PLATFORM_CPPFLAGS += -mabi=64 -DCONFIG_64BIT -ifdef CONFIG_SYS_BIG_ENDIAN -PLATFORM_LDFLAGS += -m elf64btsmip -else -PLATFORM_LDFLAGS += -m elf64ltsmip -endif - CONFIG_STANDALONE_LOAD_ADDR ?= 0xffffffff80200000 \ -T $(srctree)/examples/standalone/mips64.lds diff --git a/arch/mips/cpu/u-boot.lds b/arch/mips/cpu/u-boot.lds index e504ea7..7d71c11 100644 --- a/arch/mips/cpu/u-boot.lds +++ b/arch/mips/cpu/u-boot.lds @@ -61,6 +61,24 @@ SECTIONS __rel_dyn_end = .; } + .padding : { + /* + * Workaround for a binutils feature (or bug?). + * + * The GNU ld from binutils puts the dynamic relocation + * entries into the .rel.dyn section. Sometimes it + * allocates more dynamic relocation entries than it needs + * and the unused slots are set to R_MIPS_NONE entries. + * + * However the size of the .rel.dyn section in the ELF + * section header does not cover the unused entries, so + * objcopy removes those during stripping. + * + * Create a small section here to avoid that. + */ + LONG(0xFFFFFFFF) + } + _end = .; .bss __rel_dyn_start (OVERLAY) : { diff --git a/arch/powerpc/cpu/mpc5xxx/Kconfig b/arch/powerpc/cpu/mpc5xxx/Kconfig index a1305bc..c1fb92a 100644 --- a/arch/powerpc/cpu/mpc5xxx/Kconfig +++ b/arch/powerpc/cpu/mpc5xxx/Kconfig @@ -56,9 +56,6 @@ config TARGET_TOTAL5200 config TARGET_V38B bool "Support v38b" -config TARGET_TOP5200 - bool "Support TOP5200" - config TARGET_CPCI5200 bool "Support cpci5200" diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig index 011f4b4..e447748e 100644 --- a/arch/powerpc/cpu/mpc8xx/Kconfig +++ b/arch/powerpc/cpu/mpc8xx/Kconfig @@ -40,9 +40,6 @@ config TARGET_RRVISION config TARGET_SPD823TS bool "Support SPD823TS" -config TARGET_TOP860 - bool "Support TOP860" - config TARGET_KUP4K bool "Support KUP4K" diff --git a/arch/sparc/Kconfig b/arch/sparc/Kconfig index 733334f..2df09b2 100644 --- a/arch/sparc/Kconfig +++ b/arch/sparc/Kconfig @@ -1,29 +1,56 @@ menu "SPARC architecture" depends on SPARC -config SYS_ARCH - default "sparc" +config LEON + bool + +config LEON2 + bool + select LEON + +config LEON3 + bool + select LEON choice - prompt "Target select" + prompt "Board select" config TARGET_GRSIM_LEON2 - bool "Support grsim_leon2" + bool "GRSIM simulating a LEON2 board" + select LEON2 config TARGET_GR_CPCI_AX2000 - bool "Support gr_cpci_ax2000" + bool "Gaisler GR-CPCI-AX2000 board" + select LEON3 config TARGET_GR_EP2S60 - bool "Support gr_ep2s60" + bool "Gaisler Template design for Altera NIOS board with Stratix EP2S60" + select LEON3 + help + Gaisler Research AB's Template design (GPL Open Source SPARC/LEON3 + 96MHz) for Altera NIOS Development board Stratix II edition, + with the FPGA device EP2S60. config TARGET_GR_XC3S_1500 - bool "Support gr_xc3s_1500" + bool "Gaisler GR-XC3S-1500 spartan board" + select LEON3 config TARGET_GRSIM - bool "Support grsim" + bool "GRSIM simulating a LEON3 GR-XC3S-1500 board" + select LEON3 endchoice +config SYS_ARCH + default "sparc" + +config SYS_CPU + default "leon2" if LEON2 + default "leon3" if LEON3 + +config SYS_VENDOR + default "gaisler" + source "board/gaisler/gr_cpci_ax2000/Kconfig" source "board/gaisler/gr_ep2s60/Kconfig" source "board/gaisler/gr_xc3s_1500/Kconfig" diff --git a/arch/sparc/config.mk b/arch/sparc/config.mk index 196d28a..d615f29 100644 --- a/arch/sparc/config.mk +++ b/arch/sparc/config.mk @@ -15,3 +15,5 @@ CONFIG_STANDALONE_LOAD_ADDR ?= 0x00000000 -L $(gcclibdir) \ -T $(srctree)/examples/standalone/sparc.lds PLATFORM_CPPFLAGS += -D__sparc__ + +PLATFORM_RELFLAGS += -fPIC diff --git a/arch/sparc/cpu/leon2/config.mk b/arch/sparc/cpu/leon2/config.mk deleted file mode 100644 index c44b093..0000000 --- a/arch/sparc/cpu/leon2/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fPIC - -PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON2 diff --git a/arch/sparc/cpu/leon3/config.mk b/arch/sparc/cpu/leon3/config.mk deleted file mode 100644 index ca6c9b1..0000000 --- a/arch/sparc/cpu/leon3/config.mk +++ /dev/null @@ -1,10 +0,0 @@ -# -# (C) Copyright 2003 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -PLATFORM_RELFLAGS += -fPIC - -PLATFORM_CPPFLAGS += -DCONFIG_LEON -DCONFIG_LEON3 diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index e7bb3e3..9d38ef7 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -10,4 +10,4 @@ extra-y = start.o obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o -obj-y += interrupts.o cpu.o +obj-y += interrupts.o cpu.o call64.o diff --git a/arch/x86/cpu/call64.S b/arch/x86/cpu/call64.S new file mode 100644 index 0000000..74dd5a8 --- /dev/null +++ b/arch/x86/cpu/call64.S @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2014 Google, Inc + * Copyright (C) 1991, 1992, 1993 Linus Torvalds + * + * Parts of this copied from Linux arch/x86/boot/compressed/head_64.S + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/global_data.h> +#include <asm/msr-index.h> +#include <asm/processor-flags.h> + +.code32 +.globl cpu_call64 +cpu_call64: + /* + * cpu_call64(ulong pgtable, ulong setup_base, ulong target) + * + * eax - pgtable + * edx - setup_base + * ecx - target + */ + cli + push %ecx /* arg2 = target */ + push %edx /* arg1 = setup_base */ + mov %eax, %ebx + + /* Load new GDT with the 64bit segments using 32bit descriptor */ + leal gdt, %eax + movl %eax, gdt+2 + lgdt gdt + + /* Enable PAE mode */ + movl $(X86_CR4_PAE), %eax + movl %eax, %cr4 + + /* Enable the boot page tables */ + leal (%ebx), %eax + movl %eax, %cr3 + + /* Enable Long mode in EFER (Extended Feature Enable Register) */ + movl $MSR_EFER, %ecx + rdmsr + btsl $_EFER_LME, %eax + wrmsr + + /* After gdt is loaded */ + xorl %eax, %eax + lldt %ax + movl $0x20, %eax + ltr %ax + + /* + * Setup for the jump to 64bit mode + * + * When the jump is performed we will be in long mode but + * in 32bit compatibility mode with EFER.LME = 1, CS.L = 0, CS.D = 1 + * (and in turn EFER.LMA = 1). To jump into 64bit mode we use + * the new gdt/idt that has __KERNEL_CS with CS.L = 1. + * We place all of the values on our mini stack so lret can + * used to perform that far jump. See the gdt below. + */ + pop %esi /* setup_base */ + + pushl $0x10 + leal lret_target, %eax + pushl %eax + + /* Enter paged protected Mode, activating Long Mode */ + movl $(X86_CR0_PG | X86_CR0_PE), %eax + movl %eax, %cr0 + + /* Jump from 32bit compatibility mode into 64bit mode. */ + lret + +code64: +lret_target: + pop %eax /* target */ + mov %eax, %eax /* Clear bits 63:32 */ + jmp *%eax /* Jump to the 64-bit target */ + + .data +gdt: + .word gdt_end - gdt + .long gdt + .word 0 + .quad 0x0000000000000000 /* NULL descriptor */ + .quad 0x00af9a000000ffff /* __KERNEL_CS */ + .quad 0x00cf92000000ffff /* __KERNEL_DS */ + .quad 0x0080890000000000 /* TS descriptor */ + .quad 0x0000000000000000 /* TS continued */ +gdt_end: diff --git a/arch/x86/cpu/cpu.c b/arch/x86/cpu/cpu.c index 623e3af..2e25253 100644 --- a/arch/x86/cpu/cpu.c +++ b/arch/x86/cpu/cpu.c @@ -18,7 +18,10 @@ #include <common.h> #include <command.h> +#include <errno.h> +#include <malloc.h> #include <asm/control_regs.h> +#include <asm/cpu.h> #include <asm/processor.h> #include <asm/processor-flags.h> #include <asm/interrupt.h> @@ -240,3 +243,144 @@ int icache_status(void) { return 1; } + +void cpu_enable_paging_pae(ulong cr3) +{ + __asm__ __volatile__( + /* Load the page table address */ + "movl %0, %%cr3\n" + /* Enable pae */ + "movl %%cr4, %%eax\n" + "orl $0x00000020, %%eax\n" + "movl %%eax, %%cr4\n" + /* Enable paging */ + "movl %%cr0, %%eax\n" + "orl $0x80000000, %%eax\n" + "movl %%eax, %%cr0\n" + : + : "r" (cr3) + : "eax"); +} + +void cpu_disable_paging_pae(void) +{ + /* Turn off paging */ + __asm__ __volatile__ ( + /* Disable paging */ + "movl %%cr0, %%eax\n" + "andl $0x7fffffff, %%eax\n" + "movl %%eax, %%cr0\n" + /* Disable pae */ + "movl %%cr4, %%eax\n" + "andl $0xffffffdf, %%eax\n" + "movl %%eax, %%cr4\n" + : + : + : "eax"); +} + +static bool has_cpuid(void) +{ + unsigned long flag; + + asm volatile("pushf\n" \ + "pop %%eax\n" + "mov %%eax, %%ecx\n" /* ecx = flags */ + "xor %1, %%eax\n" + "push %%eax\n" + "popf\n" /* flags ^= $2 */ + "pushf\n" + "pop %%eax\n" /* eax = flags */ + "push %%ecx\n" + "popf\n" /* flags = ecx */ + "xor %%ecx, %%eax\n" + "mov %%eax, %0" + : "=r" (flag) + : "i" (1 << 21) + : "eax", "ecx", "memory"); + + return flag != 0; +} + +static bool can_detect_long_mode(void) +{ + unsigned long flag; + + asm volatile("mov $0x80000000, %%eax\n" + "cpuid\n" + "mov %%eax, %0" + : "=r" (flag) + : + : "eax", "ebx", "ecx", "edx", "memory"); + + return flag > 0x80000000UL; +} + +static bool has_long_mode(void) +{ + unsigned long flag; + + asm volatile("mov $0x80000001, %%eax\n" + "cpuid\n" + "mov %%edx, %0" + : "=r" (flag) + : + : "eax", "ebx", "ecx", "edx", "memory"); + + return flag & (1 << 29) ? true : false; +} + +int cpu_has_64bit(void) +{ + return has_cpuid() && can_detect_long_mode() && + has_long_mode(); +} + +int print_cpuinfo(void) +{ + printf("CPU: %s\n", cpu_has_64bit() ? "x86_64" : "x86"); + + return 0; +} + +#define PAGETABLE_SIZE (6 * 4096) + +/** + * build_pagetable() - build a flat 4GiB page table structure for 64-bti mode + * + * @pgtable: Pointer to a 24iKB block of memory + */ +static void build_pagetable(uint32_t *pgtable) +{ + uint i; + + memset(pgtable, '\0', PAGETABLE_SIZE); + + /* Level 4 needs a single entry */ + pgtable[0] = (uint32_t)&pgtable[1024] + 7; + + /* Level 3 has one 64-bit entry for each GiB of memory */ + for (i = 0; i < 4; i++) { + pgtable[1024 + i * 2] = (uint32_t)&pgtable[2048] + + 0x1000 * i + 7; + } + + /* Level 2 has 2048 64-bit entries, each repesenting 2MiB */ + for (i = 0; i < 2048; i++) + pgtable[2048 + i * 2] = 0x183 + (i << 21UL); +} + +int cpu_jump_to_64bit(ulong setup_base, ulong target) +{ + uint32_t *pgtable; + + pgtable = memalign(4096, PAGETABLE_SIZE); + if (!pgtable) + return -ENOMEM; + + build_pagetable(pgtable); + cpu_call64((ulong)pgtable, setup_base, target); + free(pgtable); + + return -EFAULT; +} diff --git a/arch/x86/include/asm/bootm.h b/arch/x86/include/asm/bootm.h index 033ab79..f6a64ce 100644 --- a/arch/x86/include/asm/bootm.h +++ b/arch/x86/include/asm/bootm.h @@ -9,4 +9,20 @@ void bootm_announce_and_cleanup(void); +/** + * boot_linux_kernel() - boot a linux kernel + * + * This boots a kernel image, either 32-bit or 64-bit. It will also work with + * a self-extracting kernel, if you set @image_64bit to false. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @load_address: Pointer to the start of the kernel image + * @image_64bit: true if the image is a raw 64-bit kernel, false if it + * is raw 32-bit or any type of self-extracting kernel + * such as a bzImage. + * @return -ve error code. This function does not return if the kernel was + * booted successfully. + */ +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit); + #endif diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h new file mode 100644 index 0000000..6c6774a --- /dev/null +++ b/arch/x86/include/asm/cpu.h @@ -0,0 +1,55 @@ +/* + * Copyright (c) 2014 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __X86_CPU_H +#define __X86_CPU_H + + /** + * cpu_enable_paging_pae() - Enable PAE-paging + * + * @pdpt: Value to set in cr3 (PDPT or PML4T) + */ +void cpu_enable_paging_pae(ulong cr3); + +/** + * cpu_disable_paging_pae() - Disable paging and PAE + */ +void cpu_disable_paging_pae(void); + +/** + * cpu_has_64bit() - Check if the CPU has 64-bit support + * + * @return 1 if this CPU supports long mode (64-bit), 0 if not + */ +int cpu_has_64bit(void); + +/** + * cpu_call64() - Jump to a 64-bit Linux kernel (internal function) + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * This function is used internally - see cpu_jump_to_64bit() for a more + * useful function. + * + * @pgtable: Address of 24KB area containing the page table + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +void cpu_call64(ulong pgtable, ulong setup_base, ulong target); + +/** + * cpu_jump_to_64bit() - Jump to a 64-bit Linux kernel + * + * The kernel is uncompressed and the 64-bit entry point is expected to be + * at @target. + * + * @setup_base: Pointer to the setup.bin information for the kernel + * @target: Pointer to the start of the kernel image + */ +int cpu_jump_to_64bit(ulong setup_base, ulong target); + +#endif diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h index 0a36e17..6027d59 100644 --- a/arch/x86/include/asm/msr-index.h +++ b/arch/x86/include/asm/msr-index.h @@ -44,12 +44,16 @@ #define MSR_IA32_PERFCTR0 0x000000c1 #define MSR_IA32_PERFCTR1 0x000000c2 #define MSR_FSB_FREQ 0x000000cd +#define MSR_NHM_PLATFORM_INFO 0x000000ce #define MSR_NHM_SNB_PKG_CST_CFG_CTL 0x000000e2 #define NHM_C3_AUTO_DEMOTE (1UL << 25) #define NHM_C1_AUTO_DEMOTE (1UL << 26) #define ATM_LNC_C6_AUTO_DEMOTE (1UL << 25) +#define SNB_C1_AUTO_UNDEMOTE (1UL << 27) +#define SNB_C3_AUTO_UNDEMOTE (1UL << 28) +#define MSR_PLATFORM_INFO 0x000000ce #define MSR_MTRRcap 0x000000fe #define MSR_IA32_BBL_CR_CTL 0x00000119 #define MSR_IA32_BBL_CR_CTL3 0x0000011e @@ -64,10 +68,20 @@ #define MSR_OFFCORE_RSP_0 0x000001a6 #define MSR_OFFCORE_RSP_1 0x000001a7 +#define MSR_NHM_TURBO_RATIO_LIMIT 0x000001ad +#define MSR_IVT_TURBO_RATIO_LIMIT 0x000001ae + +#define MSR_LBR_SELECT 0x000001c8 +#define MSR_LBR_TOS 0x000001c9 +#define MSR_LBR_NHM_FROM 0x00000680 +#define MSR_LBR_NHM_TO 0x000006c0 +#define MSR_LBR_CORE_FROM 0x00000040 +#define MSR_LBR_CORE_TO 0x00000060 #define MSR_IA32_PEBS_ENABLE 0x000003f1 #define MSR_IA32_DS_AREA 0x00000600 #define MSR_IA32_PERF_CAPABILITIES 0x00000345 +#define MSR_PEBS_LD_LAT_THRESHOLD 0x000003f6 #define MSR_MTRRfix64K_00000 0x00000250 #define MSR_MTRRfix16K_80000 0x00000258 @@ -91,7 +105,8 @@ #define MSR_IA32_LASTINTTOIP 0x000001de /* DEBUGCTLMSR bits (others vary by model): */ -#define DEBUGCTLMSR_LBR (1UL << 0) +#define DEBUGCTLMSR_LBR (1UL << 0) /* last branch recording */ +/* single-step on branches */ #define DEBUGCTLMSR_BTF (1UL << 1) #define DEBUGCTLMSR_TR (1UL << 6) #define DEBUGCTLMSR_BTS (1UL << 7) @@ -100,11 +115,50 @@ #define DEBUGCTLMSR_BTS_OFF_USR (1UL << 10) #define DEBUGCTLMSR_FREEZE_LBRS_ON_PMI (1UL << 11) +#define MSR_IA32_POWER_CTL 0x000001fc + #define MSR_IA32_MC0_CTL 0x00000400 #define MSR_IA32_MC0_STATUS 0x00000401 #define MSR_IA32_MC0_ADDR 0x00000402 #define MSR_IA32_MC0_MISC 0x00000403 +/* C-state Residency Counters */ +#define MSR_PKG_C3_RESIDENCY 0x000003f8 +#define MSR_PKG_C6_RESIDENCY 0x000003f9 +#define MSR_PKG_C7_RESIDENCY 0x000003fa +#define MSR_CORE_C3_RESIDENCY 0x000003fc +#define MSR_CORE_C6_RESIDENCY 0x000003fd +#define MSR_CORE_C7_RESIDENCY 0x000003fe +#define MSR_PKG_C2_RESIDENCY 0x0000060d +#define MSR_PKG_C8_RESIDENCY 0x00000630 +#define MSR_PKG_C9_RESIDENCY 0x00000631 +#define MSR_PKG_C10_RESIDENCY 0x00000632 + +/* Run Time Average Power Limiting (RAPL) Interface */ + +#define MSR_RAPL_POWER_UNIT 0x00000606 + +#define MSR_PKG_POWER_LIMIT 0x00000610 +#define MSR_PKG_ENERGY_STATUS 0x00000611 +#define MSR_PKG_PERF_STATUS 0x00000613 +#define MSR_PKG_POWER_INFO 0x00000614 + +#define MSR_DRAM_POWER_LIMIT 0x00000618 +#define MSR_DRAM_ENERGY_STATUS 0x00000619 +#define MSR_DRAM_PERF_STATUS 0x0000061b +#define MSR_DRAM_POWER_INFO 0x0000061c + +#define MSR_PP0_POWER_LIMIT 0x00000638 +#define MSR_PP0_ENERGY_STATUS 0x00000639 +#define MSR_PP0_POLICY 0x0000063a +#define MSR_PP0_PERF_STATUS 0x0000063b + +#define MSR_PP1_POWER_LIMIT 0x00000640 +#define MSR_PP1_ENERGY_STATUS 0x00000641 +#define MSR_PP1_POLICY 0x00000642 + +#define MSR_CORE_C1_RES 0x00000660 + #define MSR_AMD64_MC0_MASK 0xc0010044 #define MSR_IA32_MCx_CTL(x) (MSR_IA32_MC0_CTL + 4*(x)) @@ -123,18 +177,31 @@ #define MSR_P6_EVNTSEL0 0x00000186 #define MSR_P6_EVNTSEL1 0x00000187 +#define MSR_KNC_PERFCTR0 0x00000020 +#define MSR_KNC_PERFCTR1 0x00000021 +#define MSR_KNC_EVNTSEL0 0x00000028 +#define MSR_KNC_EVNTSEL1 0x00000029 + +/* Alternative perfctr range with full access. */ +#define MSR_IA32_PMC0 0x000004c1 + /* AMD64 MSRs. Not complete. See the architecture manual for a more complete list. */ #define MSR_AMD64_PATCH_LEVEL 0x0000008b +#define MSR_AMD64_TSC_RATIO 0xc0000104 #define MSR_AMD64_NB_CFG 0xc001001f #define MSR_AMD64_PATCH_LOADER 0xc0010020 #define MSR_AMD64_OSVW_ID_LENGTH 0xc0010140 #define MSR_AMD64_OSVW_STATUS 0xc0010141 +#define MSR_AMD64_LS_CFG 0xc0011020 #define MSR_AMD64_DC_CFG 0xc0011022 +#define MSR_AMD64_BU_CFG2 0xc001102a #define MSR_AMD64_IBSFETCHCTL 0xc0011030 #define MSR_AMD64_IBSFETCHLINAD 0xc0011031 #define MSR_AMD64_IBSFETCHPHYSAD 0xc0011032 +#define MSR_AMD64_IBSFETCH_REG_COUNT 3 +#define MSR_AMD64_IBSFETCH_REG_MASK ((1UL<<MSR_AMD64_IBSFETCH_REG_COUNT)-1) #define MSR_AMD64_IBSOPCTL 0xc0011033 #define MSR_AMD64_IBSOPRIP 0xc0011034 #define MSR_AMD64_IBSOPDATA 0xc0011035 @@ -142,12 +209,21 @@ #define MSR_AMD64_IBSOPDATA3 0xc0011037 #define MSR_AMD64_IBSDCLINAD 0xc0011038 #define MSR_AMD64_IBSDCPHYSAD 0xc0011039 +#define MSR_AMD64_IBSOP_REG_COUNT 7 +#define MSR_AMD64_IBSOP_REG_MASK ((1UL<<MSR_AMD64_IBSOP_REG_COUNT)-1) #define MSR_AMD64_IBSCTL 0xc001103a #define MSR_AMD64_IBSBRTARGET 0xc001103b +#define MSR_AMD64_IBS_REG_COUNT_MAX 8 /* includes MSR_AMD64_IBSBRTARGET */ + +/* Fam 16h MSRs */ +#define MSR_F16H_L2I_PERF_CTL 0xc0010230 +#define MSR_F16H_L2I_PERF_CTR 0xc0010231 /* Fam 15h MSRs */ #define MSR_F15H_PERF_CTL 0xc0010200 #define MSR_F15H_PERF_CTR 0xc0010201 +#define MSR_F15H_NB_PERF_CTL 0xc0010240 +#define MSR_F15H_NB_PERF_CTR 0xc0010241 /* Fam 10h MSRs */ #define MSR_FAM10H_MMIO_CONF_BASE 0xc0010058 @@ -226,7 +302,9 @@ #define MSR_IA32_PLATFORM_ID 0x00000017 #define MSR_IA32_EBL_CR_POWERON 0x0000002a #define MSR_EBC_FREQUENCY_ID 0x0000002c +#define MSR_SMI_COUNT 0x00000034 #define MSR_IA32_FEATURE_CONTROL 0x0000003a +#define MSR_IA32_TSC_ADJUST 0x0000003b #define FEATURE_CONTROL_LOCKED (1<<0) #define FEATURE_CONTROL_VMXON_ENABLED_INSIDE_SMX (1<<1) @@ -237,11 +315,16 @@ #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_BASE (0xfffff<<12) +#define MSR_IA32_TSCDEADLINE 0x000006e0 + #define MSR_IA32_UCODE_WRITE 0x00000079 #define MSR_IA32_UCODE_REV 0x0000008b #define MSR_IA32_PERF_STATUS 0x00000198 #define MSR_IA32_PERF_CTL 0x00000199 +#define MSR_AMD_PSTATE_DEF_BASE 0xc0010064 +#define MSR_AMD_PERF_STATUS 0xc0010063 +#define MSR_AMD_PERF_CTL 0xc0010062 #define MSR_IA32_MPERF 0x000000e7 #define MSR_IA32_APERF 0x000000e8 @@ -267,6 +350,9 @@ #define MSR_IA32_TEMPERATURE_TARGET 0x000001a2 #define MSR_IA32_ENERGY_PERF_BIAS 0x000001b0 +#define ENERGY_PERF_BIAS_PERFORMANCE 0 +#define ENERGY_PERF_BIAS_NORMAL 6 +#define ENERGY_PERF_BIAS_POWERSAVE 15 #define MSR_IA32_PACKAGE_THERM_STATUS 0x000001b1 @@ -320,6 +406,8 @@ #define MSR_IA32_MISC_ENABLE_TURBO_DISABLE (1ULL << 38) #define MSR_IA32_MISC_ENABLE_IP_PREF_DISABLE (1ULL << 39) +#define MSR_IA32_TSC_DEADLINE 0x000006E0 + /* P4/Xeon+ specific */ #define MSR_IA32_MCG_EAX 0x00000180 #define MSR_IA32_MCG_EBX 0x00000181 @@ -446,7 +534,23 @@ #define MSR_IA32_VMX_VMCS_ENUM 0x0000048a #define MSR_IA32_VMX_PROCBASED_CTLS2 0x0000048b #define MSR_IA32_VMX_EPT_VPID_CAP 0x0000048c - +#define MSR_IA32_VMX_TRUE_PINBASED_CTLS 0x0000048d +#define MSR_IA32_VMX_TRUE_PROCBASED_CTLS 0x0000048e +#define MSR_IA32_VMX_TRUE_EXIT_CTLS 0x0000048f +#define MSR_IA32_VMX_TRUE_ENTRY_CTLS 0x00000490 +#define MSR_IA32_VMX_VMFUNC 0x00000491 + +/* VMX_BASIC bits and bitmasks */ +#define VMX_BASIC_VMCS_SIZE_SHIFT 32 +#define VMX_BASIC_64 0x0001000000000000LLU +#define VMX_BASIC_MEM_TYPE_SHIFT 50 +#define VMX_BASIC_MEM_TYPE_MASK 0x003c000000000000LLU +#define VMX_BASIC_MEM_TYPE_WB 6LLU +#define VMX_BASIC_INOUT 0x0040000000000000LLU + +/* MSR_IA32_VMX_MISC bits */ +#define MSR_IA32_VMX_MISC_VMWRITE_SHADOW_RO_FIELDS (1ULL << 29) +#define MSR_IA32_VMX_MISC_PREEMPTION_TIMER_SCALE 0x1F /* AMD-V MSRs */ #define MSR_VM_CR 0xc0010114 diff --git a/arch/x86/include/asm/zimage.h b/arch/x86/include/asm/zimage.h index 0f36662..8e7dd42 100644 --- a/arch/x86/include/asm/zimage.h +++ b/arch/x86/include/asm/zimage.h @@ -35,10 +35,8 @@ unsigned install_e820_map(unsigned max_entries, struct e820entry *); struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address); + ulong *load_addressp); int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, unsigned long initrd_addr, unsigned long initrd_size); -void boot_zimage(void *setup_base, void *load_address); - #endif diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index 4c5c7f5..86030cf 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -10,10 +10,12 @@ #include <common.h> #include <command.h> +#include <errno.h> #include <fdt_support.h> #include <image.h> #include <u-boot/zlib.h> #include <asm/bootparam.h> +#include <asm/cpu.h> #include <asm/byteorder.h> #include <asm/zimage.h> #ifdef CONFIG_SYS_COREBOOT @@ -109,17 +111,17 @@ static int boot_prep_linux(bootm_headers_t *images) } if (is_zimage) { - void *load_address; + ulong load_address; char *base_ptr; base_ptr = (char *)load_zimage(data, len, &load_address); - images->os.load = (ulong)load_address; + images->os.load = load_address; cmd_line_dest = base_ptr + COMMAND_LINE_OFFSET; images->ep = (ulong)base_ptr; } else if (images->ep) { cmd_line_dest = (void *)images->ep + COMMAND_LINE_OFFSET; } else { - printf("## Kernel loading failed (no setup) ...\n"); + printf("## Kernel loading failed (missing x86 kernel setup) ...\n"); goto error; } @@ -139,16 +141,50 @@ error: return 1; } +int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) +{ + bootm_announce_and_cleanup(); + +#ifdef CONFIG_SYS_COREBOOT + timestamp_add_now(TS_U_BOOT_START_KERNEL); +#endif + if (image_64bit) { + if (!cpu_has_64bit()) { + puts("Cannot boot 64-bit kernel on 32-bit machine\n"); + return -EFAULT; + } + return cpu_jump_to_64bit(setup_base, load_address); + } else { + /* + * Set %ebx, %ebp, and %edi to 0, %esi to point to the + * boot_params structure, and then jump to the kernel. We + * assume that %cs is 0x10, 4GB flat, and read/execute, and + * the data segments are 0x18, 4GB flat, and read/write. + * U-boot is setting them up that way for itself in + * arch/i386/cpu/cpu.c. + */ + __asm__ __volatile__ ( + "movl $0, %%ebp\n" + "cli\n" + "jmp *%[kernel_entry]\n" + :: [kernel_entry]"a"(load_address), + [boot_params] "S"(setup_base), + "b"(0), "D"(0) + ); + } + + /* We can't get to here */ + return -EFAULT; +} + /* Subcommand: GO */ static int boot_jump_linux(bootm_headers_t *images) { debug("## Transferring control to Linux (at address %08lx, kernel %08lx) ...\n", images->ep, images->os.load); - boot_zimage((struct boot_params *)images->ep, (void *)images->os.load); - /* does not return */ - - return 1; + return boot_linux_kernel(images->ep, images->os.load, + images->os.arch == IH_ARCH_X86_64); } int do_bootm_linux(int flag, int argc, char * const argv[], @@ -161,10 +197,8 @@ int do_bootm_linux(int flag, int argc, char * const argv[], if (flag & BOOTM_STATE_OS_PREP) return boot_prep_linux(images); - if (flag & BOOTM_STATE_OS_GO) { - boot_jump_linux(images); - return 0; - } + if (flag & BOOTM_STATE_OS_GO) + return boot_jump_linux(images); return boot_jump_linux(images); } diff --git a/arch/x86/lib/physmem.c b/arch/x86/lib/physmem.c index b57b2c3..c3c709e 100644 --- a/arch/x86/lib/physmem.c +++ b/arch/x86/lib/physmem.c @@ -10,6 +10,7 @@ #include <common.h> #include <physmem.h> +#include <asm/cpu.h> #include <linux/compiler.h> DECLARE_GLOBAL_DATA_PTR; @@ -112,41 +113,13 @@ static void x86_phys_enter_paging(void) x86_phys_map_page(page_addr, page_addr, 0); } - /* Turn on paging */ - __asm__ __volatile__( - /* Load the page table address */ - "movl %0, %%cr3\n\t" - /* Enable pae */ - "movl %%cr4, %%eax\n\t" - "orl $0x00000020, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - /* Enable paging */ - "movl %%cr0, %%eax\n\t" - "orl $0x80000000, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - : - : "r" (pdpt) - : "eax" - ); + cpu_enable_paging_pae((ulong)pdpt); } /* Disable paging and PAE mode. */ static void x86_phys_exit_paging(void) { - /* Turn off paging */ - __asm__ __volatile__ ( - /* Disable paging */ - "movl %%cr0, %%eax\n\t" - "andl $0x7fffffff, %%eax\n\t" - "movl %%eax, %%cr0\n\t" - /* Disable pae */ - "movl %%cr4, %%eax\n\t" - "andl $0xffffffdf, %%eax\n\t" - "movl %%eax, %%cr4\n\t" - : - : - : "eax" - ); + cpu_disable_paging_pae(); } /* diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index b190283..566b048 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -103,7 +103,7 @@ static int get_boot_protocol(struct setup_header *hdr) } struct boot_params *load_zimage(char *image, unsigned long kernel_size, - void **load_address) + ulong *load_addressp) { struct boot_params *setup_base; int setup_size; @@ -155,9 +155,9 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, /* Determine load address */ if (big_image) - *load_address = (void *)BZIMAGE_LOAD_ADDR; + *load_addressp = BZIMAGE_LOAD_ADDR; else - *load_address = (void *)ZIMAGE_LOAD_ADDR; + *load_addressp = ZIMAGE_LOAD_ADDR; printf("Building boot_params at 0x%8.8lx\n", (ulong)setup_base); memset(setup_base, 0, sizeof(*setup_base)); @@ -204,10 +204,10 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, return 0; } - printf("Loading %s at address %p (%ld bytes)\n", - big_image ? "bzImage" : "zImage", *load_address, kernel_size); + printf("Loading %s at address %lx (%ld bytes)\n", + big_image ? "bzImage" : "zImage", *load_addressp, kernel_size); - memmove(*load_address, image + setup_size, kernel_size); + memmove((void *)*load_addressp, image + setup_size, kernel_size); return setup_base; } @@ -261,30 +261,6 @@ int setup_zimage(struct boot_params *setup_base, char *cmd_line, int auto_boot, return 0; } -void boot_zimage(void *setup_base, void *load_address) -{ - bootm_announce_and_cleanup(); - -#ifdef CONFIG_SYS_COREBOOT - timestamp_add_now(TS_U_BOOT_START_KERNEL); -#endif - /* - * Set %ebx, %ebp, and %edi to 0, %esi to point to the boot_params - * structure, and then jump to the kernel. We assume that %cs is - * 0x10, 4GB flat, and read/execute, and the data segments are 0x18, - * 4GB flat, and read/write. U-boot is setting them up that way for - * itself in arch/i386/cpu/cpu.c. - */ - __asm__ __volatile__ ( - "movl $0, %%ebp\n" - "cli\n" - "jmp *%[kernel_entry]\n" - :: [kernel_entry]"a"(load_address), - [boot_params] "S"(setup_base), - "b"(0), "D"(0) - ); -} - void setup_pcat_compatibility(void) __attribute__((weak, alias("__setup_pcat_compatibility"))); @@ -296,7 +272,7 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) { struct boot_params *base_ptr; void *bzImage_addr = NULL; - void *load_address; + ulong load_address; char *s; ulong bzImage_size = 0; ulong initrd_addr = 0; @@ -331,20 +307,17 @@ int do_zboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]) base_ptr = load_zimage(bzImage_addr, bzImage_size, &load_address); if (!base_ptr) { - printf("## Kernel loading failed ...\n"); + puts("## Kernel loading failed ...\n"); return -1; } if (setup_zimage(base_ptr, (char *)base_ptr + COMMAND_LINE_OFFSET, 0, initrd_addr, initrd_size)) { - printf("Setting up boot parameters failed ...\n"); + puts("Setting up boot parameters failed ...\n"); return -1; } /* we assume that the kernel is in place */ - boot_zimage(base_ptr, load_address); - /* does not return */ - - return -1; + return boot_linux_kernel((ulong)base_ptr, load_address, false); } U_BOOT_CMD( diff --git a/board/dbau1x00/Kconfig b/board/dbau1x00/Kconfig index 1a8946d..1286e45 100644 --- a/board/dbau1x00/Kconfig +++ b/board/dbau1x00/Kconfig @@ -1,8 +1,5 @@ if TARGET_DBAU1X00 -config SYS_CPU - default "mips32" - config SYS_BOARD default "dbau1x00" @@ -12,4 +9,22 @@ config SYS_SOC config SYS_CONFIG_NAME default "dbau1x00" +menu "dbau1x00 board options" + +choice + prompt "Select au1x00 SoC type" + +config DBAU1100 + bool "Select AU1100" + +config DBAU1500 + bool "Select AU1500" + +config DBAU1550 + bool "Select AU1550" + +endchoice + +endmenu + endif diff --git a/board/gaisler/gr_cpci_ax2000/Kconfig b/board/gaisler/gr_cpci_ax2000/Kconfig index 8da0504..c12a002 100644 --- a/board/gaisler/gr_cpci_ax2000/Kconfig +++ b/board/gaisler/gr_cpci_ax2000/Kconfig @@ -1,14 +1,8 @@ if TARGET_GR_CPCI_AX2000 -config SYS_CPU - default "leon3" - config SYS_BOARD default "gr_cpci_ax2000" -config SYS_VENDOR - default "gaisler" - config SYS_CONFIG_NAME default "gr_cpci_ax2000" diff --git a/board/gaisler/gr_cpci_ax2000/config.mk b/board/gaisler/gr_cpci_ax2000/config.mk deleted file mode 100644 index 731a539..0000000 --- a/board/gaisler/gr_cpci_ax2000/config.mk +++ /dev/null @@ -1,19 +0,0 @@ -# -# (C) Copyright 2008 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GR-CPCI-AX2000 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM or SDRAM with -nosram flag set when starting GRMON -#CONFIG_SYS_TEXT_BASE = 0x40000000 - -# U-BOOT IN SDRAM -#CONFIG_SYS_TEXT_BASE = 0x60000000 diff --git a/board/gaisler/gr_ep2s60/Kconfig b/board/gaisler/gr_ep2s60/Kconfig index 00b2097..f49937c 100644 --- a/board/gaisler/gr_ep2s60/Kconfig +++ b/board/gaisler/gr_ep2s60/Kconfig @@ -1,14 +1,8 @@ if TARGET_GR_EP2S60 -config SYS_CPU - default "leon3" - config SYS_BOARD default "gr_ep2s60" -config SYS_VENDOR - default "gaisler" - config SYS_CONFIG_NAME default "gr_ep2s60" diff --git a/board/gaisler/gr_ep2s60/config.mk b/board/gaisler/gr_ep2s60/config.mk deleted file mode 100644 index 6e01f07..0000000 --- a/board/gaisler/gr_ep2s60/config.mk +++ /dev/null @@ -1,17 +0,0 @@ -# -# (C) Copyright 2008 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# Altera NIOS delopment board Stratix II edition, FPGA device EP2S60, -# with GRLIB Template design (GPL Open Source SPARC/LEON3) -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN SDRAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 diff --git a/board/gaisler/gr_xc3s_1500/Kconfig b/board/gaisler/gr_xc3s_1500/Kconfig index 765e028..e695ba2 100644 --- a/board/gaisler/gr_xc3s_1500/Kconfig +++ b/board/gaisler/gr_xc3s_1500/Kconfig @@ -1,14 +1,8 @@ if TARGET_GR_XC3S_1500 -config SYS_CPU - default "leon3" - config SYS_BOARD default "gr_xc3s_1500" -config SYS_VENDOR - default "gaisler" - config SYS_CONFIG_NAME default "gr_xc3s_1500" diff --git a/board/gaisler/gr_xc3s_1500/config.mk b/board/gaisler/gr_xc3s_1500/config.mk deleted file mode 100644 index e4a66cb..0000000 --- a/board/gaisler/gr_xc3s_1500/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GR-XC3S-1500 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 diff --git a/board/gaisler/grsim/Kconfig b/board/gaisler/grsim/Kconfig index 751fa03..18598d3 100644 --- a/board/gaisler/grsim/Kconfig +++ b/board/gaisler/grsim/Kconfig @@ -1,14 +1,8 @@ if TARGET_GRSIM -config SYS_CPU - default "leon3" - config SYS_BOARD default "grsim" -config SYS_VENDOR - default "gaisler" - config SYS_CONFIG_NAME default "grsim" diff --git a/board/gaisler/grsim/config.mk b/board/gaisler/grsim/config.mk deleted file mode 100644 index d1f61da..0000000 --- a/board/gaisler/grsim/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GRSIM simulating a LEON3 GR-XC3S-1500 board -# - -# U-BOOT IN FLASH -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# U-BOOT IN RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 diff --git a/board/gaisler/grsim_leon2/Kconfig b/board/gaisler/grsim_leon2/Kconfig index 0907f3a..0d21a0a 100644 --- a/board/gaisler/grsim_leon2/Kconfig +++ b/board/gaisler/grsim_leon2/Kconfig @@ -1,14 +1,8 @@ if TARGET_GRSIM_LEON2 -config SYS_CPU - default "leon2" - config SYS_BOARD default "grsim_leon2" -config SYS_VENDOR - default "gaisler" - config SYS_CONFIG_NAME default "grsim_leon2" diff --git a/board/gaisler/grsim_leon2/config.mk b/board/gaisler/grsim_leon2/config.mk deleted file mode 100644 index f98b23b..0000000 --- a/board/gaisler/grsim_leon2/config.mk +++ /dev/null @@ -1,16 +0,0 @@ -# -# (C) Copyright 2007 -# Daniel Hellstrom, Gaisler Research, daniel@gaisler.com -# -# SPDX-License-Identifier: GPL-2.0+ -# - -# -# GRSIM simulating a LEON2 board -# - -# RUN U-BOOT FROM PROM -CONFIG_SYS_TEXT_BASE = 0x00000000 - -# RUN U-BOOT FROM RAM -#CONFIG_SYS_TEXT_BASE = 0x40000000 diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig index 401962c..4c06d0c 100644 --- a/board/imgtec/malta/Kconfig +++ b/board/imgtec/malta/Kconfig @@ -1,8 +1,5 @@ if TARGET_MALTA -config SYS_CPU - default "mips32" - config SYS_BOARD default "malta" diff --git a/board/kosagi/novena/MAINTAINERS b/board/kosagi/novena/MAINTAINERS new file mode 100644 index 0000000..d3471c2 --- /dev/null +++ b/board/kosagi/novena/MAINTAINERS @@ -0,0 +1,6 @@ +NOVENA BOARD +M: Marek Vasut <marex@denx.de> +S: Maintained +F: board/kosagi/novena/ +F: include/configs/novena.h +F: configs/novena_defconfig diff --git a/board/matrix_vision/common/Makefile b/board/matrix_vision/common/Makefile deleted file mode 100644 index 699da1c..0000000 --- a/board/matrix_vision/common/Makefile +++ /dev/null @@ -1,8 +0,0 @@ -# -# (C) Copyright 2006 -# Wolfgang Denk, DENX Software Engineering, wd@denx.de. -# -# SPDX-License-Identifier: GPL-2.0+ -# - -obj-y = mv_common.o diff --git a/board/matrix_vision/common/mv_common.c b/board/matrix_vision/common/mv_common.c deleted file mode 100644 index 1be5aba..0000000 --- a/board/matrix_vision/common/mv_common.c +++ /dev/null @@ -1,112 +0,0 @@ -/* - * (C) Copyright 2008 - * Andre Schwarz, Matrix Vision GmbH, andre.schwarz@matrix-vision.de - * - * SPDX-License-Identifier: GPL-2.0+ - */ - -#include <common.h> -#include <malloc.h> -#include <environment.h> -#include <fpga.h> -#include <asm/io.h> - -DECLARE_GLOBAL_DATA_PTR; - -#ifndef CONFIG_ENV_IS_NOWHERE -static char* entries_to_keep[] = { - "serial#", "ethaddr", "eth1addr", "model_info", "sensor_cnt", - "fpgadatasize", "ddr_size", "use_dhcp", "use_static_ipaddr", - "static_ipaddr", "static_netmask", "static_gateway", - "syslog", "watchdog", "netboot", "evo8serialnumber" }; - -#define MV_MAX_ENV_ENTRY_LENGTH 64 -#define MV_KEEP_ENTRIES ARRAY_SIZE(entries_to_keep) - -void mv_reset_environment(void) -{ - int i; - char *s[MV_KEEP_ENTRIES]; - char entries[MV_KEEP_ENTRIES][MV_MAX_ENV_ENTRY_LENGTH]; - - printf("\n*** RESET ENVIRONMENT ***\n"); - - memset(entries, 0, MV_KEEP_ENTRIES * MV_MAX_ENV_ENTRY_LENGTH); - for (i = 0; i < MV_KEEP_ENTRIES; i++) { - s[i] = getenv(entries_to_keep[i]); - if (s[i]) { - printf("save '%s' : %s\n", entries_to_keep[i], s[i]); - strncpy(entries[i], s[i], MV_MAX_ENV_ENTRY_LENGTH); - } - } - - gd->env_valid = 0; - env_relocate(); - - for (i = 0; i < MV_KEEP_ENTRIES; i++) { - if (s[i]) { - printf("restore '%s' : %s\n", entries_to_keep[i], s[i]); - setenv(entries_to_keep[i], s[i]); - } - } - - saveenv(); -} -#endif - -int mv_load_fpga(void) -{ - int result; - size_t data_size = 0; - void *fpga_data = NULL; - char *datastr = getenv("fpgadata"); - char *sizestr = getenv("fpgadatasize"); - - if (getenv("skip_fpga")) { - printf("found 'skip_fpga' -> FPGA _not_ loaded !\n"); - return -1; - } - printf("loading FPGA\n"); - - if (datastr) - fpga_data = (void *)simple_strtoul(datastr, NULL, 16); - if (sizestr) - data_size = (size_t)simple_strtoul(sizestr, NULL, 16); - if (!data_size) { - printf("fpgadatasize invalid -> FPGA _not_ loaded !\n"); - return -1; - } - - result = fpga_load(0, fpga_data, data_size, BIT_FULL); - if (!result) - bootstage_mark(BOOTSTAGE_ID_START); - - return result; -} - -u8 *dhcp_vendorex_prep(u8 *e) -{ - char *ptr; - - /* DHCP vendor-class-identifier = 60 */ - if ((ptr = getenv("dhcp_vendor-class-identifier"))) { - *e++ = 60; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - /* DHCP_CLIENT_IDENTIFIER = 61 */ - if ((ptr = getenv("dhcp_client_id"))) { - *e++ = 61; - *e++ = strlen(ptr); - while (*ptr) - *e++ = *ptr++; - } - - return e; -} - -u8 *dhcp_vendorex_proc(u8 *popt) -{ - return NULL; -} diff --git a/board/matrix_vision/common/mv_common.h b/board/matrix_vision/common/mv_common.h deleted file mode 100644 index 3693943..0000000 --- a/board/matrix_vision/common/mv_common.h +++ /dev/null @@ -1,9 +0,0 @@ -/* - * Copyright 2008 Matrix Vision GmbH - * - * SPDX-License-Identifier: GPL-2.0+ - */ - - -extern int mv_load_fpga(void); -extern void mv_reset_environment(void); diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig index 75046fe..288a1ae 100644 --- a/board/micronas/vct/Kconfig +++ b/board/micronas/vct/Kconfig @@ -1,8 +1,5 @@ if TARGET_VCT -config SYS_CPU - default "mips32" - config SYS_BOARD default "vct" @@ -12,4 +9,28 @@ config SYS_VENDOR config SYS_CONFIG_NAME default "vct" +menu "vct board options" + +choice + prompt "Board variant" + +config VCT_PLATINUM + bool "Enable VCT_PLATINUM" + +config VCT_PLATINUMAVC + bool "Enable VCT_PLATINUMAVC" + +config VCT_PREMIUM + bool "Enable VCT_PLATINUMAVC" + +endchoice + +config VCT_ONENAND + bool "Enable VCT_ONENAND" + +config VCT_SMALL_IMAGE + bool "Enable VCT_SMALL_IMAGE" + +endmenu + endif diff --git a/board/pb1x00/Kconfig b/board/pb1x00/Kconfig index ef2844a..251db6a 100644 --- a/board/pb1x00/Kconfig +++ b/board/pb1x00/Kconfig @@ -1,8 +1,5 @@ if TARGET_PB1X00 -config SYS_CPU - default "mips32" - config SYS_BOARD default "pb1x00" diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig index e4d9663..18d78b5 100644 --- a/board/qemu-mips/Kconfig +++ b/board/qemu-mips/Kconfig @@ -1,25 +1,10 @@ if TARGET_QEMU_MIPS -config SYS_CPU - default "mips32" - -config SYS_BOARD - default "qemu-mips" - -config SYS_CONFIG_NAME - default "qemu-mips" - -endif - -if TARGET_QEMU_MIPS64 - -config SYS_CPU - default "mips64" - config SYS_BOARD default "qemu-mips" config SYS_CONFIG_NAME - default "qemu-mips64" + default "qemu-mips" if 32BIT + default "qemu-mips64" if 64BIT endif diff --git a/board/samsung/odroid/odroid.c b/board/samsung/odroid/odroid.c index 5edb250..33003ee 100644 --- a/board/samsung/odroid/odroid.c +++ b/board/samsung/odroid/odroid.c @@ -356,21 +356,29 @@ static void board_clock_init(void) static void board_gpio_init(void) { /* eMMC Reset Pin */ + gpio_request(EXYNOS4X12_GPIO_K12, "eMMC Reset"); + gpio_cfg_pin(EXYNOS4X12_GPIO_K12, S5P_GPIO_FUNC(0x1)); gpio_set_pull(EXYNOS4X12_GPIO_K12, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_K12, S5P_GPIO_DRV_4X); /* Enable FAN (Odroid U3) */ + gpio_request(EXYNOS4X12_GPIO_D00, "FAN Control"); + gpio_set_pull(EXYNOS4X12_GPIO_D00, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_D00, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_D00, 1); /* OTG Vbus output (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_L20, "OTG Vbus"); + gpio_set_pull(EXYNOS4X12_GPIO_L20, S5P_GPIO_PULL_NONE); gpio_set_drv(EXYNOS4X12_GPIO_L20, S5P_GPIO_DRV_4X); gpio_direction_output(EXYNOS4X12_GPIO_L20, 0); /* OTG INT (Odroid U3+) */ + gpio_request(EXYNOS4X12_GPIO_X31, "OTG INT"); + gpio_set_pull(EXYNOS4X12_GPIO_X31, S5P_GPIO_PULL_UP); gpio_set_drv(EXYNOS4X12_GPIO_X31, S5P_GPIO_DRV_4X); gpio_direction_input(EXYNOS4X12_GPIO_X31); @@ -403,7 +411,6 @@ static void board_init_i2c(void) int exynos_early_init_f(void) { board_clock_init(); - board_gpio_init(); return 0; } @@ -414,6 +421,8 @@ int exynos_init(void) gd->ram_size -= SZ_1M; gd->bd->bi_dram[CONFIG_NR_DRAM_BANKS - 1].size -= SZ_1M; + board_gpio_init(); + return 0; } diff --git a/common/bootm.c b/common/bootm.c index 81e3261..6b3ea8c 100644 --- a/common/bootm.c +++ b/common/bootm.c @@ -167,7 +167,8 @@ static int bootm_find_os(cmd_tbl_t *cmdtp, int flag, int argc, } /* If we have a valid setup.bin, we will use that for entry (x86) */ - if (images.os.arch == IH_ARCH_I386) { + if (images.os.arch == IH_ARCH_I386 || + images.os.arch == IH_ARCH_X86_64) { ulong len; ret = boot_get_setup(&images, IH_ARCH_I386, &images.ep, &len); diff --git a/common/image-fit.c b/common/image-fit.c index a272ea2..4ffc5aa 100644 --- a/common/image-fit.c +++ b/common/image-fit.c @@ -1114,7 +1114,8 @@ int fit_image_check_arch(const void *fit, int noffset, uint8_t arch) if (fit_image_get_arch(fit, noffset, &image_arch)) return 0; - return (arch == image_arch); + return (arch == image_arch) || + (arch == IH_ARCH_I386 && image_arch == IH_ARCH_X86_64); } /** diff --git a/common/image.c b/common/image.c index eb92e63..b75a5ce 100644 --- a/common/image.c +++ b/common/image.c @@ -85,6 +85,7 @@ static const table_entry_t uimage_arch[] = { { IH_ARCH_SANDBOX, "sandbox", "Sandbox", }, { IH_ARCH_ARM64, "arm64", "AArch64", }, { IH_ARCH_ARC, "arc", "ARC", }, + { IH_ARCH_X86_64, "x86_64", "AMD x86_64", }, { -1, "", "", }, }; diff --git a/common/stdio.c b/common/stdio.c index 68c595d..adbfc89 100644 --- a/common/stdio.c +++ b/common/stdio.c @@ -197,6 +197,7 @@ int stdio_deregister_dev(struct stdio_dev *dev, int force) } list_del(&(dev->list)); + free(dev); /* reassign Device list */ list_for_each(pos, &(devs.list)) { diff --git a/common/usb.c b/common/usb.c index bd0f8d5..7d33a0f 100644 --- a/common/usb.c +++ b/common/usb.c @@ -927,7 +927,6 @@ int usb_new_device(struct usb_device *dev) * thread_id=5729457&forum_id=5398 */ __maybe_unused struct usb_device_descriptor *desc; - int port = -1; struct usb_device *parent = dev->parent; unsigned short portstatus; @@ -965,24 +964,10 @@ int usb_new_device(struct usb_device *dev) #endif if (parent) { - int j; - - /* find the port number we're at */ - for (j = 0; j < parent->maxchild; j++) { - if (parent->children[j] == dev) { - port = j; - break; - } - } - if (port < 0) { - printf("usb_new_device:cannot locate device's port.\n"); - return 1; - } - /* reset the port for the second time */ - err = hub_port_reset(dev->parent, port, &portstatus); + err = hub_port_reset(dev->parent, dev->portnr - 1, &portstatus); if (err < 0) { - printf("\n Couldn't reset port %i\n", port); + printf("\n Couldn't reset port %i\n", dev->portnr); return 1; } } diff --git a/common/usb_hub.c b/common/usb_hub.c index c416e5e..0f1eab4 100644 --- a/common/usb_hub.c +++ b/common/usb_hub.c @@ -86,50 +86,11 @@ static void usb_hub_power_on(struct usb_hub_device *hub) int i; struct usb_device *dev; unsigned pgood_delay = hub->desc.bPwrOn2PwrGood * 2; - ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1); - unsigned short portstatus; - int ret; dev = hub->pusb_dev; - /* - * Enable power to the ports: - * Here we Power-cycle the ports: aka, - * turning them off and turning on again. - */ debug("enabling power on all ports\n"); for (i = 0; i < dev->maxchild; i++) { - usb_clear_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); - debug("port %d returns %lX\n", i + 1, dev->status); - } - - /* Wait at least 2*bPwrOn2PwrGood for PP to change */ - mdelay(pgood_delay); - - for (i = 0; i < dev->maxchild; i++) { - ret = usb_get_port_status(dev, i + 1, portsts); - if (ret < 0) { - debug("port %d: get_port_status failed\n", i + 1); - continue; - } - - /* - * Check to confirm the state of Port Power: - * xHCI says "After modifying PP, s/w shall read - * PP and confirm that it has reached the desired state - * before modifying it again, undefined behavior may occur - * if this procedure is not followed". - * EHCI doesn't say anything like this, but no harm in keeping - * this. - */ - portstatus = le16_to_cpu(portsts->wPortStatus); - if (portstatus & (USB_PORT_STAT_POWER << 1)) { - debug("port %d: Port power change failed\n", i + 1); - continue; - } - } - - for (i = 0; i < dev->maxchild; i++) { usb_set_port_feature(dev, i + 1, USB_PORT_FEAT_POWER); debug("port %d returns %lX\n", i + 1, dev->status); } diff --git a/common/usb_kbd.c b/common/usb_kbd.c index fdc083c..bc7145e 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -99,6 +99,11 @@ static const unsigned char usb_kbd_arrow[] = { #define USB_KBD_BOOT_REPORT_SIZE 8 struct usb_kbd_pdata { + unsigned long intpipe; + int intpktsize; + int intinterval; + struct int_queue *intq; + uint32_t repeat_delay; uint32_t usb_in_pointer; @@ -116,32 +121,6 @@ extern int __maybe_unused net_busy_flag; /* The period of time between two calls of usb_kbd_testc(). */ static unsigned long __maybe_unused kbd_testc_tms; -/* Generic keyboard event polling. */ -void usb_kbd_generic_poll(void) -{ - struct stdio_dev *dev; - struct usb_device *usb_kbd_dev; - struct usb_kbd_pdata *data; - struct usb_interface *iface; - struct usb_endpoint_descriptor *ep; - int pipe; - int maxp; - - /* Get the pointer to USB Keyboard device pointer */ - dev = stdio_get_by_name(DEVNAME); - usb_kbd_dev = (struct usb_device *)dev->priv; - data = usb_kbd_dev->privptr; - iface = &usb_kbd_dev->config.if_desc[0]; - ep = &iface->ep_desc[0]; - pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); - - /* Submit a interrupt transfer request */ - maxp = usb_maxpacket(usb_kbd_dev, pipe); - usb_submit_int_msg(usb_kbd_dev, pipe, data->new, - min(maxp, USB_KBD_BOOT_REPORT_SIZE), - ep->bInterval); -} - /* Puts character in the queue and sets up the in and out pointer. */ static void usb_kbd_put_queue(struct usb_kbd_pdata *data, char c) { @@ -331,23 +310,11 @@ static int usb_kbd_irq(struct usb_device *dev) static inline void usb_kbd_poll_for_event(struct usb_device *dev) { #if defined(CONFIG_SYS_USB_EVENT_POLL) - struct usb_interface *iface; - struct usb_endpoint_descriptor *ep; - struct usb_kbd_pdata *data; - int pipe; - int maxp; - - /* Get the pointer to USB Keyboard device pointer */ - data = dev->privptr; - iface = &dev->config.if_desc[0]; - ep = &iface->ep_desc[0]; - pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + struct usb_kbd_pdata *data = dev->privptr; /* Submit a interrupt transfer request */ - maxp = usb_maxpacket(dev, pipe); - usb_submit_int_msg(dev, pipe, &data->new[0], - min(maxp, USB_KBD_BOOT_REPORT_SIZE), - ep->bInterval); + usb_submit_int_msg(dev, data->intpipe, &data->new[0], data->intpktsize, + data->intinterval); usb_kbd_irq_worker(dev); #elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP) @@ -358,6 +325,15 @@ static inline void usb_kbd_poll_for_event(struct usb_device *dev) 1, 0, data->new, USB_KBD_BOOT_REPORT_SIZE); if (memcmp(data->old, data->new, USB_KBD_BOOT_REPORT_SIZE)) usb_kbd_irq_worker(dev); +#elif defined(CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE) + struct usb_kbd_pdata *data = dev->privptr; + if (poll_int_queue(dev, data->intq)) { + usb_kbd_irq_worker(dev); + /* We've consumed all queued int packets, create new */ + destroy_int_queue(dev, data->intq); + data->intq = create_int_queue(dev, data->intpipe, 1, + USB_KBD_BOOT_REPORT_SIZE, data->new); + } #endif } @@ -415,7 +391,6 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) struct usb_interface *iface; struct usb_endpoint_descriptor *ep; struct usb_kbd_pdata *data; - int pipe, maxp; if (dev->descriptor.bNumConfigurations != 1) return 0; @@ -464,8 +439,10 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) /* Set IRQ handler */ dev->irq_handle = usb_kbd_irq; - pipe = usb_rcvintpipe(dev, ep->bEndpointAddress); - maxp = usb_maxpacket(dev, pipe); + data->intpipe = usb_rcvintpipe(dev, ep->bEndpointAddress); + data->intpktsize = min(usb_maxpacket(dev, data->intpipe), + USB_KBD_BOOT_REPORT_SIZE); + data->intinterval = ep->bInterval; /* We found a USB Keyboard, install it. */ usb_set_protocol(dev, iface->desc.bInterfaceNumber, 0); @@ -474,9 +451,14 @@ static int usb_kbd_probe(struct usb_device *dev, unsigned int ifnum) usb_set_idle(dev, iface->desc.bInterfaceNumber, REPEAT_RATE, 0); debug("USB KBD: enable interrupt pipe...\n"); - if (usb_submit_int_msg(dev, pipe, data->new, - min(maxp, USB_KBD_BOOT_REPORT_SIZE), - ep->bInterval) < 0) { +#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE + data->intq = create_int_queue(dev, data->intpipe, 1, + USB_KBD_BOOT_REPORT_SIZE, data->new); + if (!data->intq) { +#else + if (usb_submit_int_msg(dev, data->intpipe, data->new, data->intpktsize, + data->intinterval) < 0) { +#endif printf("Failed to get keyboard state from device %04x:%04x\n", dev->descriptor.idVendor, dev->descriptor.idProduct); /* Abort, we don't want to use that non-functional keyboard. */ @@ -550,9 +532,22 @@ int drv_usb_kbd_init(void) int usb_kbd_deregister(int force) { #ifdef CONFIG_SYS_STDIO_DEREGISTER - int ret = stdio_deregister(DEVNAME, force); - if (ret && ret != -ENODEV) - return ret; + struct stdio_dev *dev; + struct usb_device *usb_kbd_dev; + struct usb_kbd_pdata *data; + + dev = stdio_get_by_name(DEVNAME); + if (dev) { + usb_kbd_dev = (struct usb_device *)dev->priv; + data = usb_kbd_dev->privptr; + if (stdio_deregister_dev(dev, force) != 0) + return 1; +#ifdef CONFIG_SYS_USB_EVENT_POLL_VIA_INT_QUEUE + destroy_int_queue(usb_kbd_dev, data->intq); +#endif + free(data->new); + free(data); + } return 0; #else diff --git a/configs/dbau1000_defconfig b/configs/dbau1000_defconfig index 7c95629..aa4d338 100644 --- a/configs/dbau1000_defconfig +++ b/configs/dbau1000_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="DBAU1000" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y diff --git a/configs/dbau1100_defconfig b/configs/dbau1100_defconfig index 506f5da..aac9f03 100644 --- a/configs/dbau1100_defconfig +++ b/configs/dbau1100_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DBAU1100" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1100=y diff --git a/configs/dbau1500_defconfig b/configs/dbau1500_defconfig index 5a02a78..d96de13 100644 --- a/configs/dbau1500_defconfig +++ b/configs/dbau1500_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DBAU1500" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1500=y diff --git a/configs/dbau1550_defconfig b/configs/dbau1550_defconfig index 9015023..a2dfe18 100644 --- a/configs/dbau1550_defconfig +++ b/configs/dbau1550_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DBAU1550" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_DBAU1550=y diff --git a/configs/dbau1550_el_defconfig b/configs/dbau1550_el_defconfig index 53b35ce..767326f 100644 --- a/configs/dbau1550_el_defconfig +++ b/configs/dbau1550_el_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="DBAU1550,SYS_LITTLE_ENDIAN" CONFIG_MIPS=y CONFIG_TARGET_DBAU1X00=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_DBAU1550=y diff --git a/configs/gr_cpci_ax2000_defconfig b/configs/gr_cpci_ax2000_defconfig index 6eb02ad..b59d077 100644 --- a/configs/gr_cpci_ax2000_defconfig +++ b/configs/gr_cpci_ax2000_defconfig @@ -1,2 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_CPCI_AX2000=y diff --git a/configs/gr_ep2s60_defconfig b/configs/gr_ep2s60_defconfig index 6e1eb83..2c69efa 100644 --- a/configs/gr_ep2s60_defconfig +++ b/configs/gr_ep2s60_defconfig @@ -1,2 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_EP2S60=y diff --git a/configs/gr_xc3s_1500_defconfig b/configs/gr_xc3s_1500_defconfig index da846db..fecdd25 100644 --- a/configs/gr_xc3s_1500_defconfig +++ b/configs/gr_xc3s_1500_defconfig @@ -1,2 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GR_XC3S_1500=y diff --git a/configs/grsim_defconfig b/configs/grsim_defconfig index 2a7e8e7..e3ffd69 100644 --- a/configs/grsim_defconfig +++ b/configs/grsim_defconfig @@ -1,2 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GRSIM=y diff --git a/configs/grsim_leon2_defconfig b/configs/grsim_leon2_defconfig index e91eb96..6090e34 100644 --- a/configs/grsim_leon2_defconfig +++ b/configs/grsim_leon2_defconfig @@ -1,2 +1,3 @@ +CONFIG_SYS_TEXT_BASE=0x00000000 CONFIG_SPARC=y CONFIG_TARGET_GRSIM_LEON2=y diff --git a/configs/malta_defconfig b/configs/malta_defconfig index f3788b6..5a178a7 100644 --- a/configs/malta_defconfig +++ b/configs/malta_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN" CONFIG_MIPS=y CONFIG_TARGET_MALTA=y +CONFIG_SYS_BIG_ENDIAN=y diff --git a/configs/maltael_defconfig b/configs/maltael_defconfig index 97d0e89..011525f 100644 --- a/configs/maltael_defconfig +++ b/configs/maltael_defconfig @@ -1,3 +1,3 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN" CONFIG_MIPS=y CONFIG_TARGET_MALTA=y +CONFIG_SYS_LITTLE_ENDIAN=y diff --git a/configs/pb1000_defconfig b/configs/pb1000_defconfig index e226358..72c22a0 100644 --- a/configs/pb1000_defconfig +++ b/configs/pb1000_defconfig @@ -1,3 +1,4 @@ CONFIG_SYS_EXTRA_OPTIONS="PB1000" CONFIG_MIPS=y CONFIG_TARGET_PB1X00=y +CONFIG_SYS_LITTLE_ENDIAN=y diff --git a/configs/qemu_mips64_defconfig b/configs/qemu_mips64_defconfig index 2948355..3608bbe 100644 --- a/configs/qemu_mips64_defconfig +++ b/configs/qemu_mips64_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN" CONFIG_MIPS=y -CONFIG_TARGET_QEMU_MIPS64=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_CPU_MIPS64_R1=y diff --git a/configs/qemu_mips64el_defconfig b/configs/qemu_mips64el_defconfig index 13a039f..a9ebd7b 100644 --- a/configs/qemu_mips64el_defconfig +++ b/configs/qemu_mips64el_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN" CONFIG_MIPS=y -CONFIG_TARGET_QEMU_MIPS64=y +CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS64_R1=y diff --git a/configs/qemu_mips_defconfig b/configs/qemu_mips_defconfig index 6b2c029..f58dd22 100644 --- a/configs/qemu_mips_defconfig +++ b/configs/qemu_mips_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_BIG_ENDIAN" CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y diff --git a/configs/qemu_mipsel_defconfig b/configs/qemu_mipsel_defconfig index 57c8701..84a4511 100644 --- a/configs/qemu_mipsel_defconfig +++ b/configs/qemu_mipsel_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="SYS_LITTLE_ENDIAN" CONFIG_MIPS=y CONFIG_TARGET_QEMU_MIPS=y +CONFIG_SYS_LITTLE_ENDIAN=y +CONFIG_CPU_MIPS32_R2=y diff --git a/configs/vct_platinum_defconfig b/configs/vct_platinum_defconfig index 9ff8b68..32e9e8c 100644 --- a/configs/vct_platinum_defconfig +++ b/configs/vct_platinum_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y diff --git a/configs/vct_platinum_onenand_defconfig b/configs/vct_platinum_onenand_defconfig index f33c97d..4346518 100644 --- a/configs/vct_platinum_onenand_defconfig +++ b/configs/vct_platinum_onenand_defconfig @@ -1,3 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinum_onenand_small_defconfig b/configs/vct_platinum_onenand_small_defconfig index 58c7995..fd52282 100644 --- a/configs/vct_platinum_onenand_small_defconfig +++ b/configs/vct_platinum_onenand_small_defconfig @@ -1,4 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_ONENAND,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinum_small_defconfig b/configs/vct_platinum_small_defconfig index f4f56c4..58f956d 100644 --- a/configs/vct_platinum_small_defconfig +++ b/configs/vct_platinum_small_defconfig @@ -1,4 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUM,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUM=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinumavc_defconfig b/configs/vct_platinumavc_defconfig index 8aaac56..732565c 100644 --- a/configs/vct_platinumavc_defconfig +++ b/configs/vct_platinumavc_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y diff --git a/configs/vct_platinumavc_onenand_defconfig b/configs/vct_platinumavc_onenand_defconfig index 926c6e4..670e7f9 100644 --- a/configs/vct_platinumavc_onenand_defconfig +++ b/configs/vct_platinumavc_onenand_defconfig @@ -1,3 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_platinumavc_onenand_small_defconfig b/configs/vct_platinumavc_onenand_small_defconfig index 31b4c9a..31a4948 100644 --- a/configs/vct_platinumavc_onenand_small_defconfig +++ b/configs/vct_platinumavc_onenand_small_defconfig @@ -1,4 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_ONENAND,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_platinumavc_small_defconfig b/configs/vct_platinumavc_small_defconfig index 23f6561..ce00a6c 100644 --- a/configs/vct_platinumavc_small_defconfig +++ b/configs/vct_platinumavc_small_defconfig @@ -1,4 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PLATINUMAVC,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PLATINUMAVC=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_premium_defconfig b/configs/vct_premium_defconfig index 0e16ff9..a19e65d 100644 --- a/configs/vct_premium_defconfig +++ b/configs/vct_premium_defconfig @@ -1,3 +1,4 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y diff --git a/configs/vct_premium_onenand_defconfig b/configs/vct_premium_onenand_defconfig index 29734b8..092d0f7 100644 --- a/configs/vct_premium_onenand_defconfig +++ b/configs/vct_premium_onenand_defconfig @@ -1,3 +1,5 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_ONENAND=y diff --git a/configs/vct_premium_onenand_small_defconfig b/configs/vct_premium_onenand_small_defconfig index 354793e..eabfb88 100644 --- a/configs/vct_premium_onenand_small_defconfig +++ b/configs/vct_premium_onenand_small_defconfig @@ -1,4 +1,7 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_ONENAND,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_ONENAND=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/configs/vct_premium_small_defconfig b/configs/vct_premium_small_defconfig index a23ddb7..1ce0efd 100644 --- a/configs/vct_premium_small_defconfig +++ b/configs/vct_premium_small_defconfig @@ -1,4 +1,6 @@ -CONFIG_SYS_EXTRA_OPTIONS="VCT_PREMIUM,VCT_SMALL_IMAGE" CONFIG_MIPS=y CONFIG_TARGET_VCT=y +CONFIG_SYS_BIG_ENDIAN=y +CONFIG_VCT_PREMIUM=y +CONFIG_VCT_SMALL_IMAGE=y # CONFIG_CMD_CRC32 is not set diff --git a/doc/SPI/README.altera_spi b/doc/SPI/README.altera_spi new file mode 100644 index 0000000..b07449f --- /dev/null +++ b/doc/SPI/README.altera_spi @@ -0,0 +1,6 @@ +SoCFPGA EPCS/EPCQx1 mini howto: +- Instantiate EPCS/EPCQx1 Serial flash controller in QSys and rebuild +- The controller base address is the "Base" in QSys + 0x400 +- Set MSEL[4:0]=10010 (AS Standard) +- Load the bitstream into FPGA, enable bridges +- Only then will the driver work diff --git a/doc/mkimage.1 b/doc/mkimage.1 index 14374da..b48f70b 100644 --- a/doc/mkimage.1 +++ b/doc/mkimage.1 @@ -115,7 +115,7 @@ FIT image. .TP .BI "\-F" Indicates that an existing FIT image should be modified. No dtc -compilation is performed and the -f flag should not be given. +compilation is performed and the \-f flag should not be given. This can be used to sign images with additional keys after initial image creation. @@ -163,7 +163,8 @@ Create FIT image with compressed kernel and sign it with keys in the skipping those for which keys cannot be found. Also add a comment. .nf .B mkimage -f kernel.its -k /public/signing-keys -K u-boot.dtb \\\\ --c "Kernel 3.8 image for production devices" kernel.itb +.br +.B -c "Kernel 3.8 image for production devices" kernel.itb .fi .P @@ -173,7 +174,8 @@ with keys that are available in the new directory. Images that request signing with unavailable keys are skipped. .nf .B mkimage -F -k /secret/signing-keys -K u-boot.dtb \\\\ --c "Kernel 3.8 image for production devices" kernel.itb +.br +.B -c "Kernel 3.8 image for production devices" kernel.itb .fi .SH HOMEPAGE diff --git a/drivers/i2c/i2c_core.c b/drivers/i2c/i2c_core.c index 18d6736..d34b749 100644 --- a/drivers/i2c/i2c_core.c +++ b/drivers/i2c/i2c_core.c @@ -229,11 +229,9 @@ static void i2c_init_bus(unsigned int bus_no, int speed, int slaveaddr) } /* implement possible board specific board init */ -static void __def_i2c_init_board(void) +__weak void i2c_init_board(void) { } -void i2c_init_board(void) - __attribute__((weak, alias("__def_i2c_init_board"))); /* * i2c_init_all(): @@ -395,9 +393,7 @@ void i2c_reg_write(uint8_t addr, uint8_t reg, uint8_t val) i2c_write(addr, reg, 1, &val, 1); } -void __i2c_init(int speed, int slaveaddr) +__weak void i2c_init(int speed, int slaveaddr) { i2c_init_bus(i2c_get_bus_num(), speed, slaveaddr); } -void i2c_init(int speed, int slaveaddr) - __attribute__((weak, alias("__i2c_init"))); diff --git a/drivers/power/twl4030.c b/drivers/power/twl4030.c index 3e50310..e578ae6 100644 --- a/drivers/power/twl4030.c +++ b/drivers/power/twl4030.c @@ -98,4 +98,10 @@ void twl4030_power_mmc_init(void) TWL4030_PM_RECEIVER_VMMC1_VSEL_32, TWL4030_PM_RECEIVER_VMMC1_DEV_GRP, TWL4030_PM_RECEIVER_DEV_GRP_P1); + + /* Set VMMC2 to 3.15 Volts */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VMMC2_DEDICATED, + TWL4030_PM_RECEIVER_VMMC2_VSEL_32, + TWL4030_PM_RECEIVER_VMMC2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); } diff --git a/drivers/serial/serial.c b/drivers/serial/serial.c index 18e41b2..95c992a 100644 --- a/drivers/serial/serial.c +++ b/drivers/serial/serial.c @@ -109,54 +109,54 @@ U_BOOT_ENV_CALLBACK(baudrate, on_baudrate); void name(void) \ __attribute__((weak, alias("serial_null"))); -serial_initfunc(mpc8xx_serial_initialize); -serial_initfunc(ns16550_serial_initialize); -serial_initfunc(pxa_serial_initialize); -serial_initfunc(s3c24xx_serial_initialize); -serial_initfunc(s5p_serial_initialize); -serial_initfunc(zynq_serial_initialize); -serial_initfunc(bfin_serial_initialize); -serial_initfunc(bfin_jtag_initialize); -serial_initfunc(mpc512x_serial_initialize); -serial_initfunc(uartlite_serial_initialize); -serial_initfunc(au1x00_serial_initialize); -serial_initfunc(asc_serial_initialize); -serial_initfunc(jz_serial_initialize); -serial_initfunc(mpc5xx_serial_initialize); -serial_initfunc(mpc8260_scc_serial_initialize); -serial_initfunc(mpc8260_smc_serial_initialize); -serial_initfunc(mpc85xx_serial_initialize); -serial_initfunc(iop480_serial_initialize); -serial_initfunc(leon2_serial_initialize); -serial_initfunc(leon3_serial_initialize); -serial_initfunc(marvell_serial_initialize); +serial_initfunc(altera_jtag_serial_initialize); +serial_initfunc(altera_serial_initialize); serial_initfunc(amirix_serial_initialize); +serial_initfunc(arc_serial_initialize); +serial_initfunc(arm_dcc_initialize); +serial_initfunc(asc_serial_initialize); +serial_initfunc(atmel_serial_initialize); +serial_initfunc(au1x00_serial_initialize); +serial_initfunc(bfin_jtag_initialize); +serial_initfunc(bfin_serial_initialize); serial_initfunc(bmw_serial_initialize); +serial_initfunc(clps7111_serial_initialize); serial_initfunc(cogent_serial_initialize); serial_initfunc(cpci750_serial_initialize); serial_initfunc(evb64260_serial_initialize); -serial_initfunc(ml2_serial_initialize); -serial_initfunc(sconsole_serial_initialize); -serial_initfunc(p3mx_serial_initialize); -serial_initfunc(altera_jtag_serial_initialize); -serial_initfunc(altera_serial_initialize); -serial_initfunc(atmel_serial_initialize); -serial_initfunc(lpc32xx_serial_initialize); -serial_initfunc(mcf_serial_initialize); -serial_initfunc(oc_serial_initialize); -serial_initfunc(sandbox_serial_initialize); -serial_initfunc(clps7111_serial_initialize); serial_initfunc(imx_serial_initialize); +serial_initfunc(iop480_serial_initialize); +serial_initfunc(jz_serial_initialize); serial_initfunc(ks8695_serial_initialize); +serial_initfunc(leon2_serial_initialize); +serial_initfunc(leon3_serial_initialize); serial_initfunc(lh7a40x_serial_initialize); +serial_initfunc(lpc32xx_serial_initialize); +serial_initfunc(marvell_serial_initialize); serial_initfunc(max3100_serial_initialize); +serial_initfunc(mcf_serial_initialize); +serial_initfunc(ml2_serial_initialize); +serial_initfunc(mpc512x_serial_initialize); +serial_initfunc(mpc5xx_serial_initialize); +serial_initfunc(mpc8260_scc_serial_initialize); +serial_initfunc(mpc8260_smc_serial_initialize); +serial_initfunc(mpc85xx_serial_initialize); +serial_initfunc(mpc8xx_serial_initialize); serial_initfunc(mxc_serial_initialize); +serial_initfunc(mxs_auart_initialize); +serial_initfunc(ns16550_serial_initialize); +serial_initfunc(oc_serial_initialize); +serial_initfunc(p3mx_serial_initialize); serial_initfunc(pl01x_serial_initialize); +serial_initfunc(pxa_serial_initialize); +serial_initfunc(s3c24xx_serial_initialize); +serial_initfunc(s5p_serial_initialize); serial_initfunc(sa1100_serial_initialize); +serial_initfunc(sandbox_serial_initialize); +serial_initfunc(sconsole_serial_initialize); serial_initfunc(sh_serial_initialize); -serial_initfunc(arm_dcc_initialize); -serial_initfunc(mxs_auart_initialize); -serial_initfunc(arc_serial_initialize); +serial_initfunc(uartlite_serial_initialize); +serial_initfunc(zynq_serial_initialize); /** * serial_register() - Register serial driver with serial driver core @@ -202,54 +202,54 @@ void serial_register(struct serial_device *dev) */ void serial_initialize(void) { - mpc8xx_serial_initialize(); - ns16550_serial_initialize(); - pxa_serial_initialize(); - s3c24xx_serial_initialize(); - s5p_serial_initialize(); - mpc512x_serial_initialize(); - bfin_serial_initialize(); - bfin_jtag_initialize(); - uartlite_serial_initialize(); - zynq_serial_initialize(); - au1x00_serial_initialize(); - asc_serial_initialize(); - jz_serial_initialize(); - mpc5xx_serial_initialize(); - mpc8260_scc_serial_initialize(); - mpc8260_smc_serial_initialize(); - mpc85xx_serial_initialize(); - iop480_serial_initialize(); - leon2_serial_initialize(); - leon3_serial_initialize(); - marvell_serial_initialize(); + altera_jtag_serial_initialize(); + altera_serial_initialize(); amirix_serial_initialize(); + arc_serial_initialize(); + arm_dcc_initialize(); + asc_serial_initialize(); + atmel_serial_initialize(); + au1x00_serial_initialize(); + bfin_jtag_initialize(); + bfin_serial_initialize(); bmw_serial_initialize(); + clps7111_serial_initialize(); cogent_serial_initialize(); cpci750_serial_initialize(); evb64260_serial_initialize(); - ml2_serial_initialize(); - sconsole_serial_initialize(); - p3mx_serial_initialize(); - altera_jtag_serial_initialize(); - altera_serial_initialize(); - atmel_serial_initialize(); - lpc32xx_serial_initialize(); - mcf_serial_initialize(); - oc_serial_initialize(); - sandbox_serial_initialize(); - clps7111_serial_initialize(); imx_serial_initialize(); + iop480_serial_initialize(); + jz_serial_initialize(); ks8695_serial_initialize(); + leon2_serial_initialize(); + leon3_serial_initialize(); lh7a40x_serial_initialize(); + lpc32xx_serial_initialize(); + marvell_serial_initialize(); max3100_serial_initialize(); + mcf_serial_initialize(); + ml2_serial_initialize(); + mpc512x_serial_initialize(); + mpc5xx_serial_initialize(); + mpc8260_scc_serial_initialize(); + mpc8260_smc_serial_initialize(); + mpc85xx_serial_initialize(); + mpc8xx_serial_initialize(); mxc_serial_initialize(); + mxs_auart_initialize(); + ns16550_serial_initialize(); + oc_serial_initialize(); + p3mx_serial_initialize(); pl01x_serial_initialize(); + pxa_serial_initialize(); + s3c24xx_serial_initialize(); + s5p_serial_initialize(); sa1100_serial_initialize(); + sandbox_serial_initialize(); + sconsole_serial_initialize(); sh_serial_initialize(); - arm_dcc_initialize(); - mxs_auart_initialize(); - arc_serial_initialize(); + uartlite_serial_initialize(); + zynq_serial_initialize(); serial_assign(default_serial_console()->name); } diff --git a/drivers/serial/serial_uniphier.c b/drivers/serial/serial_uniphier.c index 9114b3e..3f3d415 100644 --- a/drivers/serial/serial_uniphier.c +++ b/drivers/serial/serial_uniphier.c @@ -55,7 +55,7 @@ struct uniphier_serial_private_data { #define uniphier_serial_port(dev) \ ((struct uniphier_serial_private_data *)dev_get_priv(dev))->membase -int uniphier_serial_setbrg(struct udevice *dev, int baudrate) +static int uniphier_serial_setbrg(struct udevice *dev, int baudrate) { struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); struct uniphier_serial __iomem *port = uniphier_serial_port(dev); @@ -93,7 +93,17 @@ static int uniphier_serial_putc(struct udevice *dev, const char c) return 0; } -int uniphier_serial_probe(struct udevice *dev) +static int uniphier_serial_pending(struct udevice *dev, bool input) +{ + struct uniphier_serial __iomem *port = uniphier_serial_port(dev); + + if (input) + return readb(&port->lsr) & UART_LSR_DR; + else + return !(readb(&port->lsr) & UART_LSR_THRE); +} + +static int uniphier_serial_probe(struct udevice *dev) { struct uniphier_serial_private_data *priv = dev_get_priv(dev); struct uniphier_serial_platform_data *plat = dev_get_platdata(dev); @@ -106,7 +116,7 @@ int uniphier_serial_probe(struct udevice *dev) return 0; } -int uniphier_serial_remove(struct udevice *dev) +static int uniphier_serial_remove(struct udevice *dev) { unmap_sysmem(uniphier_serial_port(dev)); @@ -134,6 +144,7 @@ static const struct dm_serial_ops uniphier_serial_ops = { .setbrg = uniphier_serial_setbrg, .getc = uniphier_serial_getc, .putc = uniphier_serial_putc, + .pending = uniphier_serial_pending, }; U_BOOT_DRIVER(uniphier_serial) = { diff --git a/drivers/spi/altera_spi.c b/drivers/spi/altera_spi.c index 5accbb5..a4d03d9 100644 --- a/drivers/spi/altera_spi.c +++ b/drivers/spi/altera_spi.c @@ -12,58 +12,62 @@ #include <malloc.h> #include <spi.h> -#define ALTERA_SPI_RXDATA 0 -#define ALTERA_SPI_TXDATA 4 -#define ALTERA_SPI_STATUS 8 -#define ALTERA_SPI_CONTROL 12 -#define ALTERA_SPI_SLAVE_SEL 20 - -#define ALTERA_SPI_STATUS_ROE_MSK (0x8) -#define ALTERA_SPI_STATUS_TOE_MSK (0x10) -#define ALTERA_SPI_STATUS_TMT_MSK (0x20) -#define ALTERA_SPI_STATUS_TRDY_MSK (0x40) -#define ALTERA_SPI_STATUS_RRDY_MSK (0x80) -#define ALTERA_SPI_STATUS_E_MSK (0x100) - -#define ALTERA_SPI_CONTROL_IROE_MSK (0x8) -#define ALTERA_SPI_CONTROL_ITOE_MSK (0x10) -#define ALTERA_SPI_CONTROL_ITRDY_MSK (0x40) -#define ALTERA_SPI_CONTROL_IRRDY_MSK (0x80) -#define ALTERA_SPI_CONTROL_IE_MSK (0x100) -#define ALTERA_SPI_CONTROL_SSO_MSK (0x400) +#ifndef CONFIG_ALTERA_SPI_IDLE_VAL +#define CONFIG_ALTERA_SPI_IDLE_VAL 0xff +#endif #ifndef CONFIG_SYS_ALTERA_SPI_LIST #define CONFIG_SYS_ALTERA_SPI_LIST { CONFIG_SYS_SPI_BASE } #endif +struct altera_spi_regs { + u32 rxdata; + u32 txdata; + u32 status; + u32 control; + u32 _reserved; + u32 slave_sel; +}; + +#define ALTERA_SPI_STATUS_ROE_MSK (1 << 3) +#define ALTERA_SPI_STATUS_TOE_MSK (1 << 4) +#define ALTERA_SPI_STATUS_TMT_MSK (1 << 5) +#define ALTERA_SPI_STATUS_TRDY_MSK (1 << 6) +#define ALTERA_SPI_STATUS_RRDY_MSK (1 << 7) +#define ALTERA_SPI_STATUS_E_MSK (1 << 8) + +#define ALTERA_SPI_CONTROL_IROE_MSK (1 << 3) +#define ALTERA_SPI_CONTROL_ITOE_MSK (1 << 4) +#define ALTERA_SPI_CONTROL_ITRDY_MSK (1 << 6) +#define ALTERA_SPI_CONTROL_IRRDY_MSK (1 << 7) +#define ALTERA_SPI_CONTROL_IE_MSK (1 << 8) +#define ALTERA_SPI_CONTROL_SSO_MSK (1 << 10) + static ulong altera_spi_base_list[] = CONFIG_SYS_ALTERA_SPI_LIST; struct altera_spi_slave { - struct spi_slave slave; - ulong base; + struct spi_slave slave; + struct altera_spi_regs *regs; }; #define to_altera_spi_slave(s) container_of(s, struct altera_spi_slave, slave) -__attribute__((weak)) -int spi_cs_is_valid(unsigned int bus, unsigned int cs) +__weak int spi_cs_is_valid(unsigned int bus, unsigned int cs) { return bus < ARRAY_SIZE(altera_spi_base_list) && cs < 32; } -__attribute__((weak)) -void spi_cs_activate(struct spi_slave *slave) +__weak void spi_cs_activate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(1 << slave->cs, altspi->base + ALTERA_SPI_SLAVE_SEL); - writel(ALTERA_SPI_CONTROL_SSO_MSK, altspi->base + ALTERA_SPI_CONTROL); + writel(1 << slave->cs, &altspi->regs->slave_sel); + writel(ALTERA_SPI_CONTROL_SSO_MSK, &altspi->regs->control); } -__attribute__((weak)) -void spi_cs_deactivate(struct spi_slave *slave) +__weak void spi_cs_deactivate(struct spi_slave *slave) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); } void spi_init(void) @@ -87,9 +91,8 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!altspi) return NULL; - altspi->base = altera_spi_base_list[bus]; - debug("%s: bus:%i cs:%i base:%lx\n", __func__, - bus, cs, altspi->base); + altspi->regs = (struct altera_spi_regs *)altera_spi_base_list[bus]; + debug("%s: bus:%i cs:%i base:%p\n", __func__, bus, cs, altspi->regs); return &altspi->slave; } @@ -105,8 +108,8 @@ int spi_claim_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_CONTROL); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->control); + writel(0, &altspi->regs->slave_sel); return 0; } @@ -115,24 +118,22 @@ void spi_release_bus(struct spi_slave *slave) struct altera_spi_slave *altspi = to_altera_spi_slave(slave); debug("%s: bus:%i cs:%i\n", __func__, slave->bus, slave->cs); - writel(0, altspi->base + ALTERA_SPI_SLAVE_SEL); + writel(0, &altspi->regs->slave_sel); } -#ifndef CONFIG_ALTERA_SPI_IDLE_VAL -# define CONFIG_ALTERA_SPI_IDLE_VAL 0xff -#endif - int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, void *din, unsigned long flags) { struct altera_spi_slave *altspi = to_altera_spi_slave(slave); /* assume spi core configured to do 8 bit transfers */ - uint bytes = bitlen / 8; - const uchar *txp = dout; - uchar *rxp = din; + unsigned int bytes = bitlen / 8; + const unsigned char *txp = dout; + unsigned char *rxp = din; + uint32_t reg, data, start; debug("%s: bus:%i cs:%i bitlen:%i bytes:%i flags:%lx\n", __func__, - slave->bus, slave->cs, bitlen, bytes, flags); + slave->bus, slave->cs, bitlen, bytes, flags); + if (bitlen == 0) goto done; @@ -142,25 +143,40 @@ int spi_xfer(struct spi_slave *slave, unsigned int bitlen, const void *dout, } /* empty read buffer */ - if (readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK) - readl(altspi->base + ALTERA_SPI_RXDATA); + if (readl(&altspi->regs->status) & ALTERA_SPI_STATUS_RRDY_MSK) + readl(&altspi->regs->rxdata); + if (flags & SPI_XFER_BEGIN) spi_cs_activate(slave); while (bytes--) { - uchar d = txp ? *txp++ : CONFIG_ALTERA_SPI_IDLE_VAL; - debug("%s: tx:%x ", __func__, d); - writel(d, altspi->base + ALTERA_SPI_TXDATA); - while (!(readl(altspi->base + ALTERA_SPI_STATUS) & - ALTERA_SPI_STATUS_RRDY_MSK)) - ; - d = readl(altspi->base + ALTERA_SPI_RXDATA); + if (txp) + data = *txp++; + else + data = CONFIG_ALTERA_SPI_IDLE_VAL; + + debug("%s: tx:%x ", __func__, data); + writel(data, &altspi->regs->txdata); + + start = get_timer(0); + while (1) { + reg = readl(&altspi->regs->status); + if (reg & ALTERA_SPI_STATUS_RRDY_MSK) + break; + if (get_timer(start) > (CONFIG_SYS_HZ / 1000)) { + printf("%s: Transmission timed out!\n", __func__); + goto done; + } + } + + data = readl(&altspi->regs->rxdata); if (rxp) - *rxp++ = d; - debug("rx:%x\n", d); + *rxp++ = data & 0xff; + + debug("rx:%x\n", data); } - done: + +done: if (flags & SPI_XFER_END) spi_cs_deactivate(slave); diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c index be10269..23f2ba6 100644 --- a/drivers/spi/mxc_spi.c +++ b/drivers/spi/mxc_spi.c @@ -49,6 +49,8 @@ struct mxc_spi_slave { #endif int gpio; int ss_pol; + unsigned int max_hz; + unsigned int mode; }; static inline struct mxc_spi_slave *to_mxc_spi_slave(struct spi_slave *slave) @@ -83,12 +85,13 @@ u32 get_cspi_div(u32 div) } #ifdef MXC_CSPI -static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { unsigned int ctrl_reg; u32 clk_src; u32 div; + unsigned int max_hz = mxcs->max_hz; + unsigned int mode = mxcs->mode; clk_src = mxc_get_clock(MXC_CSPI_CLK); @@ -120,19 +123,15 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, #endif #ifdef MXC_ECSPI -static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, - unsigned int max_hz, unsigned int mode) +static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs) { u32 clk_src = mxc_get_clock(MXC_CSPI_CLK); s32 reg_ctrl, reg_config; u32 ss_pol = 0, sclkpol = 0, sclkpha = 0, sclkctl = 0; u32 pre_div = 0, post_div = 0; struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; - - if (max_hz == 0) { - printf("Error: desired clock is 0\n"); - return -1; - } + unsigned int max_hz = mxcs->max_hz; + unsigned int mode = mxcs->mode; /* * Reset SPI and set all CSs to master mode, if toggling @@ -169,9 +168,6 @@ static s32 spi_cfg_mxc(struct mxc_spi_slave *mxcs, unsigned int cs, reg_ctrl = (reg_ctrl & ~MXC_CSPICTRL_POSTDIV(0x0F)) | MXC_CSPICTRL_POSTDIV(post_div); - /* We need to disable SPI before changing registers */ - reg_ctrl &= ~MXC_CSPICTRL_EN; - if (mode & SPI_CS_HIGH) ss_pol = 1; @@ -412,6 +408,11 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (bus >= ARRAY_SIZE(spi_bases)) return NULL; + if (max_hz == 0) { + printf("Error: desired clock is 0\n"); + return NULL; + } + mxcs = spi_alloc_slave(struct mxc_spi_slave, bus, cs); if (!mxcs) { puts("mxc_spi: SPI Slave not allocated !\n"); @@ -427,13 +428,9 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, } mxcs->base = spi_bases[bus]; + mxcs->max_hz = max_hz; + mxcs->mode = mode; - ret = spi_cfg_mxc(mxcs, cs, max_hz, mode); - if (ret) { - printf("mxc_spi: cannot setup SPI controller\n"); - free(mxcs); - return NULL; - } return &mxcs->slave; } @@ -446,12 +443,17 @@ void spi_free_slave(struct spi_slave *slave) int spi_claim_bus(struct spi_slave *slave) { + int ret; struct mxc_spi_slave *mxcs = to_mxc_spi_slave(slave); struct cspi_regs *regs = (struct cspi_regs *)mxcs->base; reg_write(®s->rxdata, 1); udelay(1); - reg_write(®s->ctrl, mxcs->ctrl_reg); + ret = spi_cfg_mxc(mxcs, slave->cs); + if (ret) { + printf("mxc_spi: cannot setup SPI controller\n"); + return ret; + } reg_write(®s->period, MXC_CSPIPERIOD_32KHZ); reg_write(®s->intr, 0); diff --git a/drivers/usb/host/ehci-hcd.c b/drivers/usb/host/ehci-hcd.c index 936d006..c671c72 100644 --- a/drivers/usb/host/ehci-hcd.c +++ b/drivers/usb/host/ehci-hcd.c @@ -1097,6 +1097,7 @@ submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, } struct int_queue { + int elementsize; struct QH *first; struct QH *current; struct QH *last; @@ -1154,6 +1155,23 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, struct int_queue *result = NULL; int i; + /* + * Interrupt transfers requiring several transactions are not supported + * because bInterval is ignored. + * + * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 + * <= PKT_ALIGN if several qTDs are required, while the USB + * specification does not constrain this for interrupt transfers. That + * means that ehci_submit_async() would support interrupt transfers + * requiring several transactions only as long as the transfer size does + * not require more than a single qTD. + */ + if (elementsize > usb_maxpacket(dev, pipe)) { + printf("%s: xfers requiring several transactions are not supported.\n", + __func__); + return NULL; + } + debug("Enter create_int_queue\n"); if (usb_pipetype(pipe) != PIPE_INTERRUPT) { debug("non-interrupt pipe (type=%lu)", usb_pipetype(pipe)); @@ -1174,6 +1192,7 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, debug("ehci intr queue: out of memory\n"); goto fail1; } + result->elementsize = elementsize; result->first = memalign(USB_DMA_MINALIGN, sizeof(struct QH) * queuesize); if (!result->first) { @@ -1249,9 +1268,11 @@ create_int_queue(struct usb_device *dev, unsigned long pipe, int queuesize, ALIGN_END_ADDR(struct qTD, result->tds, queuesize)); - if (disable_periodic(ctrl) < 0) { - debug("FATAL: periodic should never fail, but did"); - goto fail3; + if (ctrl->periodic_schedules > 0) { + if (disable_periodic(ctrl) < 0) { + debug("FATAL: periodic should never fail, but did"); + goto fail3; + } } /* hook up to periodic list */ @@ -1308,13 +1329,18 @@ void *poll_int_queue(struct usb_device *dev, struct int_queue *queue) queue->current++; else queue->current = NULL; + + invalidate_dcache_range((uint32_t)cur->buffer, + ALIGN_END_ADDR(char, cur->buffer, + queue->elementsize)); + debug("Exit poll_int_queue with completed intr transfer. token is %x at %p (first at %p)\n", hc32_to_cpu(cur_td->qt_token), cur, queue->first); return cur->buffer; } /* Do not free buffers associated with QHs, they're owned by someone else */ -static int +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue) { struct ehci_ctrl *ctrl = dev->controller; @@ -1373,24 +1399,9 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, debug("dev=%p, pipe=%lu, buffer=%p, length=%d, interval=%d", dev, pipe, buffer, length, interval); - /* - * Interrupt transfers requiring several transactions are not supported - * because bInterval is ignored. - * - * Also, ehci_submit_async() relies on wMaxPacketSize being a power of 2 - * <= PKT_ALIGN if several qTDs are required, while the USB - * specification does not constrain this for interrupt transfers. That - * means that ehci_submit_async() would support interrupt transfers - * requiring several transactions only as long as the transfer size does - * not require more than a single qTD. - */ - if (length > usb_maxpacket(dev, pipe)) { - printf("%s: Interrupt transfers requiring several " - "transactions are not supported.\n", __func__); - return -1; - } - queue = create_int_queue(dev, pipe, 1, length, buffer); + if (!queue) + return -1; timeout = get_timer(0) + USB_TIMEOUT_MS(pipe); while ((backbuffer = poll_int_queue(dev, queue)) == NULL) @@ -1406,9 +1417,6 @@ submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, return -EINVAL; } - invalidate_dcache_range((uint32_t)buffer, - ALIGN_END_ADDR(char, buffer, length)); - ret = destroy_int_queue(dev, queue); if (ret < 0) return ret; diff --git a/drivers/usb/host/ehci-rmobile.c b/drivers/usb/host/ehci-rmobile.c index 0d1a726..b433087 100644 --- a/drivers/usb/host/ehci-rmobile.c +++ b/drivers/usb/host/ehci-rmobile.c @@ -22,12 +22,8 @@ static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 0xEE0A0000, /* USB1 */ 0xEE0C0000, /* USB2 */ }; -#elif defined(CONFIG_R8A7791) -static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { - 0xEE080000, /* USB0 (EHCI) */ - 0xEE0C0000, /* USB1 */ -}; -#elif defined(CONFIG_R8A7794) +#elif defined(CONFIG_R8A7791) || defined(CONFIG_R8A7793) || \ + defined(CONFIG_R8A7794) static u32 usb_base_address[CONFIG_USB_MAX_CONTROLLER_COUNT] = { 0xEE080000, /* USB0 (EHCI) */ 0xEE0C0000, /* USB1 */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index 69c0336..cdccbef 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2003-2005 + * (C) Copyright 2003-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2004-2006 @@ -19,6 +19,8 @@ #define CONFIG_MPC5200 1 /* This is an MPC5200 CPU */ #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO /* * Valid values for CONFIG_SYS_TEXT_BASE are: diff --git a/include/configs/TQM823L.h b/include/configs/TQM823L.h index cc22045..0d5a2b9 100644 --- a/include/configs/TQM823L.h +++ b/include/configs/TQM823L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM823M.h b/include/configs/TQM823M.h index 4fd070f..e765a03 100644 --- a/include/configs/TQM823M.h +++ b/include/configs/TQM823M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC823 1 /* This is a MPC823 CPU */ #define CONFIG_TQM823M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM850L.h b/include/configs/TQM850L.h index ca3750d..bbdc3f8 100644 --- a/include/configs/TQM850L.h +++ b/include/configs/TQM850L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM850M.h b/include/configs/TQM850M.h index 659c9ad..5fc87f2 100644 --- a/include/configs/TQM850M.h +++ b/include/configs/TQM850M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC850 1 /* This is a MPC850 CPU */ #define CONFIG_TQM850M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855L.h b/include/configs/TQM855L.h index 906d79b..589d168 100644 --- a/include/configs/TQM855L.h +++ b/include/configs/TQM855L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM855M.h b/include/configs/TQM855M.h index 44d456e..60acb56 100644 --- a/include/configs/TQM855M.h +++ b/include/configs/TQM855M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC855 1 /* This is a MPC855 CPU */ #define CONFIG_TQM855M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860L.h b/include/configs/TQM860L.h index 855b0cd..ebc5571 100644 --- a/include/configs/TQM860L.h +++ b/include/configs/TQM860L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860L 1 /* ...on a TQM8xxL module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM860M.h b/include/configs/TQM860M.h index 8109379..f4ce07f 100644 --- a/include/configs/TQM860M.h +++ b/include/configs/TQM860M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC860 1 /* This is a MPC860 CPU */ #define CONFIG_TQM860M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM862L.h b/include/configs/TQM862L.h index da4af93..97db519 100644 --- a/include/configs/TQM862L.h +++ b/include/configs/TQM862L.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862L 1 /* ...on a TQM8xxL module */ diff --git a/include/configs/TQM862M.h b/include/configs/TQM862M.h index ec3a57b..25d60a7 100644 --- a/include/configs/TQM862M.h +++ b/include/configs/TQM862M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -20,6 +20,8 @@ #define CONFIG_MPC860 1 #define CONFIG_MPC860T 1 #define CONFIG_MPC862 1 +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_TQM862M 1 /* ...on a TQM8xxM module */ diff --git a/include/configs/TQM866M.h b/include/configs/TQM866M.h index cb8b84d..928b879 100644 --- a/include/configs/TQM866M.h +++ b/include/configs/TQM866M.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2008 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * SPDX-License-Identifier: GPL-2.0+ @@ -19,6 +19,8 @@ #define CONFIG_MPC866 1 /* This is a MPC866 CPU */ #define CONFIG_TQM866M 1 /* ...on a TQM8xxM module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index d1e6c5b..598020c 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2000-2005 + * (C) Copyright 2000-2014 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * (C) Copyright 2006 @@ -22,6 +22,8 @@ #define CONFIG_MPC885 1 /* This is a MPC885 CPU */ #define CONFIG_TQM885D 1 /* ...on a TQM88D module */ +#define CONFIG_SYS_GENERIC_BOARD +#define CONFIG_DISPLAY_BOARDINFO #define CONFIG_SYS_TEXT_BASE 0x40000000 diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 4b90dc2..fef267f 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -26,6 +26,7 @@ #define CONFIG_PHYSMEM #define CONFIG_SYS_EARLY_PCI_INIT #define CONFIG_DISPLAY_BOARDINFO_LATE +#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DM #define CONFIG_CMD_DM @@ -48,6 +49,7 @@ #define CONFIG_FIT #undef CONFIG_ZLIB #undef CONFIG_GZIP +#define CONFIG_SYS_BOOTM_LEN (16 << 20) /*----------------------------------------------------------------------- * Watchdog Configuration @@ -221,7 +223,7 @@ #define CONFIG_SYS_MEMTEST_START 0x00100000 #define CONFIG_SYS_MEMTEST_END 0x01000000 -#define CONFIG_SYS_LOAD_ADDR 0x02000000 +#define CONFIG_SYS_LOAD_ADDR 0x20000000 /*----------------------------------------------------------------------- * SDRAM Configuration diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index f924965..1c04a58 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -29,8 +29,6 @@ #endif #endif -#define CONFIG_SYS_LITTLE_ENDIAN - #define CONFIG_ETHADDR DE:AD:BE:EF:01:01 /* Ethernet address */ #define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */ diff --git a/include/image.h b/include/image.h index a13a302..07e9aed 100644 --- a/include/image.h +++ b/include/image.h @@ -173,6 +173,7 @@ struct lmb; #define IH_ARCH_OPENRISC 21 /* OpenRISC 1000 */ #define IH_ARCH_ARM64 22 /* ARM64 */ #define IH_ARCH_ARC 23 /* Synopsys DesignWare ARC */ +#define IH_ARCH_X86_64 24 /* AMD x86_64, Intel and Via */ /* * Image Types diff --git a/include/serial.h b/include/serial.h index 8f574e4..66ed12c 100644 --- a/include/serial.h +++ b/include/serial.h @@ -164,4 +164,53 @@ struct serial_dev_priv { /* Access the serial operations for a device */ #define serial_get_ops(dev) ((struct dm_serial_ops *)(dev)->driver->ops) +void altera_jtag_serial_initialize(void); +void altera_serial_initialize(void); +void amirix_serial_initialize(void); +void arc_serial_initialize(void); +void arm_dcc_initialize(void); +void asc_serial_initialize(void); +void atmel_serial_initialize(void); +void au1x00_serial_initialize(void); +void bfin_jtag_initialize(void); +void bfin_serial_initialize(void); +void bmw_serial_initialize(void); +void clps7111_serial_initialize(void); +void cogent_serial_initialize(void); +void cpci750_serial_initialize(void); +void evb64260_serial_initialize(void); +void imx_serial_initialize(void); +void iop480_serial_initialize(void); +void jz_serial_initialize(void); +void ks8695_serial_initialize(void); +void leon2_serial_initialize(void); +void leon3_serial_initialize(void); +void lh7a40x_serial_initialize(void); +void lpc32xx_serial_initialize(void); +void marvell_serial_initialize(void); +void max3100_serial_initialize(void); +void mcf_serial_initialize(void); +void ml2_serial_initialize(void); +void mpc512x_serial_initialize(void); +void mpc5xx_serial_initialize(void); +void mpc8260_scc_serial_initialize(void); +void mpc8260_smc_serial_initialize(void); +void mpc85xx_serial_initialize(void); +void mpc8xx_serial_initialize(void); +void mxc_serial_initialize(void); +void mxs_auart_initialize(void); +void ns16550_serial_initialize(void); +void oc_serial_initialize(void); +void p3mx_serial_initialize(void); +void pl01x_serial_initialize(void); +void pxa_serial_initialize(void); +void s3c24xx_serial_initialize(void); +void s5p_serial_initialize(void); +void sa1100_serial_initialize(void); +void sandbox_serial_initialize(void); +void sconsole_serial_initialize(void); +void sh_serial_initialize(void); +void uartlite_serial_initialize(void); +void zynq_serial_initialize(void); + #endif diff --git a/include/twl4030.h b/include/twl4030.h index 093c61d..18795a6 100644 --- a/include/twl4030.h +++ b/include/twl4030.h @@ -395,6 +395,8 @@ #define TWL4030_PM_RECEIVER_VDAC_VSEL_18 0x03 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_30 0x02 #define TWL4030_PM_RECEIVER_VMMC1_VSEL_32 0x03 +#define TWL4030_PM_RECEIVER_VMMC2_VSEL_30 0x0B +#define TWL4030_PM_RECEIVER_VMMC2_VSEL_32 0x0C #define TWL4030_PM_RECEIVER_VSIM_VSEL_18 0x03 /* Device Selection in PM Receiver Module */ diff --git a/include/usb.h b/include/usb.h index c4a288d..9d0d04d 100644 --- a/include/usb.h +++ b/include/usb.h @@ -129,6 +129,8 @@ struct usb_device { unsigned int slot_id; }; +struct int_queue; + /* * You can initialize platform's USB host or device * ports by passing this enum as an argument to @@ -163,6 +165,13 @@ int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer, int transfer_len, int interval); +#ifdef CONFIG_USB_EHCI /* Only the ehci code has pollable int support */ +struct int_queue *create_int_queue(struct usb_device *dev, unsigned long pipe, + int queuesize, int elementsize, void *buffer); +int destroy_int_queue(struct usb_device *dev, struct int_queue *queue); +void *poll_int_queue(struct usb_device *dev, struct int_queue *queue); +#endif + /* Defines */ #define USB_UHCI_VEND_ID 0x8086 #define USB_UHCI_DEV_ID 0x7112 diff --git a/include/usb/omap1510_udc.h b/include/usb/omap1510_udc.h deleted file mode 100644 index adfbf54..0000000 --- a/include/usb/omap1510_udc.h +++ /dev/null @@ -1,174 +0,0 @@ -/* - * (C) Copyright 2003 - * Gerry Hamel, geh@ti.com, Texas Instruments - * - * Based on - * linux/drivers/usb/device/bi/omap.h - * Register definitions for TI OMAP1510 USB bus interface driver - * - * Author: MontaVista Software, Inc. - * source@mvista.com - * - * 2003 (c) MontaVista Software, Inc. This file is licensed under - * the terms of the GNU General Public License version 2. This program - * is licensed "as is" without any warranty of any kind, whether express - * or implied. - */ - -#ifndef __USBDCORE_OMAP1510_H__ -#define __USBDCORE_OMAP1510_H__ - - -/* - * 13.2 MPU Register Map - */ - -/* Table 13-1. USB Function Module Registers (endpoint) */ -#define UDC_BASE 0xFFFB4000 -#define UDC_OFFSET(offset) (UDC_BASE + (offset)) -#define UDC_REV UDC_OFFSET(0x0) /* Revision */ -#define UDC_EP_NUM UDC_OFFSET(0x4) /* Endpoint selection */ -#define UDC_DATA UDC_OFFSET(0x08) /* Data */ -#define UDC_CTRL UDC_OFFSET(0x0C) /* Control */ -#define UDC_STAT_FLG UDC_OFFSET(0x10) /* Status flag */ -#define UDC_RXFSTAT UDC_OFFSET(0x14) /* Receive FIFO status */ -#define UDC_SYSCON1 UDC_OFFSET(0x18) /* System configuration 1 */ -#define UDC_SYSCON2 UDC_OFFSET(0x1C) /* System configuration 2 */ -#define UDC_DEVSTAT UDC_OFFSET(0x20) /* Device status */ -#define UDC_SOF UDC_OFFSET(0x24) /* Start of frame */ -#define UDC_IRQ_EN UDC_OFFSET(0x28) /* Interrupt enable */ -#define UDC_DMA_IRQ_EN UDC_OFFSET(0x2C) /* DMA interrupt enable */ -#define UDC_IRQ_SRC UDC_OFFSET(0x30) /* Interrupt source */ -#define UDC_EPN_STAT UDC_OFFSET(0x34) /* Endpoint interrupt status */ -#define UDC_DMAN_STAT UDC_OFFSET(0x3C) /* DMA endpoint interrupt status */ - -/* IRQ_EN register fields */ -#define UDC_Sof_IE (1 << 7) /* Start-of-frame interrupt enabled */ -#define UDC_EPn_RX_IE (1 << 5) /* Receive endpoint interrupt enabled */ -#define UDC_EPn_TX_IE (1 << 4) /* Transmit endpoint interrupt enabled */ -#define UDC_DS_Chg_IE (1 << 3) /* Device state changed interrupt enabled */ -#define UDC_EP0_IE (1 << 0) /* EP0 transaction interrupt enabled */ - -/* IRQ_SRC register fields */ -#define UDC_TXn_Done (1 << 10) /* Transmit DMA channel n done */ -#define UDC_RXn_Cnt (1 << 9) /* Receive DMA channel n transactions count */ -#define UDC_RXn_EOT (1 << 8) /* Receive DMA channel n end of transfer */ -#define UDC_SOF_Flg (1 << 7) /* Start-of-frame interrupt flag */ -#define UDC_EPn_RX (1 << 5) /* Endpoint n OUT transaction */ -#define UDC_EPn_TX (1 << 4) /* Endpoint n IN transaction */ -#define UDC_DS_Chg (1 << 3) /* Device state changed */ -#define UDC_Setup (1 << 2) /* Setup transaction */ -#define UDC_EP0_RX (1 << 1) /* EP0 OUT transaction */ -#define UDC_EP0_TX (1 << 0) /* EP0 IN transaction */ - -/* DEVSTAT register fields, 14.2.9 */ -#define UDC_R_WK_OK (1 << 6) /* Remote wakeup granted */ -#define UDC_USB_Reset (1 << 5) /* USB reset signalling is active */ -#define UDC_SUS (1 << 4) /* Suspended state */ -#define UDC_CFG (1 << 3) /* Configured state */ -#define UDC_ADD (1 << 2) /* Addressed state */ -#define UDC_DEF (1 << 1) /* Default state */ -#define UDC_ATT (1 << 0) /* Attached state */ - -/* SYSCON1 register fields */ -#define UDC_Cfg_Lock (1 << 8) /* Device configuration locked */ -#define UDC_Nak_En (1 << 4) /* NAK enable */ -#define UDC_Self_Pwr (1 << 2) /* Device is self-powered */ -#define UDC_Soff_Dis (1 << 1) /* Shutoff disabled */ -#define UDC_Pullup_En (1 << 0) /* External pullup enabled */ - -/* SYSCON2 register fields */ -#define UDC_Rmt_Wkp (1 << 6) /* Remote wakeup */ -#define UDC_Stall_Cmd (1 << 5) /* Stall endpoint */ -#define UDC_Dev_Cfg (1 << 3) /* Device configured */ -#define UDC_Clr_Cfg (1 << 2) /* Clear configured */ - -/* - * Select and enable endpoints - */ - -/* Table 13-1. USB Function Module Registers (endpoint configuration) */ -#define UDC_EPBASE UDC_OFFSET(0x80) /* Endpoints base address */ -#define UDC_EP0 UDC_EPBASE /* Control endpoint configuration */ -#define UDC_EP_RX_BASE UDC_OFFSET(0x84) /* Receive endpoints base address */ -#define UDC_EP_RX(endpoint) (UDC_EP_RX_BASE + ((endpoint) - 1) * 4) -#define UDC_EP_TX_BASE UDC_OFFSET(0xC4) /* Transmit endpoints base address */ -#define UDC_EP_TX(endpoint) (UDC_EP_TX_BASE + ((endpoint) - 1) * 4) - -/* EP_NUM register fields */ -#define UDC_Setup_Sel (1 << 6) /* Setup FIFO select */ -#define UDC_EP_Sel (1 << 5) /* TX/RX FIFO select */ -#define UDC_EP_Dir (1 << 4) /* Endpoint direction */ - -/* CTRL register fields */ -#define UDC_Clr_Halt (1 << 7) /* Clear halt endpoint */ -#define UDC_Set_Halt (1 << 6) /* Set halt endpoint */ -#define UDC_Set_FIFO_En (1 << 2) /* Set FIFO enable */ -#define UDC_Clr_EP (1 << 1) /* Clear endpoint */ -#define UDC_Reset_EP (1 << 0) /* Reset endpoint */ - -/* STAT_FLG register fields */ -#define UDC_Miss_In (1 << 14) -#define UDC_Data_Flush (1 << 13) -#define UDC_ISO_Err (1 << 12) -#define UDC_ISO_FIFO_Empty (1 << 9) -#define UDC_ISO_FIFO_Full (1 << 8) -#define UDC_EP_Halted (1 << 6) -#define UDC_STALL (1 << 5) -#define UDC_NAK (1 << 4) -#define UDC_ACK (1 << 3) -#define UDC_FIFO_En (1 << 2) -#define UDC_Non_ISO_FIFO_Empty (1 << 1) -#define UDC_Non_ISO_FIFO_Full (1 << 0) - -/* EPn_RX register fields */ -#define UDC_EPn_RX_Valid (1 << 15) /* valid */ -#define UDC_EPn_RX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_RX_Iso (1 << 11) /* isochronous */ - -/* EPn_TX register fields */ -#define UDC_EPn_TX_Valid (1 << 15) /* valid */ -#define UDC_EPn_TX_Db (1 << 14) /* double-buffer */ -#define UDC_EPn_TX_Iso (1 << 11) /* isochronous */ - -#define EP0_PACKETSIZE 0x40 - -/* physical to logical endpoint mapping - * Physical endpoints are an index into device->bus->endpoint_array. - * Logical endpoints are endpoints 0 to 15 IN and OUT as defined in - * the USB specification. - * - * physical ep logical ep direction endpoint_address - * 0 0 IN and OUT 0x00 - * 1 to 15 1 to 15 OUT 0x01 to 0x0f - * 16 to 30 1 to 15 IN 0x81 to 0x8f - */ -#define PHYS_EP_TO_EP_ADDR(ep) (((ep) < 16) ? (ep) : (((ep) - 15) | 0x80)) -#define EP_ADDR_TO_PHYS_EP(a) (((a) & 0x80) ? (((a) & ~0x80) + 15) : (a)) - -/* MOD_CONF_CTRL_0 bits (FIXME: move to board hardware.h ?) */ -#define CONF_MOD_USB_W2FC_VBUS_MODE_R (1 << 17) - -/* Other registers (may be) related to USB */ - -#define CLOCK_CTRL (0xFFFE0830) -#define APLL_CTRL (0xFFFE084C) -#define DPLL_CTRL (0xFFFE083C) -#define SOFT_REQ (0xFFFE0834) -#define STATUS_REQ (0xFFFE0840) - -/* FUNC_MUX_CTRL_0 bits related to USB */ -#define UDC_VBUS_CTRL (1 << 19) -#define UDC_VBUS_MODE (1 << 18) - -/* OMAP Endpoint parameters */ -#define UDC_OUT_PACKET_SIZE 64 -#define UDC_IN_PACKET_SIZE 64 -#define UDC_INT_PACKET_SIZE 16 -#define UDC_BULK_PACKET_SIZE 16 - -#define UDC_INT_ENDPOINT 5 -#define UDC_OUT_ENDPOINT 2 -#define UDC_IN_ENDPOINT 1 - -#endif diff --git a/scripts/Makefile.extrawarn b/scripts/Makefile.extrawarn index 6564350..0ec0d24 100644 --- a/scripts/Makefile.extrawarn +++ b/scripts/Makefile.extrawarn @@ -26,16 +26,6 @@ warning-1 += $(call cc-option, -Wmissing-include-dirs) warning-1 += $(call cc-option, -Wunused-but-set-variable) warning-1 += $(call cc-disable-warning, missing-field-initializers) -# Clang -warning-1 += $(call cc-disable-warning, initializer-overrides) -warning-1 += $(call cc-disable-warning, unused-value) -warning-1 += $(call cc-disable-warning, format) -warning-1 += $(call cc-disable-warning, unknown-warning-option) -warning-1 += $(call cc-disable-warning, sign-compare) -warning-1 += $(call cc-disable-warning, format-zero-length) -warning-1 += $(call cc-disable-warning, uninitialized) -warning-1 += $(call cc-option, -fcatch-undefined-behavior) - warning-2 := -Waggregate-return warning-2 += -Wcast-align warning-2 += -Wdisabled-optimization diff --git a/tools/kwbimage.c b/tools/kwbimage.c index 1120e9b..c50f2e2 100644 --- a/tools/kwbimage.c +++ b/tools/kwbimage.c @@ -12,6 +12,7 @@ */ #include "imagetool.h" +#include <limits.h> #include <image.h> #include <stdint.h> #include "kwbimage.h" @@ -324,7 +325,7 @@ static void *image_create_v0(size_t *imagesz, struct image_tool_params *params, main_hdr = image; /* Fill in the main header */ - main_hdr->blocksize = payloadsz + sizeof(uint32_t); + main_hdr->blocksize = payloadsz + sizeof(uint32_t) - headersz; main_hdr->srcaddr = headersz; main_hdr->ext = has_ext; main_hdr->destaddr = params->addr; @@ -396,13 +397,20 @@ static size_t image_headersz_v1(struct image_tool_params *params, ret = stat(binarye->binary.file, &s); if (ret < 0) { - char *cwd = get_current_dir_name(); + char cwd[PATH_MAX]; + char *dir = cwd; + + memset(cwd, 0, sizeof(cwd)); + if (!getcwd(cwd, sizeof(cwd))) { + dir = "current working directory"; + perror("getcwd() failed"); + } + fprintf(stderr, "Didn't find the file '%s' in '%s' which is mandatory to generate the image\n" "This file generally contains the DDR3 training code, and should be extracted from an existing bootable\n" "image for your board. See 'kwbimage -x' to extract it from an existing image.\n", - binarye->binary.file, cwd); - free(cwd); + binarye->binary.file, dir); return 0; } @@ -752,14 +760,25 @@ static void kwbimage_set_header(void *ptr, struct stat *sbuf, int ifd, } version = image_get_version(); - /* Fallback to version 0 is no version is provided in the cfg file */ - if (version == -1) - version = 0; - - if (version == 0) + switch (version) { + /* + * Fallback to version 0 if no version is provided in the + * cfg file + */ + case -1: + case 0: image = image_create_v0(&headersz, params, sbuf->st_size); - else if (version == 1) + break; + + case 1: image = image_create_v1(&headersz, params, sbuf->st_size); + break; + + default: + fprintf(stderr, "Unsupported version %d\n", version); + free(image_cfg); + exit(EXIT_FAILURE); + } if (!image) { fprintf(stderr, "Could not create image\n"); @@ -792,8 +811,8 @@ static void kwbimage_print_header(const void *ptr) printf("Image Type: MVEBU Boot from %s Image\n", image_boot_mode_name(mhdr->blockid)); - printf("Data Size: "); printf("Image version:%d\n", image_version((void *)ptr)); + printf("Data Size: "); genimg_print_size(mhdr->blocksize - sizeof(uint32_t)); printf("Load Address: %08x\n", mhdr->destaddr); printf("Entry Point: %08x\n", mhdr->execaddr); @@ -816,7 +835,8 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, main_hdr = (void *)ptr; checksum = image_checksum8(ptr, - sizeof(struct main_hdr_v0)); + sizeof(struct main_hdr_v0) + - sizeof(uint8_t)); if (checksum != main_hdr->checksum) return -FDT_ERR_BADSTRUCTURE; @@ -824,7 +844,8 @@ static int kwbimage_verify_header(unsigned char *ptr, int image_size, if (image_version((void *)ptr) == 0) { ext_hdr = (void *)ptr + sizeof(struct main_hdr_v0); checksum = image_checksum8(ext_hdr, - sizeof(struct ext_hdr_v0)); + sizeof(struct ext_hdr_v0) + - sizeof(uint8_t)); if (checksum != ext_hdr->checksum) return -FDT_ERR_BADSTRUCTURE; } |