diff options
| -rw-r--r-- | cpu/ppc4xx/fdt.c | 42 | ||||
| -rw-r--r-- | include/asm-ppc/4xx_pcie.h | 5 |
2 files changed, 46 insertions, 1 deletions
diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index afcb974..1f4d6f2 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -31,9 +31,46 @@ #include <libfdt.h> #include <libfdt_env.h> #include <fdt_support.h> +#include <asm/4xx_pcie.h> DECLARE_GLOBAL_DATA_PTR; +/* + * Fixup all PCIe nodes by setting the device_type property + * to "pci-endpoint" instead is "pci" for endpoint ports. + * This property will get checked later by the Linux driver + * to properly configure the PCIe port in Linux (again). + */ +void fdt_pcie_setup(void *blob) +{ + const char *compat = "ibm,plb-pciex"; + const char *prop = "device_type"; + const char *prop_val = "pci-endpoint"; + const u32 *port; + int no; + int rc; + + /* Search first PCIe node */ + no = fdt_node_offset_by_compatible(blob, -1, compat); + while (no != -FDT_ERR_NOTFOUND) { + port = fdt_getprop(blob, no, "port", NULL); + if (port == NULL) { + printf("WARNING: could not find port property\n"); + } else { + if (is_end_point(*port)) { + rc = fdt_setprop(blob, no, prop, prop_val, + strlen(prop_val) + 1); + if (rc < 0) + printf("WARNING: could not set %s for %s: %s.\n", + prop, compat, fdt_strerror(rc)); + } + } + + /* Jump to next PCIe node */ + no = fdt_node_offset_by_compatible(blob, no, compat); + } +} + void ft_cpu_setup(void *blob, bd_t *bd) { sys_info_t sys_info; @@ -60,5 +97,10 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Note: aliases in the dts are required for this */ fdt_fixup_ethernet(blob, bd); + + /* + * Fixup all available PCIe nodes by setting the device_type property + */ + fdt_pcie_setup(blob); } #endif /* CONFIG_OF_LIBFDT */ diff --git a/include/asm-ppc/4xx_pcie.h b/include/asm-ppc/4xx_pcie.h index d27d2a9..5398696 100644 --- a/include/asm-ppc/4xx_pcie.h +++ b/include/asm-ppc/4xx_pcie.h @@ -8,10 +8,11 @@ * option) any later version. */ -#include <ppc4xx.h> #ifndef __4XX_PCIE_H #define __4XX_PCIE_H +#include <ppc4xx.h> + #define DCRN_SDR0_CFGADDR 0x00e #define DCRN_SDR0_CFGDATA 0x00f @@ -395,6 +396,7 @@ static inline void mdelay(int n) udelay(1000); } +#if defined(PCIE0_SDR) static inline u32 sdr_base(int port) { switch (port) { @@ -409,5 +411,6 @@ static inline u32 sdr_base(int port) #endif } } +#endif /* defined(PCIE0_SDR) */ #endif /* __4XX_PCIE_H */ |