diff options
| -rw-r--r-- | MAINTAINERS | 1 | ||||
| -rw-r--r-- | arch/sh/cpu/sh2/config.mk | 3 | ||||
| -rw-r--r-- | arch/sh/cpu/sh4/cache.c | 22 | ||||
| -rw-r--r-- | arch/sh/include/asm/cache.h | 24 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh4.h | 2 | ||||
| -rw-r--r-- | arch/sh/include/asm/cpu_sh7724.h | 234 | ||||
| -rw-r--r-- | arch/sh/lib/Makefile | 1 | ||||
| -rw-r--r-- | arch/sh/lib/ashrsi3.S | 185 | ||||
| -rw-r--r-- | board/renesas/ecovec/Makefile | 38 | ||||
| -rw-r--r-- | board/renesas/ecovec/ecovec.c | 124 | ||||
| -rw-r--r-- | board/renesas/ecovec/lowlevel_init.S | 211 | ||||
| -rw-r--r-- | board/renesas/sh7757lcr/lowlevel_init.S | 3 | ||||
| -rw-r--r-- | boards.cfg | 1 | ||||
| -rw-r--r-- | doc/README.sh7757lcr | 14 | ||||
| -rw-r--r-- | drivers/net/sh_eth.c | 293 | ||||
| -rw-r--r-- | drivers/net/sh_eth.h | 59 | ||||
| -rw-r--r-- | include/configs/ecovec.h | 200 | ||||
| -rw-r--r-- | include/configs/espt.h | 4 | ||||
| -rw-r--r-- | include/configs/sh7757lcr.h | 5 | ||||
| -rw-r--r-- | include/configs/sh7763rdp.h | 4 |
20 files changed, 1157 insertions, 271 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index ad1b62f..689c766 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1054,6 +1054,7 @@ Nobuhiro Iwamatsu <iwamatsu@nigauri.org> RSK7203 SH7203 AP325RXA SH7723 SHMIN SH7706 + ECOVEC SH7724 Mark Jonas <mark.jonas@de.bosch.com> diff --git a/arch/sh/cpu/sh2/config.mk b/arch/sh/cpu/sh2/config.mk index f46b38f..bdd3315 100644 --- a/arch/sh/cpu/sh2/config.mk +++ b/arch/sh/cpu/sh2/config.mk @@ -24,10 +24,11 @@ ENDIANNESS += -EB ifdef CONFIG_SH2A -PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -mno-fdpic -ffreestanding +PLATFORM_CPPFLAGS += -m2a -m2a-nofpu -mb -ffreestanding else # SH2 PLATFORM_CPPFLAGS += -m3e -mb endif +PLATFORM_CPPFLAGS += $(call cc-option,-mno-fdpic) PLATFORM_RELFLAGS += -ffixed-r13 PLATFORM_LDFLAGS += $(ENDIANNESS) diff --git a/arch/sh/cpu/sh4/cache.c b/arch/sh/cpu/sh4/cache.c index 377005c..dc75e39 100644 --- a/arch/sh/cpu/sh4/cache.c +++ b/arch/sh/cpu/sh4/cache.c @@ -106,3 +106,25 @@ int cache_control(unsigned int cmd) return 0; } + +void dcache_wback_range(u32 start, u32 end) +{ + u32 v; + + start &= ~(L1_CACHE_BYTES - 1); + for (v = start; v < end; v += L1_CACHE_BYTES) { + asm volatile ("ocbwb %0" : /* no output */ + : "m" (__m(v))); + } +} + +void dcache_invalid_range(u32 start, u32 end) +{ + u32 v; + + start &= ~(L1_CACHE_BYTES - 1); + for (v = start; v < end; v += L1_CACHE_BYTES) { + asm volatile ("ocbi %0" : /* no output */ + : "m" (__m(v))); + } +} diff --git a/arch/sh/include/asm/cache.h b/arch/sh/include/asm/cache.h index 6ffab4d..24941b3 100644 --- a/arch/sh/include/asm/cache.h +++ b/arch/sh/include/asm/cache.h @@ -10,27 +10,9 @@ int cache_control(unsigned int cmd); struct __large_struct { unsigned long buf[100]; }; #define __m(x) (*(struct __large_struct *)(x)) -void dcache_wback_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbwb %0" : /* no output */ - : "m" (__m(v))); - } -} - -void dcache_invalid_range(u32 start, u32 end) -{ - u32 v; - - start &= ~(L1_CACHE_BYTES - 1); - for (v = start; v < end; v += L1_CACHE_BYTES) { - asm volatile ("ocbi %0" : /* no output */ - : "m" (__m(v))); - } -} +void dcache_wback_range(u32 start, u32 end); +void dcache_invalid_range(u32 start, u32 end); + #else /* diff --git a/arch/sh/include/asm/cpu_sh4.h b/arch/sh/include/asm/cpu_sh4.h index 9b29d3a..4351e8e 100644 --- a/arch/sh/include/asm/cpu_sh4.h +++ b/arch/sh/include/asm/cpu_sh4.h @@ -44,6 +44,8 @@ # include <asm/cpu_sh7722.h> #elif defined (CONFIG_CPU_SH7723) # include <asm/cpu_sh7723.h> +#elif defined (CONFIG_CPU_SH7724) +# include <asm/cpu_sh7724.h> #elif defined (CONFIG_CPU_SH7757) # include <asm/cpu_sh7757.h> #elif defined (CONFIG_CPU_SH7763) diff --git a/arch/sh/include/asm/cpu_sh7724.h b/arch/sh/include/asm/cpu_sh7724.h new file mode 100644 index 0000000..3bb51d3 --- /dev/null +++ b/arch/sh/include/asm/cpu_sh7724.h @@ -0,0 +1,234 @@ +/* + * (C) Copyright 2008, 2011 Renesas Solutions Corp. + * + * SH7724 Internal I/O register + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ASM_CPU_SH7724_H_ +#define _ASM_CPU_SH7724_H_ + +#define CACHE_OC_NUM_WAYS 4 +#define CCR_CACHE_INIT 0x0000090d + +/* EXP */ +#define TRA 0xFF000020 +#define EXPEVT 0xFF000024 +#define INTEVT 0xFF000028 + +/* MMU */ +#define PTEH 0xFF000000 +#define PTEL 0xFF000004 +#define TTB 0xFF000008 +#define TEA 0xFF00000C +#define MMUCR 0xFF000010 +#define PASCR 0xFF000070 +#define IRMCR 0xFF000078 + +/* CACHE */ +#define CCR 0xFF00001C +#define RAMCR 0xFF000074 + +/* INTC */ + +/* BSC */ +#define MMSELR 0xFF800020 +#define CMNCR 0xFEC10000 +#define CS0BCR 0xFEC10004 +#define CS2BCR 0xFEC10008 +#define CS4BCR 0xFEC10010 +#define CS5ABCR 0xFEC10014 +#define CS5BBCR 0xFEC10018 +#define CS6ABCR 0xFEC1001C +#define CS6BBCR 0xFEC10020 +#define CS0WCR 0xFEC10024 +#define CS2WCR 0xFEC10028 +#define CS4WCR 0xFEC10030 +#define CS5AWCR 0xFEC10034 +#define CS5BWCR 0xFEC10038 +#define CS6AWCR 0xFEC1003C +#define CS6BWCR 0xFEC10040 +#define RBWTCNT 0xFEC10054 + +/* SBSC */ +#define SBSC_SDCR 0xFE400008 +#define SBSC_SDWCR 0xFE40000C +#define SBSC_SDPCR 0xFE400010 +#define SBSC_RTCSR 0xFE400014 +#define SBSC_RTCNT 0xFE400018 +#define SBSC_RTCOR 0xFE40001C +#define SBSC_RFCR 0xFE400020 + +/* DSBC */ +#define DBKIND 0xFD000008 +#define DBSTATE 0xFD00000C +#define DBEN 0xFD000010 +#define DBCMDCNT 0xFD000014 +#define DBCKECNT 0xFD000018 +#define DBCONF 0xFD000020 +#define DBTR0 0xFD000030 +#define DBTR1 0xFD000034 +#define DBTR2 0xFD000038 +#define DBTR3 0xFD00003C +#define DBRFPDN0 0xFD000040 +#define DBRFPDN1 0xFD000044 +#define DBRFPDN2 0xFD000048 +#define DBRFSTS 0xFD00004C +#define DBMRCNT 0xFD000060 +#define DBPDCNT0 0xFD000108 + +/* DMAC */ + +/* CPG */ +#define FRQCRA 0xA4150000 +#define FRQCRB 0xA4150004 +#define FRQCR FRQCRA +#define VCLKCR 0xA4150004 +#define SCLKACR 0xA4150008 +#define SCLKBCR 0xA415000C +#define IRDACLKCR 0xA4150018 +#define PLLCR 0xA4150024 +#define DLLFRQ 0xA4150050 + +/* LOW POWER MODE */ +#define STBCR 0xA4150020 +#define MSTPCR0 0xA4150030 +#define MSTPCR1 0xA4150034 +#define MSTPCR2 0xA4150038 + +/* RWDT */ +#define RWTCNT 0xA4520000 +#define RWTCSR 0xA4520004 +#define WTCNT RWTCNT + +/* TMU */ +#define TSTR 0xFFD80004 +#define TCOR0 0xFFD80008 +#define TCNT0 0xFFD8000C +#define TCR0 0xFFD80010 +#define TCOR1 0xFFD80014 +#define TCNT1 0xFFD80018 +#define TCR1 0xFFD8001C +#define TCOR2 0xFFD80020 +#define TCNT2 0xFFD80024 +#define TCR2 0xFFD80028 + +/* TPU */ + +/* CMT */ +#define CMSTR 0xA44A0000 +#define CMCSR 0xA44A0060 +#define CMCNT 0xA44A0064 +#define CMCOR 0xA44A0068 + +/* MSIOF */ + +/* SCIF */ +#define SCIF0_BASE 0xFFE00000 +#define SCIF1_BASE 0xFFE10000 +#define SCIF2_BASE 0xFFE20000 +#define SCIF3_BASE 0xa4e30000 +#define SCIF4_BASE 0xa4e40000 +#define SCIF5_BASE 0xa4e50000 + +/* RTC */ +/* IrDA */ +/* KEYSC */ +/* USB */ +/* IIC */ +/* FLCTL */ +/* VPU */ +/* VIO(CEU) */ +/* VIO(VEU) */ +/* VIO(BEU) */ +/* 2DG */ +/* LCDC */ +/* VOU */ +/* TSIF */ +/* SIU */ +/* ATAPI */ + +/* PFC */ +#define PACR 0xA4050100 +#define PBCR 0xA4050102 +#define PCCR 0xA4050104 +#define PDCR 0xA4050106 +#define PECR 0xA4050108 +#define PFCR 0xA405010A +#define PGCR 0xA405010C +#define PHCR 0xA405010E +#define PJCR 0xA4050110 +#define PKCR 0xA4050112 +#define PLCR 0xA4050114 +#define PMCR 0xA4050116 +#define PNCR 0xA4050118 +#define PQCR 0xA405011A +#define PRCR 0xA405011C +#define PSCR 0xA405011E +#define PTCR 0xA4050140 +#define PUCR 0xA4050142 +#define PVCR 0xA4050144 +#define PWCR 0xA4050146 +#define PXCR 0xA4050148 +#define PYCR 0xA405014A +#define PZCR 0xA405014C +#define PSELA 0xA405014E +#define PSELB 0xA4050150 +#define PSELC 0xA4050152 +#define PSELD 0xA4050154 +#define PSELE 0xA4050156 +#define HIZCRA 0xA4050158 +#define HIZCRB 0xA405015A +#define HIZCRC 0xA405015C +#define HIZCRD 0xA405015E +#define MSELCRA 0xA4050180 +#define MSELCRB 0xA4050182 +#define PULCR 0xA4050184 +#define DRVCRA 0xA405018A +#define DRVCRB 0xA405018C + +/* I/O Port */ +#define PADR 0xA4050120 +#define PBDR 0xA4050122 +#define PCDR 0xA4050124 +#define PDDR 0xA4050126 +#define PEDR 0xA4050128 +#define PFDR 0xA405012A +#define PGDR 0xA405012C +#define PHDR 0xA405012E +#define PJDR 0xA4050130 +#define PKDR 0xA4050132 +#define PLDR 0xA4050134 +#define PMDR 0xA4050136 +#define PNDR 0xA4050138 +#define PQDR 0xA405013A +#define PRDR 0xA405013C +#define PSDR 0xA405013E +#define PTDR 0xA4050160 +#define PUDR 0xA4050162 +#define PVDR 0xA4050164 +#define PWDR 0xA4050166 +#define PYDR 0xA4050168 +#define PZDR 0xA405016A + +/* Ether */ +#define EDMR 0xA4600000 + +/* UBC */ +/* H-UDI */ + +#endif /* _ASM_CPU_SH7724_H_ */ diff --git a/arch/sh/lib/Makefile b/arch/sh/lib/Makefile index 6aaf55a..256811a 100644 --- a/arch/sh/lib/Makefile +++ b/arch/sh/lib/Makefile @@ -28,6 +28,7 @@ GLSOBJS += ashiftrt.o GLSOBJS += ashiftlt.o GLSOBJS += lshiftrt.o GLSOBJS += ashldi3.o +GLSOBJS += ashrsi3.o GLSOBJS += lshrdi3.o GLSOBJS += movmem.o diff --git a/arch/sh/lib/ashrsi3.S b/arch/sh/lib/ashrsi3.S new file mode 100644 index 0000000..6f3cf46 --- /dev/null +++ b/arch/sh/lib/ashrsi3.S @@ -0,0 +1,185 @@ +/* Copyright (C) 1994, 1995, 1997, 1998, 1999, 2000, 2001, 2002, 2003, + 2004, 2005, 2006 + Free Software Foundation, Inc. + +This file is free software; you can redistribute it and/or modify it +under the terms of the GNU General Public License as published by the +Free Software Foundation; either version 2, or (at your option) any +later version. + +In addition to the permissions in the GNU General Public License, the +Free Software Foundation gives you unlimited permission to link the +compiled version of this file into combinations with other programs, +and to distribute those combinations without any restriction coming +from the use of this file. (The General Public License restrictions +do apply in other respects; for example, they cover modification of +the file, and distribution when not linked into a combine +executable.) + +This file is distributed in the hope that it will be useful, but +WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +General Public License for more details. + +You should have received a copy of the GNU General Public License +along with this program; see the file COPYING. If not, write to +the Free Software Foundation, 51 Franklin Street, Fifth Floor, +Boston, MA 02110-1301, USA. */ + +!! libgcc routines for the Renesas / SuperH SH CPUs. +!! Contributed by Steve Chamberlain. +!! sac@cygnus.com + +!! ashiftrt_r4_x, ___ashrsi3, ___ashlsi3, ___lshrsi3 routines +!! recoded in assembly by Toshiyasu Morita +!! tm@netcom.com + +/* SH2 optimizations for ___ashrsi3, ___ashlsi3, ___lshrsi3 and + ELF local label prefixes by J"orn Rennecke + amylaar@cygnus.com */ + +! +! __ashrsi3 +! +! Entry: +! +! r4: Value to shift +! r5: Shifts +! +! Exit: +! +! r0: Result +! +! Destroys: +! +! (none) +! + + .global __ashrsi3 + + .align 2 +__ashrsi3: + mov #31,r0 + and r0,r5 + mova ashrsi3_table,r0 + mov.b @(r0,r5),r5 +#ifdef __sh1__ + add r5,r0 + jmp @r0 +#else + braf r5 +#endif + mov r4,r0 + + .align 2 +ashrsi3_table: + .byte ashrsi3_0-ashrsi3_table + .byte ashrsi3_1-ashrsi3_table + .byte ashrsi3_2-ashrsi3_table + .byte ashrsi3_3-ashrsi3_table + .byte ashrsi3_4-ashrsi3_table + .byte ashrsi3_5-ashrsi3_table + .byte ashrsi3_6-ashrsi3_table + .byte ashrsi3_7-ashrsi3_table + .byte ashrsi3_8-ashrsi3_table + .byte ashrsi3_9-ashrsi3_table + .byte ashrsi3_10-ashrsi3_table + .byte ashrsi3_11-ashrsi3_table + .byte ashrsi3_12-ashrsi3_table + .byte ashrsi3_13-ashrsi3_table + .byte ashrsi3_14-ashrsi3_table + .byte ashrsi3_15-ashrsi3_table + .byte ashrsi3_16-ashrsi3_table + .byte ashrsi3_17-ashrsi3_table + .byte ashrsi3_18-ashrsi3_table + .byte ashrsi3_19-ashrsi3_table + .byte ashrsi3_20-ashrsi3_table + .byte ashrsi3_21-ashrsi3_table + .byte ashrsi3_22-ashrsi3_table + .byte ashrsi3_23-ashrsi3_table + .byte ashrsi3_24-ashrsi3_table + .byte ashrsi3_25-ashrsi3_table + .byte ashrsi3_26-ashrsi3_table + .byte ashrsi3_27-ashrsi3_table + .byte ashrsi3_28-ashrsi3_table + .byte ashrsi3_29-ashrsi3_table + .byte ashrsi3_30-ashrsi3_table + .byte ashrsi3_31-ashrsi3_table + +ashrsi3_31: + rotcl r0 + rts + subc r0,r0 + +ashrsi3_30: + shar r0 +ashrsi3_29: + shar r0 +ashrsi3_28: + shar r0 +ashrsi3_27: + shar r0 +ashrsi3_26: + shar r0 +ashrsi3_25: + shar r0 +ashrsi3_24: + shlr16 r0 + shlr8 r0 + rts + exts.b r0,r0 + +ashrsi3_23: + shar r0 +ashrsi3_22: + shar r0 +ashrsi3_21: + shar r0 +ashrsi3_20: + shar r0 +ashrsi3_19: + shar r0 +ashrsi3_18: + shar r0 +ashrsi3_17: + shar r0 +ashrsi3_16: + shlr16 r0 + rts + exts.w r0,r0 + +ashrsi3_15: + shar r0 +ashrsi3_14: + shar r0 +ashrsi3_13: + shar r0 +ashrsi3_12: + shar r0 +ashrsi3_11: + shar r0 +ashrsi3_10: + shar r0 +ashrsi3_9: + shar r0 +ashrsi3_8: + shar r0 +ashrsi3_7: + shar r0 +ashrsi3_6: + shar r0 +ashrsi3_5: + shar r0 +ashrsi3_4: + shar r0 +ashrsi3_3: + shar r0 +ashrsi3_2: + shar r0 +ashrsi3_1: + rts + shar r0 + +ashrsi3_0: + rts + nop diff --git a/board/renesas/ecovec/Makefile b/board/renesas/ecovec/Makefile new file mode 100644 index 0000000..8fdc0c9 --- /dev/null +++ b/board/renesas/ecovec/Makefile @@ -0,0 +1,38 @@ +# +# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org> +# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := ecovec.o +SOBJS := lowlevel_init.o + +$(LIB): $(obj).depend $(COBJS) $(SOBJS) + $(call cmd_link_o_target, $(COBJS) $(SOBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/renesas/ecovec/ecovec.c b/board/renesas/ecovec/ecovec.c new file mode 100644 index 0000000..275b0ba --- /dev/null +++ b/board/renesas/ecovec/ecovec.c @@ -0,0 +1,124 @@ +/* + * Copyright (C) 2009, 2011 Renesas Solutions Corp. + * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> + * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> +#include <asm/processor.h> +#include <i2c.h> +#include <netdev.h> + +/* USB power management register */ +#define UPONCR0 0xA40501D4 + +int checkboard(void) +{ + puts("BOARD: ecovec\n"); + return 0; +} + +int dram_init(void) +{ + DECLARE_GLOBAL_DATA_PTR; + + gd->bd->bi_memstart = CONFIG_SYS_SDRAM_BASE; + gd->bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE; + printf("DRAM: %dMB\n", CONFIG_SYS_SDRAM_SIZE / (1024 * 1024)); + return 0; +} + +static void debug_led(u8 led) +{ + /* PDGR[0-4] is debug LED */ + outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR); +} + +int board_late_init(void) +{ + u8 mac[6]; + char env_mac[17]; + int i; + + udelay(1000); + + /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/ + outw(inw(PLCR) & ~0xFFF0, PLCR); + outw(inw(PNCR) & ~0x000F, PNCR); + outw(inw(PXCR) & ~0x0FC0, PXCR); + outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB); + outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC); + outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE); + + debug_led(1 << 3); + + outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2); + + i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); + i2c_set_bus_num(CONFIG_SYS_I2C_MODULE); /* Use I2C 1 */ + + /* Read MAC address */ + i2c_read(0x50, 0x10, 0, mac, 6); + + /* Set MAC address */ + sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X", + mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]); + setenv("ethaddr", env_mac); + + debug_led(0x0F); + + return 0; +} + +int board_init(void) +{ + + /* LED (PTG) */ + outw((inw(PGCR) & ~0xFF) | 0x66, PGCR); + outw((inw(HIZCRA) & ~0x02), HIZCRA); + + debug_led(1 << 0); + + /* SCIF0 (PTF, PTM) */ + outw(inw(PFCR) & ~0x30, PFCR); + outw(inw(PMCR) & ~0x0C, PMCR); + outw((inw(PSELA) & ~0x40) | 0x40, PSELA); + + debug_led(1 << 1); + + /* RMII (PTA) */ + outw((inw(PACR) & ~0x0C) | 0x04, PACR); + outb((inb(PADR) & ~0x02) | 0x02, PADR); + + debug_led(1 << 2); + + /* USB host */ + outw((inw(PBCR) & ~0x300) | 0x100, PBCR); + outb((inb(PBDR) & ~0x10) | 0x10, PBDR); + outl(inl(MSTPCR2) & 0x100000, MSTPCR2); + outw(0x0600, UPONCR0); + + debug_led(1 << 3); + + /* debug switch */ + outw((inw(PVCR) & ~0x03) | 0x02 , PVCR); + + return 0; +} diff --git a/board/renesas/ecovec/lowlevel_init.S b/board/renesas/ecovec/lowlevel_init.S new file mode 100644 index 0000000..9fc63e0 --- /dev/null +++ b/board/renesas/ecovec/lowlevel_init.S @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2011 Renesas Solutions Corp. + * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com> + * + * board/renesas/ecovec/lowlevel_init.S + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> +#include <asm/processor.h> +#include <asm/macro.h> +#include <configs/ecovec.h> + + .global lowlevel_init + + .text + .align 2 + +lowlevel_init: + + /* jump to 0xA0020000 if bit 1 of PVDR_A */ + mov.l PVDR_A, r1 + mov.l PVDR_D, r2 + mov.b @r1, r0 + tst r0, r2 + bt 1f + mov.l JUMP_A, r1 + jmp @r1 + nop + +1: + /* Disable watchdog */ + write16 RWTCSR_A, RWTCSR_D + + /* MMU Disable */ + write32 MMUCR_A, MMUCR_D + + /* Setup clocks */ + write32 PLLCR_A, PLLCR_D + write32 FRQCRA_A, FRQCRA_D + write32 FRQCRB_A, FRQCRB_D + + wait_timer TIMER_D + + write32 MMSELR_A, MMSELR_D + + /* Srtup BSC */ + write32 CMNCR_A, CMNCR_D + write32 CS0BCR_A, CS0BCR_D + write32 CS0WCR_A, CS0WCR_D + + wait_timer TIMER_D + + /* Setup SDRAM */ + write32 DBPDCNT0_A, DBPDCNT0_D0 + write32 DBCONF_A, DBCONF_D + write32 DBTR0_A, DBTR0_D + write32 DBTR1_A, DBTR1_D + write32 DBTR2_A, DBTR2_D + write32 DBTR3_A, DBTR3_D + write32 DBKIND_A, DBKIND_D + write32 DBCKECNT_A, DBCKECNT_D + + wait_timer TIMER_D + + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBMRCNT_A, DBMRCNT_D0 + write32 DBMRCNT_A, DBMRCNT_D1 + write32 DBMRCNT_A, DBMRCNT_D2 + write32 DBMRCNT_A, DBMRCNT_D3 + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBMRCNT_A, DBMRCNT_D4 + write32 DBMRCNT_A, DBMRCNT_D5 + write32 DBMRCNT_A, DBMRCNT_D6 + + wait_timer TIMER_D + + write32 DBEN_A, DBEN_D + write32 DBRFPDN1_A, DBRFPDN1_D + write32 DBRFPDN2_A, DBRFPDN2_D + write32 DBCMDCNT_A, DBCMDCNT_D0 + + + /* Dummy read */ + mov.l DUMMY_A ,r1 + synco + mov.l @r1, r0 + synco + + mov.l SDRAM_A ,r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + add #4, r1 + synco + mov.l @r1, r0 + synco + wait_timer TIMER_D + + write32 DBCMDCNT_A, DBCMDCNT_D0 + write32 DBCMDCNT_A, DBCMDCNT_D1 + write32 DBPDCNT0_A, DBPDCNT0_D1 + write32 DBRFPDN0_A, DBRFPDN0_D + + wait_timer TIMER_D + + write32 CCR_A, CCR_D + + stc sr, r0 + mov.l SR_MASK_D, r1 + and r1, r0 + ldc r0, sr + + rts + + .align 2 + +PVDR_A: .long PVDR +PVDR_D: .long 0x00000001 +JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR +TIMER_D: .long 64 +RWTCSR_A: .long RWTCSR +RWTCSR_D: .long 0x0000A507 +MMUCR_A: .long MMUCR +MMUCR_D: .long 0x00000004 +PLLCR_A: .long PLLCR +PLLCR_D: .long 0x00004000 +FRQCRA_A: .long FRQCRA +FRQCRA_D: .long 0x8E003508 +FRQCRB_A: .long FRQCRB +FRQCRB_D: .long 0x0 +MMSELR_A: .long MMSELR +MMSELR_D: .long 0xA5A50000 +CMNCR_A: .long CMNCR +CMNCR_D: .long 0x00000013 +CS0BCR_A: .long CS0BCR +CS0BCR_D: .long 0x11110400 +CS0WCR_A: .long CS0WCR +CS0WCR_D: .long 0x00000440 +DBPDCNT0_A: .long DBPDCNT0 +DBPDCNT0_D0: .long 0x00000181 +DBPDCNT0_D1: .long 0x00000080 +DBCONF_A: .long DBCONF +DBCONF_D: .long 0x015B0002 +DBTR0_A: .long DBTR0 +DBTR0_D: .long 0x03061502 +DBTR1_A: .long DBTR1 +DBTR1_D: .long 0x02020102 +DBTR2_A: .long DBTR2 +DBTR2_D: .long 0x01090305 +DBTR3_A: .long DBTR3 +DBTR3_D: .long 0x00000002 +DBKIND_A: .long DBKIND +DBKIND_D: .long 0x00000005 +DBCKECNT_A: .long DBCKECNT +DBCKECNT_D: .long 0x00000001 +DBCMDCNT_A: .long DBCMDCNT +DBCMDCNT_D0:.long 0x2 +DBCMDCNT_D1:.long 0x4 +DBMRCNT_A: .long DBMRCNT +DBMRCNT_D0: .long 0x00020000 +DBMRCNT_D1: .long 0x00030000 +DBMRCNT_D2: .long 0x00010040 +DBMRCNT_D3: .long 0x00000532 +DBMRCNT_D4: .long 0x00000432 +DBMRCNT_D5: .long 0x000103C0 +DBMRCNT_D6: .long 0x00010040 +DBEN_A: .long DBEN +DBEN_D: .long 0x01 +DBRFPDN0_A: .long DBRFPDN0 +DBRFPDN1_A: .long DBRFPDN1 +DBRFPDN2_A: .long DBRFPDN2 +DBRFPDN0_D: .long 0x00010000 +DBRFPDN1_D: .long 0x00000613 +DBRFPDN2_D: .long 0x238C003A +SDRAM_A: .long 0xa8000000 +DUMMY_A: .long 0x0c400000 +CCR_A: .long CCR +CCR_D: .long 0x0000090B +SR_MASK_D: .long 0xEFFFFF0F diff --git a/board/renesas/sh7757lcr/lowlevel_init.S b/board/renesas/sh7757lcr/lowlevel_init.S index ab1aa49..5090fd0 100644 --- a/board/renesas/sh7757lcr/lowlevel_init.S +++ b/board/renesas/sh7757lcr/lowlevel_init.S @@ -326,12 +326,13 @@ PC_MASK: .long 0x20000000 /* step 26 */ wait_DBCMD +#if defined(CONFIG_SH7757LCR_DDR_ECC) /* enable DDR-ECC */ write32 ECD_ECDEN_A, ECD_ECDEN_D write32 ECD_INTSR_A, ECD_INTSR_D write32 ECD_SPACER_A, ECD_SPACER_D write32 ECD_MCR_A, ECD_MCR_D - +#endif bra exit_ddr nop @@ -993,6 +993,7 @@ sh7763rdp sh sh4 sh7763rdp renesas sh7785lcr sh sh4 sh7785lcr renesas - sh7785lcr_32bit sh sh4 sh7785lcr renesas - sh7785lcr:SH_32BIT=1 MigoR sh sh4 MigoR renesas - +ecovec sh sh4 ecovec renesas - grsim_leon2 sparc leon2 - gaisler gr_cpci_ax2000 sparc leon3 - gaisler gr_ep2s60 sparc leon3 - gaisler diff --git a/doc/README.sh7757lcr b/doc/README.sh7757lcr index 49fea50..109f715 100644 --- a/doc/README.sh7757lcr +++ b/doc/README.sh7757lcr @@ -61,3 +61,17 @@ You can write MAC address to SPI ROM. ETHERC ch1 = 00:00:87:6c:21:81 GETHERC ch0 = 00:00:87:6c:21:82 GETHERC ch1 = 00:00:87:6c:21:83 + + +Update SPI ROM: +============================ + +1. Copy u-boot image to RAM area. +2. Probe SPI device. + => sf probe 0 + 8192 KiB M25P64 at 0:0 is now current device +3. Erase SPI ROM. + => sf erase 0 80000 +4. Write u-boot image to SPI ROM. + => sf write 0x89000000 0 80000 + diff --git a/drivers/net/sh_eth.c b/drivers/net/sh_eth.c index 17dd0d2..27d0401 100644 --- a/drivers/net/sh_eth.c +++ b/drivers/net/sh_eth.c @@ -25,6 +25,7 @@ #include <malloc.h> #include <net.h> #include <netdev.h> +#include <miiphy.h> #include <asm/errno.h> #include <asm/io.h> @@ -45,144 +46,6 @@ #define SH_ETH_PHY_DELAY 50000 -/* - * Bits are written to the PHY serially using the - * PIR register, just like a bit banger. - */ -static void sh_eth_mii_write_phy_bits(int port, u32 val, int len) -{ - int i; - u32 pir; - - /* Bit positions is 1 less than the number of bits */ - for (i = len - 1; i >= 0; i--) { - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is high */ - pir = 3 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - /* Write direction, bit to write, clock is low */ - pir = 2 | ((val & 1 << i) ? 1 << 2 : 0); - outl(pir, PIR(port)); - udelay(1); - } -} - -static void sh_eth_mii_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} - -static void sh_eth_mii_ind_bus_release(int port) -{ - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); -} - -static void sh_eth_mii_read_phy_bits(int port, u32 *val, int len) -{ - int i; - u32 pir; - - *val = 0; - for (i = len - 1; i >= 0; i--) { - /* Read direction, clock is high */ - outl(1, PIR(port)); - udelay(1); - /* Read bit */ - pir = inl(PIR(port)); - *val |= (pir & 8) ? 1 << i : 0; - /* Read direction, clock is low */ - outl(0, PIR(port)); - udelay(1); - } -} - -#define PHY_INIT 0xFFFFFFFF -#define PHY_READ 0x02 -#define PHY_WRITE 0x01 -/* - * To read a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (Bus release): - * data (16 bits): read data - */ -static u32 sh_eth_mii_read_phy_reg(int port, u8 phy_addr, int reg) -{ - u32 val; - - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - - /* Bus release */ - sh_eth_mii_bus_release(port); - - /* Read register */ - sh_eth_mii_read_phy_bits(port, &val, 16); - - return val; -} - -/* - * To write a phy register, mii managements frames are sent to the phy. - * The frames look like this: - * pre (32 bits): 0xffff ffff - * st (2 bits): 01 - * op (2bits): 10: read 01: write - * phyad (5 bits): xxxxx - * regad (5 bits): xxxxx - * ta (2 bits): 10 - * data (16 bits): write data - * idle (Independent bus release) - */ -static void sh_eth_mii_write_phy_reg(int port, u8 phy_addr, int reg, u16 val) -{ - /* Sent mii management frame */ - /* pre */ - sh_eth_mii_write_phy_bits(port, PHY_INIT, 32); - /* st (start of frame) */ - sh_eth_mii_write_phy_bits(port, 0x1, 2); - /* op (code) */ - sh_eth_mii_write_phy_bits(port, PHY_WRITE, 2); - /* phy address */ - sh_eth_mii_write_phy_bits(port, phy_addr, 5); - /* Register to read */ - sh_eth_mii_write_phy_bits(port, reg, 5); - /* ta */ - sh_eth_mii_write_phy_bits(port, PHY_READ, 2); - /* Write register data */ - sh_eth_mii_write_phy_bits(port, val, 16); - - /* Independent bus release */ - sh_eth_mii_ind_bus_release(port); -} - int sh_eth_send(struct eth_device *dev, volatile void *packet, int len) { struct sh_eth_dev *eth = dev->priv; @@ -480,62 +343,26 @@ err_tx_init: static int sh_eth_phy_config(struct sh_eth_dev *eth) { - int port = eth->port, timeout, ret = 0; + int port = eth->port, ret = 0; struct sh_eth_info *port_info = ð->port_info[port]; - u32 val; - - /* Reset phy */ - sh_eth_mii_write_phy_reg - (port, port_info->phy_addr, PHY_CTRL, PHY_C_RESET); - timeout = 10; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, - port_info->phy_addr, PHY_CTRL); - if (!(val & PHY_C_RESET)) - break; - udelay(SH_ETH_PHY_DELAY); - } - - if (timeout < 0) { - printf(SHETHER_NAME ": phy reset timeout\n"); - ret = -EIO; - goto err_tout; - } - - /* Advertise 100/10 baseT full/half duplex */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_ANA, - (PHY_A_FDX|PHY_A_HDX|PHY_A_10FDX|PHY_A_10HDX|PHY_A_EXT)); - /* Autonegotiation, normal operation, full duplex, enable tx */ - sh_eth_mii_write_phy_reg(port, port_info->phy_addr, PHY_CTRL, - (PHY_C_ANEGEN|PHY_C_RANEG)); - /* Wait for autonegotiation to complete */ - timeout = 100; - while (timeout--) { - val = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); - if (val & PHY_S_ANEGC) - break; - - udelay(SH_ETH_PHY_DELAY); - } - - if (timeout < 0) { - printf(SHETHER_NAME ": phy auto-negotiation failed\n"); - ret = -ETIMEDOUT; - goto err_tout; - } + struct eth_device *dev = port_info->dev; + struct phy_device *phydev; - return ret; + phydev = phy_connect(miiphy_get_dev_by_name(dev->name), + port_info->phy_addr, dev, PHY_INTERFACE_MODE_MII); + port_info->phydev = phydev; + phy_config(phydev); -err_tout: return ret; } static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) { int port = eth->port, ret = 0; - u32 val, phy_status; + u32 val; struct sh_eth_info *port_info = ð->port_info[port]; struct eth_device *dev = port_info->dev; + struct phy_device *phy; /* Configure e-dmac registers */ outl((inl(EDMR(port)) & ~EMDR_DESC_R) | EDMR_EL, EDMR(port)); @@ -582,31 +409,31 @@ static int sh_eth_config(struct sh_eth_dev *eth, bd_t *bd) printf(SHETHER_NAME ": phy config timeout\n"); goto err_phy_cfg; } - /* Read phy status to finish configuring the e-mac */ - phy_status = sh_eth_mii_read_phy_reg(port, port_info->phy_addr, 1); + phy = port_info->phydev; + phy_startup(phy); /* Set the transfer speed */ #ifdef CONFIG_CPU_SH7763 - if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { + if (phy->speed == 100) { printf(SHETHER_NAME ": 100Base/"); outl(GECMR_100B, GECMR(port)); - } else { + } else if (phy->speed == 10) { printf(SHETHER_NAME ": 10Base/"); outl(GECMR_10B, GECMR(port)); } #endif #if defined(CONFIG_CPU_SH7757) - if (phy_status & (PHY_S_100X_F|PHY_S_100X_H)) { + if (phy->speed == 100) { printf("100Base/"); outl(1, RTRATE(port)); - } else { + } else if (phy->speed == 10) { printf("10Base/"); outl(0, RTRATE(port)); } #endif /* Check if full duplex mode is supported by the phy */ - if (phy_status & (PHY_S_100X_F|PHY_S_10T_F)) { + if (phy->duplex) { printf("Full\n"); outl((ECMR_CHG_DM|ECMR_RE|ECMR_TE|ECMR_DM), ECMR(port)); } else { @@ -707,6 +534,9 @@ int sh_eth_initialize(bd_t *bd) /* Register Device to EtherNet subsystem */ eth_register(dev); + bb_miiphy_buses[0].priv = eth; + miiphy_register(dev->name, bb_miiphy_read, bb_miiphy_write); + if (!eth_getenv_enetaddr("ethaddr", dev->enetaddr)) puts("Please set MAC address\n"); @@ -722,3 +552,86 @@ err: printf(SHETHER_NAME ": Failed\n"); return ret; } + +/******* for bb_miiphy *******/ +static int sh_eth_bb_init(struct bb_miiphy_bus *bus) +{ + return 0; +} + +static int sh_eth_bb_mdio_active(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + outl(inl(PIR(port)) | PIR_MMD, PIR(port)); + + return 0; +} + +static int sh_eth_bb_mdio_tristate(struct bb_miiphy_bus *bus) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + outl(inl(PIR(port)) & ~PIR_MMD, PIR(port)); + + return 0; +} + +static int sh_eth_bb_set_mdio(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + if (v) + outl(inl(PIR(port)) | PIR_MDO, PIR(port)); + else + outl(inl(PIR(port)) & ~PIR_MDO, PIR(port)); + + return 0; +} + +static int sh_eth_bb_get_mdio(struct bb_miiphy_bus *bus, int *v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + *v = (inl(PIR(port)) & PIR_MDI) >> 3; + + return 0; +} + +static int sh_eth_bb_set_mdc(struct bb_miiphy_bus *bus, int v) +{ + struct sh_eth_dev *eth = bus->priv; + int port = eth->port; + + if (v) + outl(inl(PIR(port)) | PIR_MDC, PIR(port)); + else + outl(inl(PIR(port)) & ~PIR_MDC, PIR(port)); + + return 0; +} + +static int sh_eth_bb_delay(struct bb_miiphy_bus *bus) +{ + udelay(10); + + return 0; +} + +struct bb_miiphy_bus bb_miiphy_buses[] = { + { + .name = "sh_eth", + .init = sh_eth_bb_init, + .mdio_active = sh_eth_bb_mdio_active, + .mdio_tristate = sh_eth_bb_mdio_tristate, + .set_mdio = sh_eth_bb_set_mdio, + .get_mdio = sh_eth_bb_get_mdio, + .set_mdc = sh_eth_bb_set_mdc, + .delay = sh_eth_bb_delay, + } +}; +int bb_miiphy_buses_num = ARRAY_SIZE(bb_miiphy_buses); diff --git a/drivers/net/sh_eth.h b/drivers/net/sh_eth.h index 51e5d5b..dd6a422 100644 --- a/drivers/net/sh_eth.h +++ b/drivers/net/sh_eth.h @@ -89,6 +89,7 @@ struct sh_eth_info { u8 mac_addr[6]; u8 phy_addr; struct eth_device *dev; + struct phy_device *phydev; }; struct sh_eth_dev { @@ -435,61 +436,3 @@ enum FIFO_SIZE_BIT { FIFO_SIZE_T = 0x00000700, FIFO_SIZE_R = 0x00000007, }; -enum PHY_OFFSETS { - PHY_CTRL = 0, PHY_STAT = 1, PHY_IDT1 = 2, PHY_IDT2 = 3, - PHY_ANA = 4, PHY_ANL = 5, PHY_ANE = 6, - PHY_16 = 16, -}; - -/* PHY_CTRL */ -enum PHY_CTRL_BIT { - PHY_C_RESET = 0x8000, PHY_C_LOOPBK = 0x4000, PHY_C_SPEEDSL = 0x2000, - PHY_C_ANEGEN = 0x1000, PHY_C_PWRDN = 0x0800, PHY_C_ISO = 0x0400, - PHY_C_RANEG = 0x0200, PHY_C_DUPLEX = 0x0100, PHY_C_COLT = 0x0080, -}; -#define DM9161_PHY_C_ANEGEN 0 /* auto nego special */ - -/* PHY_STAT */ -enum PHY_STAT_BIT { - PHY_S_100T4 = 0x8000, PHY_S_100X_F = 0x4000, PHY_S_100X_H = 0x2000, - PHY_S_10T_F = 0x1000, PHY_S_10T_H = 0x0800, PHY_S_ANEGC = 0x0020, - PHY_S_RFAULT = 0x0010, PHY_S_ANEGA = 0x0008, PHY_S_LINK = 0x0004, - PHY_S_JAB = 0x0002, PHY_S_EXTD = 0x0001, -}; - -/* PHY_ANA */ -enum PHY_ANA_BIT { - PHY_A_NP = 0x8000, PHY_A_ACK = 0x4000, PHY_A_RF = 0x2000, - PHY_A_FCS = 0x0400, PHY_A_T4 = 0x0200, PHY_A_FDX = 0x0100, - PHY_A_HDX = 0x0080, PHY_A_10FDX = 0x0040, PHY_A_10HDX = 0x0020, - PHY_A_SEL = 0x001e, - PHY_A_EXT = 0x0001, -}; - -/* PHY_ANL */ -enum PHY_ANL_BIT { - PHY_L_NP = 0x8000, PHY_L_ACK = 0x4000, PHY_L_RF = 0x2000, - PHY_L_FCS = 0x0400, PHY_L_T4 = 0x0200, PHY_L_FDX = 0x0100, - PHY_L_HDX = 0x0080, PHY_L_10FDX = 0x0040, PHY_L_10HDX = 0x0020, - PHY_L_SEL = 0x001f, -}; - -/* PHY_ANE */ -enum PHY_ANE_BIT { - PHY_E_PDF = 0x0010, PHY_E_LPNPA = 0x0008, PHY_E_NPA = 0x0004, - PHY_E_PRX = 0x0002, PHY_E_LPANEGA = 0x0001, -}; - -/* DM9161 */ -enum PHY_16_BIT { - PHY_16_BP4B45 = 0x8000, PHY_16_BPSCR = 0x4000, PHY_16_BPALIGN = 0x2000, - PHY_16_BP_ADPOK = 0x1000, PHY_16_Repeatmode = 0x0800, - PHY_16_TXselect = 0x0400, - PHY_16_Rsvd = 0x0200, PHY_16_RMIIEnable = 0x0100, - PHY_16_Force100LNK = 0x0080, - PHY_16_APDLED_CTL = 0x0040, PHY_16_COLLED_CTL = 0x0020, - PHY_16_RPDCTR_EN = 0x0010, - PHY_16_ResetStMch = 0x0008, PHY_16_PreamSupr = 0x0004, - PHY_16_Sleepmode = 0x0002, - PHY_16_RemoteLoopOut = 0x0001, -}; diff --git a/include/configs/ecovec.h b/include/configs/ecovec.h new file mode 100644 index 0000000..2e2a9a7 --- /dev/null +++ b/include/configs/ecovec.h @@ -0,0 +1,200 @@ +/* + * Configuation settings for the Renesas Solutions ECOVEC board + * + * Copyright (C) 2009 - 2011 Renesas Solutions Corp. + * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com> + * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __ECOVEC_H +#define __ECOVEC_H + +/* + * Address Interface BusWidth + *----------------------------------------- + * 0x0000_0000 U-Boot 16bit + * 0x0004_0000 Linux romImage 16bit + * 0x0014_0000 MTD for Linux 16bit + * 0x0400_0000 Internal I/O 16/32bit + * 0x0800_0000 DRAM 32bit + * 0x1800_0000 MFI 16bit + */ + +#undef DEBUG +#define CONFIG_SH 1 +#define CONFIG_SH4 1 +#define CONFIG_SH4A 1 +#define CONFIG_CPU_SH7724 1 +#define BOARD_LATE_INIT 1 +#define CONFIG_ECOVEC 1 + +#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000 +#define CONFIG_SYS_TEXT_BASE 0x8FFC0000 + +#define CONFIG_CMD_FLASH +#define CONFIG_CMD_MEMORY +#define CONFIG_CMD_NET +#define CONFIG_CMD_PING +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SDRAM +#define CONFIG_CMD_ENV +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_SAVEENV + +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_BOOTARGS "console=ttySC0,115200" + +#define CONFIG_VERSION_VARIABLE +#undef CONFIG_SHOW_BOOT_PROGRESS + +/* I2C */ +#define CONFIG_CMD_I2C +#define CONFIG_SH_I2C 1 +#define CONFIG_HARD_I2C 1 +#define CONFIG_I2C_MULTI_BUS 1 +#define CONFIG_SYS_MAX_I2C_BUS 2 +#define CONFIG_SYS_I2C_MODULE 1 +#define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */ +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SH_I2C_DATA_HIGH 4 +#define CONFIG_SH_I2C_DATA_LOW 5 +#define CONFIG_SH_I2C_CLOCK 41666666 +#define CONFIG_SH_I2C_BASE0 0xA4470000 +#define CONFIG_SH_I2C_BASE1 0xA4750000 + +/* Ether */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_SH_ETHER 1 +#define CONFIG_SH_ETHER_USE_PORT (0) +#define CONFIG_SH_ETHER_PHY_ADDR (0x1f) +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI + +/* USB / R8A66597 */ +#define CONFIG_USB_R8A66597_HCD +#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000 +#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ +#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ +#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ +#define CONFIG_SUPERH_ON_CHIP_R8A66597 + +/* undef to save memory */ +#define CONFIG_SYS_LONGHELP +/* Monitor Command Prompt */ +#define CONFIG_SYS_PROMPT "=> " +/* Buffer size for input from the Console */ +#define CONFIG_SYS_CBSIZE 256 +/* Buffer size for Console output */ +#define CONFIG_SYS_PBSIZE 256 +/* max args accepted for monitor commands */ +#define CONFIG_SYS_MAXARGS 16 +/* Buffer size for Boot Arguments passed to kernel */ +#define CONFIG_SYS_BARGSIZE 512 +/* List of legal baudrate settings for this board */ +#define CONFIG_SYS_BAUDRATE_TABLE { 115200 } + +/* SCIF */ +#define CONFIG_SCIF_CONSOLE 1 +#define CONFIG_SCIF 1 +#define CONFIG_CONS_SCIF0 1 + +/* Suppress display of console information at boot */ +#undef CONFIG_SYS_CONSOLE_INFO_QUIET +#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE + +/* SDRAM */ +#define CONFIG_SYS_SDRAM_BASE (0x88000000) +#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024) +#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) + +#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE) +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024) +/* Enable alternate, more extensive, memory test */ +#undef CONFIG_SYS_ALT_MEMTEST +/* Scratch address used by the alternate memory test */ +#undef CONFIG_SYS_MEMTEST_SCRATCH + +/* Enable temporary baudrate change while serial download */ +#undef CONFIG_SYS_LOADS_BAUD_CHANGE + +/* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER 1 +#define CONFIG_SYS_FLASH_CFI +#undef CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_BASE (0xA0000000) +#define CONFIG_SYS_MAX_FLASH_SECT 512 + +/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } + +/* Timeout for Flash erase operations (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) +/* Timeout for Flash write operations (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) +/* Timeout for Flash set sector lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) +/* Timeout for Flash clear lock bit operations (in ms) */ +#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) + +/* + * Use hardware flash sectors protection instead + * of U-Boot software protection + */ +#undef CONFIG_SYS_FLASH_PROTECTION +#undef CONFIG_SYS_DIRECT_FLASH_TFTP + +/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ +#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE) +/* Monitor size */ +#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +/* Size of DRAM reserved for malloc() use */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE (256) +#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) + +/* ENV setting */ +#define CONFIG_ENV_IS_IN_FLASH +#define CONFIG_ENV_OVERWRITE 1 +#define CONFIG_ENV_SECT_SIZE (128 * 1024) +#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) +#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) +/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ +#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) +#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) + +/* Board Clock */ +#define CONFIG_SYS_CLK_FREQ 41666666 +#define CONFIG_SYS_TMU_CLK_DIV 4 +#define CONFIG_SYS_HZ 1000 + +#endif /* __ECOVEC_H */ diff --git a/include/configs/espt.h b/include/configs/espt.h index 38058c7..3df1fae 100644 --- a/include/configs/espt.h +++ b/include/configs/espt.h @@ -39,6 +39,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET +#define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_ENV #define CONFIG_CMD_NFS @@ -120,5 +121,8 @@ #define CONFIG_SH_ETHER 1 #define CONFIG_SH_ETHER_USE_PORT (1) #define CONFIG_SH_ETHER_PHY_ADDR (0x00) +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI #endif /* __SH7763RDP_H */ diff --git a/include/configs/sh7757lcr.h b/include/configs/sh7757lcr.h index 2d6eb33..c1f9ce8 100644 --- a/include/configs/sh7757lcr.h +++ b/include/configs/sh7757lcr.h @@ -31,12 +31,14 @@ #define CONFIG_SH_32BIT 1 #define CONFIG_CPU_SH7757 1 #define CONFIG_SH7757LCR 1 +#define CONFIG_SH7757LCR_DDR_ECC 1 #define CONFIG_SYS_TEXT_BASE 0x8ef80000 #define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds" #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET +#define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_NFS #define CONFIG_CMD_DFL @@ -101,6 +103,9 @@ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 1 #define CONFIG_SH_ETHER_CACHE_WRITEBACK 1 +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI #define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000 #define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024) diff --git a/include/configs/sh7763rdp.h b/include/configs/sh7763rdp.h index b8eb13d..59728f5 100644 --- a/include/configs/sh7763rdp.h +++ b/include/configs/sh7763rdp.h @@ -39,6 +39,7 @@ #define CONFIG_CMD_FLASH #define CONFIG_CMD_MEMORY #define CONFIG_CMD_NET +#define CONFIG_CMD_MII #define CONFIG_CMD_PING #define CONFIG_CMD_SAVEENV #define CONFIG_CMD_NFS @@ -120,5 +121,8 @@ #define CONFIG_SH_ETHER 1 #define CONFIG_SH_ETHER_USE_PORT (1) #define CONFIG_SH_ETHER_PHY_ADDR (0x01) +#define CONFIG_PHYLIB +#define CONFIG_BITBANGMII +#define CONFIG_BITBANGMII_MULTI #endif /* __SH7763RDP_H */ |