diff options
| -rw-r--r-- | include/ioports.h | 51 | ||||
| -rw-r--r-- | include/mpc8260_irq.h | 41 |
2 files changed, 92 insertions, 0 deletions
diff --git a/include/ioports.h b/include/ioports.h new file mode 100644 index 0000000..8f5947f --- /dev/null +++ b/include/ioports.h @@ -0,0 +1,51 @@ +/* + * definitions for MPC8260 I/O Ports + * + * (in addition to those provided in <asm/immap_8260.h>) + * + * Murray.Jensen@cmst.csiro.au, 20-Oct-00 + */ + +/* + * this structure mirrors the layout of the five port registers in + * the internal memory map - see iop8260_t in <asm/immap_8260.h> + */ +typedef struct { + unsigned int pdir; /* Port Data Direction Register (35-3) */ + unsigned int ppar; /* Port Pin Assignment Register (35-4) */ + unsigned int psor; /* Port Special Options Register (35-5) */ + unsigned int podr; /* Port Open Drain Register (35-2) */ + unsigned int pdat; /* Port Data Register (35-3) */ +} ioport_t; + +/* + * this macro calculates the address within the internal + * memory map (im) of the set of registers for a port (idx) + * + * the internal memory map aligns the above structure on + * a 0x20 byte boundary + */ +#define ioport_addr(im, idx) (ioport_t *)((uint)&(im)->im_ioport + ((idx)*0x20)) + +/* + * this structure provides configuration + * information for one port pin + */ +typedef struct { + unsigned char conf:1; /* if 1, configure this port */ + unsigned char ppar:1; /* Port Pin Assignment Register (35-4) */ + unsigned char psor:1; /* Port Special Options Register (35-2) */ + unsigned char pdir:1; /* Port Data Direction Register (35-3) */ + unsigned char podr:1; /* Port Open Drain Register (35-2) */ + unsigned char pdat:1; /* Port Data Register (35-2) */ +} iop_conf_t; + +/* + * a table that contains configuration information for all 32 pins + * of all four MPC8260 I/O ports. + * + * NOTE: in the second dimension of this table, index 0 refers to pin 31 + * and index 31 refers to pin 0. this made the code in the table look more + * like the table in the 8260UM (and in the hymod manuals). + */ +extern const iop_conf_t iop_conf_tab[4][32]; diff --git a/include/mpc8260_irq.h b/include/mpc8260_irq.h new file mode 100644 index 0000000..046dd32 --- /dev/null +++ b/include/mpc8260_irq.h @@ -0,0 +1,41 @@ +#ifndef _MPC8260_IRQ_H +#define _MPC8260_IRQ_H + +/****************************************************************************/ +/* most of this was ripped out of include/asm-ppc/irq.h from the Linux/PPC */ +/* source. There was no copyright information in the file. */ + +/* + * this is the # irq's for all ppc arch's (pmac/chrp/prep) + * so it is the max of them all + * + * [let's just worry about 8260 for now - mjj] + */ +#define NR_IRQS 64 + +/* The 8260 has an internal interrupt controller with a maximum of + * 64 IRQs. We will use NR_IRQs from above since it is large enough. + * Don't be confused by the 8260 documentation where they list an + * "interrupt number" and "interrupt vector". We are only interested + * in the interrupt vector. There are "reserved" holes where the + * vector number increases, but the interrupt number in the table does not. + * (Document errata updates have fixed this...make sure you have up to + * date processor documentation -- Dan). + */ +#define NR_SIU_INTS 64 + +/* There are many more than these, we will add them as we need them. +*/ +#define SIU_INT_SMC1 ((uint)0x04) +#define SIU_INT_SMC2 ((uint)0x05) +#define SIU_INT_FCC1 ((uint)0x20) +#define SIU_INT_FCC2 ((uint)0x21) +#define SIU_INT_FCC3 ((uint)0x22) +#define SIU_INT_SCC1 ((uint)0x28) +#define SIU_INT_SCC2 ((uint)0x29) +#define SIU_INT_SCC3 ((uint)0x2a) +#define SIU_INT_SCC4 ((uint)0x2b) + +#define NR_MASK_WORDS ((NR_IRQS + 31) / 32) + +#endif /* _MPC8260_IRQ_H */ |