diff options
| -rw-r--r-- | board/lwmon5/lwmon5.c | 17 | ||||
| -rw-r--r-- | board/lwmon5/sdram.c | 64 | ||||
| -rw-r--r-- | include/configs/lwmon5.h | 16 |
3 files changed, 87 insertions, 10 deletions
diff --git a/board/lwmon5/lwmon5.c b/board/lwmon5/lwmon5.c index d5b8f8c..d916284 100644 --- a/board/lwmon5/lwmon5.c +++ b/board/lwmon5/lwmon5.c @@ -19,9 +19,10 @@ */ #include <common.h> -#include <asm/processor.h> #include <ppc440.h> +#include <asm/processor.h> #include <asm/gpio.h> +#include <asm/io.h> DECLARE_GLOBAL_DATA_PTR; @@ -220,6 +221,13 @@ int misc_init_r(void) udelay(500); gpio_write_bit(CFG_GPIO_LIME_RST, 1); + /* Lime memory clock adjusted to 133MHz */ + out_be32((void *)CFG_LIME_SDRAM_CLOCK, CFG_LIME_CLOCK_133MHZ); + /* Wait untill time expired. Because of requirements in lime manual */ + udelay(300); + /* Write lime controller memory parameters */ + out_be32((void *)CFG_LIME_MMR, CFG_LIME_MMR_VALUE); + /* * Reset PHY's */ @@ -229,13 +237,6 @@ int misc_init_r(void) gpio_write_bit(CFG_GPIO_PHY0_RST, 1); gpio_write_bit(CFG_GPIO_PHY1_RST, 1); - /* - * Reset USB hub - */ - gpio_write_bit(CFG_GPIO_HUB_RST, 0); - udelay(100); - gpio_write_bit(CFG_GPIO_HUB_RST, 1); - return 0; } diff --git a/board/lwmon5/sdram.c b/board/lwmon5/sdram.c index 85811ad..9a4a8ee 100644 --- a/board/lwmon5/sdram.c +++ b/board/lwmon5/sdram.c @@ -474,8 +474,27 @@ static void program_ecc(u32 start_address, blank_string(strlen(str)); } else { /* ECC bit set method for cached memory */ +#if 1 /* test-only: will remove this define later, when ECC problems are solved! */ + /* + * Some boards (like lwmon5) need to preserve the memory + * content upon ECC generation (for the log-buffer). + * Therefore we don't fill the memory with a pattern or + * just zero it, but write the same values back that are + * already in the memory cells. + */ + address_increment = CFG_CACHELINE_SIZE; + end_address = current_address + num_bytes; + + current_address = start_address; + while (current_address < end_address) { + ppcDcbi(current_address); + ppcDcbf(current_address); + current_address += CFG_CACHELINE_SIZE; + } +#else dcbz_area(start_address, num_bytes); dflush(); +#endif } sync(); @@ -518,6 +537,8 @@ long int initdram (int board_type) { u32 val; +#if 0 /* test-only: will remove this define later, when ECC problems are solved! */ + /* CL=3 */ mtsdram(DDR0_02, 0x00000000); mtsdram(DDR0_00, 0x0000190A); @@ -558,6 +579,49 @@ long int initdram (int board_type) mtsdram(DDR0_43, 0x030A0200); mtsdram(DDR0_44, 0x00000003); mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ +#else + /* CL=4 */ + mtsdram(DDR0_02, 0x00000000); + + mtsdram(DDR0_00, 0x0000190A); + mtsdram(DDR0_01, 0x01000000); + mtsdram(DDR0_03, 0x02040803); /* A suitable burst length was taken. CAS is right for our board */ + + mtsdram(DDR0_04, 0x0B030300); + mtsdram(DDR0_05, 0x02020308); + mtsdram(DDR0_06, 0x0003C812); + mtsdram(DDR0_07, 0x00090100); + mtsdram(DDR0_08, 0x03c80001); + mtsdram(DDR0_09, 0x00011D5F); + mtsdram(DDR0_10, 0x00000300); + mtsdram(DDR0_11, 0x000CC800); + mtsdram(DDR0_12, 0x00000003); + mtsdram(DDR0_14, 0x00000000); + mtsdram(DDR0_17, 0x1e000000); + mtsdram(DDR0_18, 0x1e1e1e1e); + mtsdram(DDR0_19, 0x1e1e1e1e); + mtsdram(DDR0_20, 0x0B0B0B0B); + mtsdram(DDR0_21, 0x0B0B0B0B); +#ifdef CONFIG_DDR_ECC + mtsdram(DDR0_22, 0x00267F0B | DDR0_22_CTRL_RAW_ECC_ENABLE); /* enable ECC */ +#else + mtsdram(DDR0_22, 0x00267F0B); +#endif + + mtsdram(DDR0_23, 0x01000000); + mtsdram(DDR0_24, 0x01010001); + + mtsdram(DDR0_26, 0x2D93028A); + mtsdram(DDR0_27, 0x0784682B); + + mtsdram(DDR0_28, 0x00000080); + mtsdram(DDR0_31, 0x00000000); + mtsdram(DDR0_42, 0x01000008); + + mtsdram(DDR0_43, 0x050A0200); + mtsdram(DDR0_44, 0x00000005); + mtsdram(DDR0_02, 0x00000001); /* Activate the denali core */ +#endif wait_for_dlllock(); diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index c6f67fe..1d87c73 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -327,12 +327,24 @@ #define CFG_EBC_CFG 0xb8400000 /*----------------------------------------------------------------------- + * Graphics (Fujitsu Lime) + *----------------------------------------------------------------------*/ +/* SDRAM Clock frequency adjustment register */ +#define CFG_LIME_SDRAM_CLOCK 0xC1FC0000 +/* Lime Clock frequency is to set 133MHz */ +#define CFG_LIME_CLOCK_133MHZ 0x10000 + +/* SDRAM Parameter register */ +#define CFG_LIME_MMR 0xC1FCFFFC +/* SDRAM parameter value */ +#define CFG_LIME_MMR_VALUE 0x414FB7F2 + +/*----------------------------------------------------------------------- * GPIO Setup *----------------------------------------------------------------------*/ #define CFG_GPIO_PHY1_RST 12 #define CFG_GPIO_FLASH_WP 14 #define CFG_GPIO_PHY0_RST 22 -#define CFG_GPIO_HUB_RST 50 #define CFG_GPIO_WATCHDOG 58 #define CFG_GPIO_LIME_S 59 #define CFG_GPIO_LIME_RST 60 @@ -396,7 +408,7 @@ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \ {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \ -{GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ +{GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \ {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO53 Unselect via TraceSelect Bit */ \ |