diff options
| -rw-r--r-- | Makefile | 1 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabresd/flash_header.S | 133 | ||||
| -rw-r--r-- | board/freescale/mx6q_sabresd/mx6q_sabresd.c | 190 | ||||
| -rw-r--r-- | drivers/net/mxc_fec.c | 6 | ||||
| -rw-r--r-- | include/configs/mx6dl_sabresd.h | 323 |
5 files changed, 627 insertions, 26 deletions
@@ -3321,6 +3321,7 @@ mx6q_arm2_iram_config : unconfig } @$(MKCONFIG) $(@:_config=) arm arm_cortexa8 mx6q_arm2 freescale mx6 +mx6dl_sabresd_config \ mx6q_sabresd_config \ mx6q_sabresd_android_config \ mx6q_sabresd_mfg_config \ diff --git a/board/freescale/mx6q_sabresd/flash_header.S b/board/freescale/mx6q_sabresd/flash_header.S index acdb500..8be2198 100644 --- a/board/freescale/mx6q_sabresd/flash_header.S +++ b/board/freescale/mx6q_sabresd/flash_header.S @@ -53,6 +53,138 @@ boot_data: .word TEXT_BASE image_len: .word _end_of_copy - TEXT_BASE + CONFIG_FLASH_HEADER_OFFSET plugin: .word 0x0 +#if defined CONFIG_MX6DL_DDR3 +dcd_hdr: .word 0x40F802D2 /* Tag=0xD2, Len=94*8 + 4 + 4, Ver=0x40 */ +write_dcd_cmd: .word 0x04F402CC /* Tag=0xCC, Len=94*8 + 4, Param=0x04 */ + +# IOMUXC_BASE_ADDR = 0x20e0000 +# DDR IO TYPE +MXC_DCD_ITEM(1, IOMUXC_BASE_ADDR + 0x798, 0x000c0000) +MXC_DCD_ITEM(2, IOMUXC_BASE_ADDR + 0x758, 0x00000000) +# Clock +MXC_DCD_ITEM(3, IOMUXC_BASE_ADDR + 0x588, 0x00000030) +MXC_DCD_ITEM(4, IOMUXC_BASE_ADDR + 0x594, 0x00000030) +# Address +MXC_DCD_ITEM(5, IOMUXC_BASE_ADDR + 0x56c, 0x00000030) +MXC_DCD_ITEM(6, IOMUXC_BASE_ADDR + 0x578, 0x00000030) +MXC_DCD_ITEM(7, IOMUXC_BASE_ADDR + 0x74c, 0x00000030) +# Control +MXC_DCD_ITEM(8, IOMUXC_BASE_ADDR + 0x57c, 0x00000030) +MXC_DCD_ITEM(9, IOMUXC_BASE_ADDR + 0x590, 0x00003000) +MXC_DCD_ITEM(10, IOMUXC_BASE_ADDR + 0x598, 0x00003000) +MXC_DCD_ITEM(11, IOMUXC_BASE_ADDR + 0x58c, 0x00000000) +MXC_DCD_ITEM(12, IOMUXC_BASE_ADDR + 0x59c, 0x00003030) +MXC_DCD_ITEM(13, IOMUXC_BASE_ADDR + 0x5a0, 0x00003030) +MXC_DCD_ITEM(14, IOMUXC_BASE_ADDR + 0x78c, 0x00000030) +# Data Strobe +MXC_DCD_ITEM(15, IOMUXC_BASE_ADDR + 0x750, 0x00020000) +MXC_DCD_ITEM(16, IOMUXC_BASE_ADDR + 0x5a8, 0x00000030) +MXC_DCD_ITEM(17, IOMUXC_BASE_ADDR + 0x5b0, 0x00000030) +MXC_DCD_ITEM(18, IOMUXC_BASE_ADDR + 0x524, 0x00000030) +MXC_DCD_ITEM(19, IOMUXC_BASE_ADDR + 0x51c, 0x00000030) +MXC_DCD_ITEM(20, IOMUXC_BASE_ADDR + 0x518, 0x00000030) +MXC_DCD_ITEM(21, IOMUXC_BASE_ADDR + 0x50c, 0x00000030) +MXC_DCD_ITEM(22, IOMUXC_BASE_ADDR + 0x5b8, 0x00000030) +MXC_DCD_ITEM(23, IOMUXC_BASE_ADDR + 0x5c0, 0x00000030) +# DATA +MXC_DCD_ITEM(24, IOMUXC_BASE_ADDR + 0x774, 0x00020000) +MXC_DCD_ITEM(25, IOMUXC_BASE_ADDR + 0x784, 0x00000030) +MXC_DCD_ITEM(26, IOMUXC_BASE_ADDR + 0x788, 0x00000030) +MXC_DCD_ITEM(27, IOMUXC_BASE_ADDR + 0x794, 0x00000030) +MXC_DCD_ITEM(28, IOMUXC_BASE_ADDR + 0x79c, 0x00000030) +MXC_DCD_ITEM(29, IOMUXC_BASE_ADDR + 0x7a0, 0x00000030) +MXC_DCD_ITEM(30, IOMUXC_BASE_ADDR + 0x7a4, 0x00000030) +MXC_DCD_ITEM(31, IOMUXC_BASE_ADDR + 0x7a8, 0x00000030) +MXC_DCD_ITEM(32, IOMUXC_BASE_ADDR + 0x748, 0x00000030) +MXC_DCD_ITEM(33, IOMUXC_BASE_ADDR + 0x5ac, 0x00000030) +MXC_DCD_ITEM(34, IOMUXC_BASE_ADDR + 0x5b4, 0x00000030) +MXC_DCD_ITEM(35, IOMUXC_BASE_ADDR + 0x528, 0x00000030) +MXC_DCD_ITEM(36, IOMUXC_BASE_ADDR + 0x520, 0x00000030) +MXC_DCD_ITEM(37, IOMUXC_BASE_ADDR + 0x514, 0x00000030) +MXC_DCD_ITEM(38, IOMUXC_BASE_ADDR + 0x510, 0x00000030) +MXC_DCD_ITEM(39, IOMUXC_BASE_ADDR + 0x5bc, 0x00000030) +MXC_DCD_ITEM(40, IOMUXC_BASE_ADDR + 0x5c4, 0x00000030) + +# MMDC_P0_BASE_ADDR = 0x021b0000 +# MMDC_P1_BASE_ADDR = 0x021b4000 +# Calibrations +# ZQ +MXC_DCD_ITEM(41, MMDC_P0_BASE_ADDR + 0x800, 0xa1390003) +MXC_DCD_ITEM(42, MMDC_P1_BASE_ADDR + 0x800, 0xa1390003) +# write leveling +MXC_DCD_ITEM(43, MMDC_P0_BASE_ADDR + 0x80c, 0x001F001F) +MXC_DCD_ITEM(44, MMDC_P0_BASE_ADDR + 0x810, 0x001F001F) +MXC_DCD_ITEM(45, MMDC_P1_BASE_ADDR + 0x80c, 0x00370037) +MXC_DCD_ITEM(46, MMDC_P1_BASE_ADDR + 0x810, 0x00370037) +# DQS gating, read delay, write delay calibration values +# based on calibration compare of 0x00ffff00 +MXC_DCD_ITEM(47, MMDC_P0_BASE_ADDR + 0x83c, 0x422f0220) +MXC_DCD_ITEM(48, MMDC_P0_BASE_ADDR + 0x840, 0x021f0219) +MXC_DCD_ITEM(49, MMDC_P1_BASE_ADDR + 0x83C, 0x422f0220) +MXC_DCD_ITEM(50, MMDC_P1_BASE_ADDR + 0x840, 0x022d022f) +MXC_DCD_ITEM(51, MMDC_P0_BASE_ADDR + 0x848, 0x47494b49) +MXC_DCD_ITEM(52, MMDC_P1_BASE_ADDR + 0x848, 0x48484c47) +MXC_DCD_ITEM(53, MMDC_P0_BASE_ADDR + 0x850, 0x39382b2f) +MXC_DCD_ITEM(54, MMDC_P1_BASE_ADDR + 0x850, 0x2f35312c) +# read data bit delay +MXC_DCD_ITEM(55, MMDC_P0_BASE_ADDR + 0x81c, 0x33333333) +MXC_DCD_ITEM(56, MMDC_P0_BASE_ADDR + 0x820, 0x33333333) +MXC_DCD_ITEM(57, MMDC_P0_BASE_ADDR + 0x824, 0x33333333) +MXC_DCD_ITEM(58, MMDC_P0_BASE_ADDR + 0x828, 0x33333333) +MXC_DCD_ITEM(59, MMDC_P1_BASE_ADDR + 0x81c, 0x33333333) +MXC_DCD_ITEM(60, MMDC_P1_BASE_ADDR + 0x820, 0x33333333) +MXC_DCD_ITEM(61, MMDC_P1_BASE_ADDR + 0x824, 0x33333333) +MXC_DCD_ITEM(62, MMDC_P1_BASE_ADDR + 0x828, 0x33333333) +# Complete calibration by forced measurment +MXC_DCD_ITEM(63, MMDC_P0_BASE_ADDR + 0x8b8, 0x00000800) +MXC_DCD_ITEM(64, MMDC_P1_BASE_ADDR + 0x8b8, 0x00000800) +# MMDC init: +# in DDR3, 64-bit mode, only MMDC0 is initiated: +MXC_DCD_ITEM(65, MMDC_P0_BASE_ADDR + 0x004, 0x0002002d) +MXC_DCD_ITEM(66, MMDC_P0_BASE_ADDR + 0x008, 0x00333030) + +MXC_DCD_ITEM(67, MMDC_P0_BASE_ADDR + 0x00c, 0x40445323) +MXC_DCD_ITEM(68, MMDC_P0_BASE_ADDR + 0x010, 0xb66e8c63) + +MXC_DCD_ITEM(69, MMDC_P0_BASE_ADDR + 0x014, 0x01ff00db) +MXC_DCD_ITEM(70, MMDC_P0_BASE_ADDR + 0x018, 0x00081740) +MXC_DCD_ITEM(71, MMDC_P0_BASE_ADDR + 0x01c, 0x00008000) +MXC_DCD_ITEM(72, MMDC_P0_BASE_ADDR + 0x02c, 0x000026d2) +MXC_DCD_ITEM(73, MMDC_P0_BASE_ADDR + 0x030, 0x00440e21) +MXC_DCD_ITEM(74, MMDC_P0_BASE_ADDR + 0x040, 0x00000027) +MXC_DCD_ITEM(75, MMDC_P0_BASE_ADDR + 0x000, 0xc31a0000) + +# Initialize 2GB DDR3 - Micron MT41J128M +# MR2 +MXC_DCD_ITEM(76, MMDC_P0_BASE_ADDR + 0x01c, 0x04008032) +MXC_DCD_ITEM(77, MMDC_P0_BASE_ADDR + 0x01c, 0x0400803a) +# MR3 +MXC_DCD_ITEM(78, MMDC_P0_BASE_ADDR + 0x01c, 0x00008033) +MXC_DCD_ITEM(79, MMDC_P0_BASE_ADDR + 0x01c, 0x0000803b) +# MR1 +MXC_DCD_ITEM(80, MMDC_P0_BASE_ADDR + 0x01c, 0x00428031) +MXC_DCD_ITEM(81, MMDC_P0_BASE_ADDR + 0x01c, 0x00428039) +# MR0 +MXC_DCD_ITEM(82, MMDC_P0_BASE_ADDR + 0x01c, 0x07208030) +MXC_DCD_ITEM(83, MMDC_P0_BASE_ADDR + 0x01c, 0x07208038) +# ZQ calibration +MXC_DCD_ITEM(84, MMDC_P0_BASE_ADDR + 0x01c, 0x04008040) +MXC_DCD_ITEM(85, MMDC_P0_BASE_ADDR + 0x01c, 0x04008048) +# final DDR setup +MXC_DCD_ITEM(86, MMDC_P0_BASE_ADDR + 0x020, 0x00005800) +MXC_DCD_ITEM(87, MMDC_P0_BASE_ADDR + 0x818, 0x00022227) +MXC_DCD_ITEM(88, MMDC_P1_BASE_ADDR + 0x818, 0x00022227) +MXC_DCD_ITEM(89, MMDC_P0_BASE_ADDR + 0x004, 0x0002556d) +MXC_DCD_ITEM(90, MMDC_P1_BASE_ADDR + 0x004, 0x00011006) +MXC_DCD_ITEM(91, MMDC_P0_BASE_ADDR + 0x01c, 0x00000000) + +/* enable AXI cache for VDOA/VPU/IPU */ +MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) +/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ +MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) +MXC_DCD_ITEM(94, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) + +#else dcd_hdr: .word 0x40F002D2 /* Tag=0xD2, Len=93*8 + 4 + 4, Ver=0x40 */ write_dcd_cmd: .word 0x04EC02CC /* Tag=0xCC, Len=93*8 + 4, Param=0x04 */ @@ -175,5 +307,6 @@ MXC_DCD_ITEM(91, IOMUXC_BASE_ADDR + 0x010, 0xf00000ff) /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */ MXC_DCD_ITEM(92, IOMUXC_BASE_ADDR + 0x018, 0x007f007f) MXC_DCD_ITEM(93, IOMUXC_BASE_ADDR + 0x01c, 0x007f007f) +#endif #endif diff --git a/board/freescale/mx6q_sabresd/mx6q_sabresd.c b/board/freescale/mx6q_sabresd/mx6q_sabresd.c index 08957d7..7266043 100644 --- a/board/freescale/mx6q_sabresd/mx6q_sabresd.c +++ b/board/freescale/mx6q_sabresd/mx6q_sabresd.c @@ -24,6 +24,7 @@ #include <asm/io.h> #include <asm/arch/mx6.h> #include <asm/arch/mx6_pins.h> +#include <asm/arch/mx6dl_pins.h> #include <asm/arch/iomux-v3.h> #include <asm/errno.h> #ifdef CONFIG_MXC_FEC @@ -59,6 +60,10 @@ #include <asm/clock.h> #endif +#ifdef CONFIG_CMD_IMXOTP +#include <imx_otp.h> +#endif + #ifdef CONFIG_ANDROID_RECOVERY #include "../common/recovery.h" #include <part.h> @@ -68,10 +73,8 @@ #include <ubi_uboot.h> #include <jffs2/load_kernel.h> #endif - DECLARE_GLOBAL_DATA_PTR; -static u32 system_rev; static enum boot_device boot_dev; #ifdef CONFIG_VIDEO_MX5 @@ -150,10 +153,7 @@ enum boot_device get_boot_device(void) u32 get_board_rev(void) { - - system_rev = 0x63000; - - return system_rev; + return fsl_system_rev; } #ifdef CONFIG_ARCH_MMU @@ -284,11 +284,19 @@ int dram_init(void) static void setup_uart(void) { +#if defined CONFIG_MX6Q /* UART1 TXD */ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT10__UART1_TXD); /* UART1 RXD */ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT11__UART1_RXD); +#elif defined CONFIG_MX6DL + /* UART1 TXD */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT10__UART1_TXD); + + /* UART1 RXD */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT11__UART1_RXD); +#endif } #ifdef CONFIG_VIDEO_MX5 @@ -299,11 +307,19 @@ static void setup_i2c(unsigned int module_base) switch (module_base) { case I2C1_BASE_ADDR: +#if defined CONFIG_MX6Q /* i2c1 SDA */ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT8__I2C1_SDA); /* i2c1 SCL */ mxc_iomux_v3_setup_pad(MX6Q_PAD_CSI0_DAT9__I2C1_SCL); +#elif defined CONFIG_MX6DL + /* i2c1 SDA */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT8__I2C1_SDA); + + /* i2c1 SCL */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_CSI0_DAT9__I2C1_SCL); +#endif /* Enable i2c clock */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); @@ -312,11 +328,19 @@ static void setup_i2c(unsigned int module_base) break; case I2C2_BASE_ADDR: +#if defined CONFIG_MX6Q /* i2c2 SDA */ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW3__I2C2_SDA); /* i2c2 SCL */ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL3__I2C2_SCL); +#elif defined CONFIG_MX6DL + /* i2c2 SDA */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW3__I2C2_SDA); + + /* i2c2 SCL */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL3__I2C2_SCL); +#endif /* Enable i2c clock */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); @@ -325,11 +349,22 @@ static void setup_i2c(unsigned int module_base) break; case I2C3_BASE_ADDR: +#if defined CONFIG_MX6Q /* GPIO_5 for I2C3_SCL */ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_3__I2C3_SCL); /* GPIO_16 for I2C3_SDA */ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_16__I2C3_SDA); +#elif defined CONFIG_MX6DL + /* GPIO_5 for I2C3_SCL */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_3__I2C3_SCL); + + /* GPIO_16 for I2C3_SDA */ + if (mx6_board_is_reva()) + mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_16__I2C3_SDA); + else /* other board ID define to the same */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_6__I2C3_SDA); +#endif /* Enable i2c clock */ reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR2); @@ -348,6 +383,7 @@ void setup_lvds_poweron(void) uchar value; i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); +#if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) i2c_read(0x1f, 3, 1, &value, 1); value &= ~0x2; i2c_write(0x1f, 3, 1, &value, 1); @@ -355,6 +391,7 @@ void setup_lvds_poweron(void) i2c_read(0x1f, 1, 1, &value, 1); value |= 0x2; i2c_write(0x1f, 1, 1, &value, 1); +#endif } #endif #endif @@ -399,6 +436,7 @@ void spi_io_init(struct imx_spi_dev_t *dev) reg |= 0x3; writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR1); +#if defined CONFIG_MX6Q /* SCLK */ mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_COL0__ECSPI1_SCLK); @@ -409,6 +447,18 @@ void spi_io_init(struct imx_spi_dev_t *dev) mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW0__ECSPI1_MOSI); mxc_iomux_v3_setup_pad(MX6Q_PAD_KEY_ROW1__ECSPI1_SS0); +#elif defined CONFIG_MX6DL + /* SCLK */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL0__ECSPI1_SCLK); + + /* MISO */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_COL1__ECSPI1_MISO); + + /* MOSI */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW0__ECSPI1_MOSI); + + mxc_iomux_v3_setup_pad(MX6DL_PAD_KEY_ROW1__ECSPI1_SS0); +#endif break; case ECSPI2_BASE_ADDR: case ECSPI3_BASE_ADDR: @@ -509,7 +559,8 @@ int get_mmc_env_devno(void) } #endif -iomux_v3_cfg_t mx6q_usdhc1_pads[] = { +#if defined CONFIG_MX6Q +iomux_v3_cfg_t usdhc1_pads[] = { MX6Q_PAD_SD1_CLK__USDHC1_CLK, MX6Q_PAD_SD1_CMD__USDHC1_CMD, MX6Q_PAD_SD1_DAT0__USDHC1_DAT0, @@ -518,7 +569,7 @@ iomux_v3_cfg_t mx6q_usdhc1_pads[] = { MX6Q_PAD_SD1_DAT3__USDHC1_DAT3, }; -iomux_v3_cfg_t mx6q_usdhc2_pads[] = { +iomux_v3_cfg_t usdhc2_pads[] = { MX6Q_PAD_SD2_CLK__USDHC2_CLK, MX6Q_PAD_SD2_CMD__USDHC2_CMD, MX6Q_PAD_SD2_DAT0__USDHC2_DAT0, @@ -527,7 +578,7 @@ iomux_v3_cfg_t mx6q_usdhc2_pads[] = { MX6Q_PAD_SD2_DAT3__USDHC2_DAT3, }; -iomux_v3_cfg_t mx6q_usdhc3_pads[] = { +iomux_v3_cfg_t usdhc3_pads[] = { MX6Q_PAD_SD3_CLK__USDHC3_CLK, MX6Q_PAD_SD3_CMD__USDHC3_CMD, MX6Q_PAD_SD3_DAT0__USDHC3_DAT0, @@ -540,7 +591,7 @@ iomux_v3_cfg_t mx6q_usdhc3_pads[] = { MX6Q_PAD_SD3_DAT7__USDHC3_DAT7, }; -iomux_v3_cfg_t mx6q_usdhc4_pads[] = { +iomux_v3_cfg_t usdhc4_pads[] = { MX6Q_PAD_SD4_CLK__USDHC4_CLK, MX6Q_PAD_SD4_CMD__USDHC4_CMD, MX6Q_PAD_SD4_DAT0__USDHC4_DAT0, @@ -552,6 +603,51 @@ iomux_v3_cfg_t mx6q_usdhc4_pads[] = { MX6Q_PAD_SD4_DAT6__USDHC4_DAT6, MX6Q_PAD_SD4_DAT7__USDHC4_DAT7, }; +#elif defined CONFIG_MX6DL +iomux_v3_cfg_t usdhc1_pads[] = { + MX6DL_PAD_SD1_CLK__USDHC1_CLK, + MX6DL_PAD_SD1_CMD__USDHC1_CMD, + MX6DL_PAD_SD1_DAT0__USDHC1_DAT0, + MX6DL_PAD_SD1_DAT1__USDHC1_DAT1, + MX6DL_PAD_SD1_DAT2__USDHC1_DAT2, + MX6DL_PAD_SD1_DAT3__USDHC1_DAT3, +}; + +iomux_v3_cfg_t usdhc2_pads[] = { + MX6DL_PAD_SD2_CLK__USDHC2_CLK, + MX6DL_PAD_SD2_CMD__USDHC2_CMD, + MX6DL_PAD_SD2_DAT0__USDHC2_DAT0, + MX6DL_PAD_SD2_DAT1__USDHC2_DAT1, + MX6DL_PAD_SD2_DAT2__USDHC2_DAT2, + MX6DL_PAD_SD2_DAT3__USDHC2_DAT3, +}; + +iomux_v3_cfg_t usdhc3_pads[] = { + MX6DL_PAD_SD3_CLK__USDHC3_CLK, + MX6DL_PAD_SD3_CMD__USDHC3_CMD, + MX6DL_PAD_SD3_DAT0__USDHC3_DAT0, + MX6DL_PAD_SD3_DAT1__USDHC3_DAT1, + MX6DL_PAD_SD3_DAT2__USDHC3_DAT2, + MX6DL_PAD_SD3_DAT3__USDHC3_DAT3, + MX6DL_PAD_SD3_DAT4__USDHC3_DAT4, + MX6DL_PAD_SD3_DAT5__USDHC3_DAT5, + MX6DL_PAD_SD3_DAT6__USDHC3_DAT6, + MX6DL_PAD_SD3_DAT7__USDHC3_DAT7, +}; + +iomux_v3_cfg_t usdhc4_pads[] = { + MX6DL_PAD_SD4_CLK__USDHC4_CLK, + MX6DL_PAD_SD4_CMD__USDHC4_CMD, + MX6DL_PAD_SD4_DAT0__USDHC4_DAT0, + MX6DL_PAD_SD4_DAT1__USDHC4_DAT1, + MX6DL_PAD_SD4_DAT2__USDHC4_DAT2, + MX6DL_PAD_SD4_DAT3__USDHC4_DAT3, + MX6DL_PAD_SD4_DAT4__USDHC4_DAT4, + MX6DL_PAD_SD4_DAT5__USDHC4_DAT5, + MX6DL_PAD_SD4_DAT6__USDHC4_DAT6, + MX6DL_PAD_SD4_DAT7__USDHC4_DAT7, +}; +#endif int usdhc_gpio_init(bd_t *bis) { @@ -562,24 +658,24 @@ int usdhc_gpio_init(bd_t *bis) ++index) { switch (index) { case 0: - mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc1_pads, - sizeof(mx6q_usdhc1_pads) / - sizeof(mx6q_usdhc1_pads[0])); + mxc_iomux_v3_setup_multiple_pads(usdhc1_pads, + sizeof(usdhc1_pads) / + sizeof(usdhc1_pads[0])); break; case 1: - mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc2_pads, - sizeof(mx6q_usdhc2_pads) / - sizeof(mx6q_usdhc2_pads[0])); + mxc_iomux_v3_setup_multiple_pads(usdhc2_pads, + sizeof(usdhc2_pads) / + sizeof(usdhc2_pads[0])); break; case 2: - mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc3_pads, - sizeof(mx6q_usdhc3_pads) / - sizeof(mx6q_usdhc3_pads[0])); + mxc_iomux_v3_setup_multiple_pads(usdhc3_pads, + sizeof(usdhc3_pads) / + sizeof(usdhc3_pads[0])); break; case 3: - mxc_iomux_v3_setup_multiple_pads(mx6q_usdhc4_pads, - sizeof(mx6q_usdhc4_pads) / - sizeof(mx6q_usdhc4_pads[0])); + mxc_iomux_v3_setup_multiple_pads(usdhc4_pads, + sizeof(usdhc4_pads) / + sizeof(usdhc4_pads[0])); break; default: printf("Warning: you configured more USDHC controllers" @@ -633,8 +729,13 @@ void lcd_enable(void) */ g_ipu_hw_rev = IPUV3_HW_REV_IPUV3H; +#if defined CONFIG_MX6Q /* set GPIO_9 to high so that backlight control could be high */ mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_9__GPIO_1_9); +#elif defined CONFIG_MX6DL + mxc_iomux_v3_setup_pad(MX6DL_PAD_SD1_DAT3__PWM1_PWMO); +#endif + reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR); reg |= (1 << 9); writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR); @@ -718,6 +819,7 @@ int board_init(void) { mxc_iomux_v3_init((void *)IOMUXC_BASE_ADDR); setup_boot_device(); + fsl_set_system_rev(); /* board id for linux */ gd->bd->bi_arch_number = MACH_TYPE_MX6Q_SABRESD; @@ -865,7 +967,11 @@ int check_recovery_cmd_file(void) /* Check Recovery Combo Button press or not. */ +#if defined CONFIG_MX6Q mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_5__GPIO_1_5); +#elif defined CONFIG_MX6DL + mxc_iomux_v3_setup_pad(MX6DL_PAD_GPIO_5__GPIO_1_5); +#endif reg = readl(GPIO1_BASE_ADDR + GPIO_GDIR); reg &= ~(1<<5); writel(reg, GPIO1_BASE_ADDR + GPIO_GDIR); @@ -928,6 +1034,7 @@ int mx6_rgmii_rework(char *devname, int phy_addr) return 0; } +#if defined CONFIG_MX6Q iomux_v3_cfg_t enet_pads[] = { MX6Q_PAD_ENET_MDIO__ENET_MDIO, MX6Q_PAD_ENET_MDC__ENET_MDC, @@ -947,18 +1054,44 @@ iomux_v3_cfg_t enet_pads[] = { MX6Q_PAD_GPIO_0__CCM_CLKO, MX6Q_PAD_GPIO_3__CCM_CLKO2, }; +#elif defined CONFIG_MX6DL +iomux_v3_cfg_t enet_pads[] = { + MX6DL_PAD_ENET_MDIO__ENET_MDIO, + MX6DL_PAD_ENET_MDC__ENET_MDC, + MX6DL_PAD_RGMII_TXC__ENET_RGMII_TXC, + MX6DL_PAD_RGMII_TD0__ENET_RGMII_TD0, + MX6DL_PAD_RGMII_TD1__ENET_RGMII_TD1, + MX6DL_PAD_RGMII_TD2__ENET_RGMII_TD2, + MX6DL_PAD_RGMII_TD3__ENET_RGMII_TD3, + MX6DL_PAD_RGMII_TX_CTL__ENET_RGMII_TX_CTL, + MX6DL_PAD_ENET_REF_CLK__ENET_TX_CLK, + MX6DL_PAD_RGMII_RXC__ENET_RGMII_RXC, + MX6DL_PAD_RGMII_RD0__ENET_RGMII_RD0, + MX6DL_PAD_RGMII_RD1__ENET_RGMII_RD1, + MX6DL_PAD_RGMII_RD2__ENET_RGMII_RD2, + MX6DL_PAD_RGMII_RD3__ENET_RGMII_RD3, + MX6DL_PAD_RGMII_RX_CTL__ENET_RGMII_RX_CTL, + MX6DL_PAD_GPIO_0__CCM_CLKO, +}; +#endif void enet_board_init(void) { unsigned int reg; +#if defined CONFIG_MX6Q iomux_v3_cfg_t enet_reset = (_MX6Q_PAD_ENET_CRS_DV__GPIO_1_25 & ~MUX_PAD_CTRL_MASK) | MUX_PAD_CTRL(0x88); +#elif defined CONFIG_MX6DL + iomux_v3_cfg_t enet_reset = + (MX6DL_PAD_ENET_CRS_DV__GPIO_1_25 & + ~MUX_PAD_CTRL_MASK) | + MUX_PAD_CTRL(0x88); +#endif mxc_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - mxc_iomux_v3_setup_pad(enet_reset); /* phy reset: gpio1-25 */ @@ -980,7 +1113,10 @@ void enet_board_init(void) int checkboard(void) { - printf("Board: MX6Q-SABRESD:[ "); + printf("Board: %s-SABRESD: %s Board: 0x%x [", + (mx6_chip_is_dq() ? "i.MX6Q" : "i.MX6DL/Solo"), + (mx6_board_is_revb() ? "RevB" : "RevA"), + fsl_system_rev); switch (__REG(SRC_BASE_ADDR + 0x8)) { case 0x0001: @@ -1041,9 +1177,15 @@ void udc_pins_setting(void) { #define GPIO_3_22_BIT_MASK (1<<22) u32 reg; +#if defined CONFIG_MX6Q mxc_iomux_v3_setup_pad(MX6Q_PAD_GPIO_1__USBOTG_ID); /* USB_OTG_PWR */ mxc_iomux_v3_setup_pad(MX6Q_PAD_EIM_D22__GPIO_3_22); +#elif defined CONFIG_MX6DL + mxc_iomux_v3_setup_pad(MX6DL_PAD_ENET_RX_ER__ANATOP_USBOTG_ID); + /* USB_OTG_PWR */ + mxc_iomux_v3_setup_pad(MX6DL_PAD_EIM_D22__GPIO_3_22); +#endif reg = readl(GPIO3_BASE_ADDR + GPIO_GDIR); /* set gpio_3_22 as output */ diff --git a/drivers/net/mxc_fec.c b/drivers/net/mxc_fec.c index 636b606..60a0f0a 100644 --- a/drivers/net/mxc_fec.c +++ b/drivers/net/mxc_fec.c @@ -79,7 +79,8 @@ #if defined(CONFIG_MX6Q) || defined(CONFIG_MX6DL) extern int mx6_rgmii_rework(char *devname, int phy_addr); #endif -#if defined(CONFIG_MX6Q_ARM2) || defined(CONFIG_MX6Q_SABRESD) +#if defined(CONFIG_MX6Q_ARM2) || defined(CONFIG_MX6Q_SABRESD) || \ + defined(CONFIG_MX6DL_SABRESD) #define PHY_MIPSCR_LINK_UP (0x1 << 10) #define PHY_MIPSCR_SPEED_MASK (0x3 << 14) #define PHY_MIPSCR_1000M (0x2 << 14) @@ -368,7 +369,8 @@ static void setFecDuplexSpeed(volatile fec_t *fecp, unsigned char addr, printf("FEC: Link is down %x\n", val); } /* for AR8031 PHY */ -#if defined(CONFIG_MX6Q_ARM2) || defined(CONFIG_MX6Q_SABRESD) +#if defined(CONFIG_MX6Q_ARM2) || defined(CONFIG_MX6Q_SABRESD) || \ + defined(CONFIG_MX6DL_SABRESD) ret = __fec_mii_read(fecp, addr, PHY_MIPSCR, &val); if (ret) dup_spd = _100BASET | (FULL << 16); diff --git a/include/configs/mx6dl_sabresd.h b/include/configs/mx6dl_sabresd.h new file mode 100644 index 0000000..5580186 --- /dev/null +++ b/include/configs/mx6dl_sabresd.h @@ -0,0 +1,323 @@ +/* + * Copyright (C) 2010-2012 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX6DL SabreSD Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx6.h> + + /* High Level Configuration Options */ +#define CONFIG_ARMV7 /* This is armv7 Cortex-A9 CPU core */ +#define CONFIG_MXC +#define CONFIG_MX6DL +#define CONFIG_MX6DL_DDR3 +#define CONFIG_MX6DL_SABRESD +#define CONFIG_DDR_64BIT /* for DDR 64bit */ +#define CONFIG_FLASH_HEADER +#define CONFIG_FLASH_HEADER_OFFSET 0x400 +#define CONFIG_MX6_CLK32 32768 + +#define CONFIG_SKIP_RELOCATE_UBOOT + +#define CONFIG_ARCH_CPU_INIT +#undef CONFIG_ARCH_MMU /* disable MMU first */ +#define CONFIG_L2_OFF /* disable L2 cache first*/ + +#define CONFIG_MX6_HCLK_FREQ 24000000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_64BIT_VSPRINTF + +#define BOARD_LATE_INIT + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (2 * 1024 * 1024) +/* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_SIZE 128 + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_UART_BASE_ADDR UART1_BASE_ADDR + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_CMD_NET +#define CONFIG_NET_RETRY_COUNT 100 +#define CONFIG_NET_MULTI 1 +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_DNS + +#define CONFIG_CMD_SPI +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMXOTP + +/* Enable below configure when supporting nand */ +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_ENV +#define CONFIG_CMD_REGUL + +#define CONFIG_CMD_CLOCK +#define CONFIG_REF_CLK_FREQ CONFIG_MX6_HCLK_FREQ + +#undef CONFIG_CMD_IMLS + +#define CONFIG_CMD_IMX_DOWNLOAD_MODE + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_PRIME "FEC0" + +#define CONFIG_LOADADDR 0x10800000 /* loadaddr env var */ +#define CONFIG_RD_LOADADDR (CONFIG_LOADADDR + 0x300000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethprime=FEC0\0" \ + "uboot=u-boot.bin\0" \ + "kernel=uImage\0" \ + "nfsroot=/opt/eldk/arm\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0"\ + "enable_wait_mode=off\0" \ + "bootargs_nfs=setenv bootargs ${bootargs} root=/dev/nfs "\ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0"\ + "bootcmd_net=run bootargs_base bootargs_nfs; " \ + "tftpboot ${loadaddr} ${kernel}; bootm\0" \ + "bootargs_mmc=setenv bootargs ${bootargs} ip=dhcp " \ + "root=/dev/mmcblk0p1 rootwait\0" \ + "bootcmd_mmc=run bootargs_base bootargs_mmc; " \ + "mmc dev 3; " \ + "mmc read ${loadaddr} 0x800 0x2000; bootm\0" \ + "bootcmd=run bootcmd_net\0" \ + + +#define CONFIG_ARP_TIMEOUT 200UL + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "MX6SDL SABRESD U-Boot > " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x10000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x10010000 + +#undef CONFIG_SYS_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 + +#define CONFIG_CMDLINE_EDITING + +#define CONFIG_FEC0_IOBASE ENET_BASE_ADDR +#define CONFIG_FEC0_PINMUX -1 +#define CONFIG_FEC0_MIIBASE -1 +#define CONFIG_GET_FEC_MAC_ADDR_FROM_IIM +#define CONFIG_MXC_FEC +#define CONFIG_FEC0_PHY_ADDR 1 +#define CONFIG_ETH_PRIME +#define CONFIG_RMII +#define CONFIG_CMD_MII +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PING +#define CONFIG_IPADDR 192.168.1.103 +#define CONFIG_SERVERIP 192.168.1.101 +#define CONFIG_NETMASK 255.255.255.0 + +/* + * OCOTP Configs + */ +#ifdef CONFIG_CMD_IMXOTP + #define CONFIG_IMX_OTP + #define IMX_OTP_BASE OCOTP_BASE_ADDR + #define IMX_OTP_ADDR_MAX 0x7F + #define IMX_OTP_DATA_ERROR_VAL 0xBADABADA +#endif + +/* + * I2C Configs + */ +#ifdef CONFIG_CMD_I2C + #define CONFIG_HARD_I2C 1 + #define CONFIG_I2C_MXC 1 + #define CONFIG_SYS_I2C_PORT I2C3_BASE_ADDR + #define CONFIG_SYS_I2C_SPEED 100000 + #define CONFIG_SYS_I2C_SLAVE 0x1f +#endif + +/* + * SPI Configs + */ +#ifdef CONFIG_CMD_SF + #define CONFIG_FSL_SF 1 + #define CONFIG_SPI_FLASH_IMX_M25PXX 1 + #define CONFIG_SPI_FLASH_CS 1 + #define CONFIG_IMX_ECSPI + #define IMX_CSPI_VER_2_3 1 + #define MAX_SPI_BYTES (64 * 4) +#endif + +/* Regulator Configs */ +#ifdef CONFIG_CMD_REGUL + #define CONFIG_ANATOP_REGULATOR + #define CONFIG_CORE_REGULATOR_NAME "vdd1p1" + #define CONFIG_PERIPH_REGULATOR_NAME "vdd1p1" +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC + #define CONFIG_MMC + #define CONFIG_GENERIC_MMC + #define CONFIG_IMX_MMC + #define CONFIG_SYS_FSL_USDHC_NUM 4 + #define CONFIG_SYS_FSL_ESDHC_ADDR 0 + #define CONFIG_SYS_MMC_ENV_DEV 2 + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* detect whether SD1, 2, 3, or 4 is boot device */ + #define CONFIG_DYNAMIC_MMC_DEVNO + + /* SD3 and SD4 are 8 bit */ + #define CONFIG_MMC_8BIT_PORTS 0xC + /* Setup target delay in DDR mode for each SD port */ + #define CONFIG_GET_DDR_TARGET_DELAY +#endif + +/* + * GPMI Nand Configs + */ +/* #define CONFIG_CMD_NAND */ + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + /* NAND is the unique module invoke APBH-DMA */ + #define CONFIG_APBH_DMA + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_DDR_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (1u * 1024 * 1024 * 1024) +#define iomem_valid_addr(addr, size) \ + (addr >= PHYS_SDRAM_1 && addr <= (PHYS_SDRAM_1 + PHYS_SDRAM_1_SIZE)) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CONFIG_SYS_NO_FLASH + +/* Monitor at beginning of flash */ +#define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ + +#define CONFIG_ENV_SECT_SIZE (8 * 1024) +#define CONFIG_ENV_SIZE CONFIG_ENV_SECT_SIZE + +#if defined(CONFIG_FSL_ENV_IN_NAND) + #define CONFIG_ENV_IS_IN_NAND 1 + #define CONFIG_ENV_OFFSET 0x100000 +#elif defined(CONFIG_FSL_ENV_IN_MMC) + #define CONFIG_ENV_IS_IN_MMC 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#elif defined(CONFIG_FSL_ENV_IN_SF) + #define CONFIG_ENV_IS_IN_SPI_FLASH 1 + #define CONFIG_ENV_SPI_CS 1 + #define CONFIG_ENV_OFFSET (768 * 1024) +#else + #define CONFIG_ENV_IS_NOWHERE 1 +#endif + +#ifdef CONFIG_SPLASH_SCREEN + /* + * Framebuffer and LCD + */ + #define CONFIG_LCD + #define CONFIG_IPU_V3H + #define CONFIG_VIDEO_MX5 + #define CONFIG_IPU_CLKRATE 260000000 + #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE + #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE + #define CONFIG_SYS_CONSOLE_IS_IN_ENV + #define LCD_BPP LCD_COLOR16 + #define CONFIG_CMD_BMP + #define CONFIG_BMP_8BPP + #define CONFIG_FB_BASE (TEXT_BASE + 0x300000) + #define CONFIG_SPLASH_SCREEN_ALIGN + #define CONFIG_SYS_WHITE_ON_BLACK +#endif +#endif /* __CONFIG_H */ |