diff options
| -rw-r--r-- | board/freescale/mx6q_arm2/mx6q_arm2.c | 56 | ||||
| -rw-r--r-- | cpu/arm_cortexa8/mx6/generic.c | 4 | ||||
| -rw-r--r-- | include/asm-arm/arch-mx6/mx6.h | 5 | ||||
| -rw-r--r-- | include/configs/mx6q_arm2.h | 27 |
4 files changed, 91 insertions, 1 deletions
diff --git a/board/freescale/mx6q_arm2/mx6q_arm2.c b/board/freescale/mx6q_arm2/mx6q_arm2.c index b7853ac..d48601e 100644 --- a/board/freescale/mx6q_arm2/mx6q_arm2.c +++ b/board/freescale/mx6q_arm2/mx6q_arm2.c @@ -404,6 +404,59 @@ void spi_io_init(struct imx_spi_dev_t *dev) } #endif +#ifdef CONFIG_NAND_GPMI + +iomux_v3_cfg_t nfc_pads[] = { + MX6Q_PAD_NANDF_CLE__RAWNAND_CLE, + MX6Q_PAD_NANDF_ALE__RAWNAND_ALE, + MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN, + MX6Q_PAD_NANDF_RB0__RAWNAND_READY0, + MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N, + MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N, + MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N, + MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N, + MX6Q_PAD_SD4_CMD__RAWNAND_RDN, + MX6Q_PAD_SD4_CLK__RAWNAND_WRN, + MX6Q_PAD_NANDF_D0__RAWNAND_D0, + MX6Q_PAD_NANDF_D1__RAWNAND_D1, + MX6Q_PAD_NANDF_D2__RAWNAND_D2, + MX6Q_PAD_NANDF_D3__RAWNAND_D3, + MX6Q_PAD_NANDF_D4__RAWNAND_D4, + MX6Q_PAD_NANDF_D5__RAWNAND_D5, + MX6Q_PAD_NANDF_D6__RAWNAND_D6, + MX6Q_PAD_NANDF_D7__RAWNAND_D7, + MX6Q_PAD_SD4_DAT0__RAWNAND_DQS, +}; + +int setup_gpmi_nand(void) +{ + unsigned int reg; + + /* config gpmi nand iomux */ + mxc_iomux_v3_setup_multiple_pads(nfc_pads, + ARRAY_SIZE(nfc_pads)); + + + /* config gpmi and bch clock to 11Mhz*/ + reg = readl(CCM_BASE_ADDR + CLKCTL_CS2CDR); + reg &= 0xF800FFFF; + reg |= 0x01E40000; + writel(reg, CCM_BASE_ADDR + CLKCTL_CS2CDR); + + /* enable gpmi and bch clock gating */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR4); + reg |= 0xFF003000; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR4); + + /* enable apbh clock gating */ + reg = readl(CCM_BASE_ADDR + CLKCTL_CCGR0); + reg |= 0x0030; + writel(reg, CCM_BASE_ADDR + CLKCTL_CCGR0); + +} +#endif + + #define HW_OCOTP_MACn(n) (0x00000620 + (n) * 0x10) #ifdef CONFIG_MXC_FEC @@ -706,6 +759,9 @@ int board_init(void) #endif #endif +#ifdef CONFIG_NAND_GPMI + setup_gpmi_nand(); +#endif return 0; } diff --git a/cpu/arm_cortexa8/mx6/generic.c b/cpu/arm_cortexa8/mx6/generic.c index 11fac50..3ffc420 100644 --- a/cpu/arm_cortexa8/mx6/generic.c +++ b/cpu/arm_cortexa8/mx6/generic.c @@ -280,7 +280,7 @@ static u32 __get_nfc_clk(void) break; } - return clkroot / pred / podf; + return clkroot / (pred+1) / (podf+1); } static u32 __get_ddr_clk(void) @@ -390,6 +390,8 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_SATA_CLK: return __get_ahb_clk(); case MXC_NFC_CLK: + case MXC_GPMI_CLK: + case MXC_BCH_CLK: return __get_nfc_clk(); default: break; diff --git a/include/asm-arm/arch-mx6/mx6.h b/include/asm-arm/arch-mx6/mx6.h index 1a984de..ae52fa2 100644 --- a/include/asm-arm/arch-mx6/mx6.h +++ b/include/asm-arm/arch-mx6/mx6.h @@ -169,6 +169,9 @@ #define CSD1_DDR_BASE_ADDR MMDC1_ARB_BASE_ADDR #define CS0_BASE_ADDR WEIM_ARB_BASE_ADDR #define NAND_FLASH_BASE_ADDR APBH_DMA_ARB_BASE_ADDR +#define ABPHDMA_BASE_ADDR APBH_DMA_ARB_BASE_ADDR +#define GPMI_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x02000) +#define BCH_BASE_ADDR (APBH_DMA_ARB_BASE_ADDR + 0x04000) /* Defines for Blocks connected via AIPS (SkyBlue) */ #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR @@ -652,6 +655,8 @@ enum mxc_clock { MXC_ESDHC4_CLK, MXC_SATA_CLK, MXC_NFC_CLK, + MXC_GPMI_CLK, + MXC_BCH_CLK, }; enum mxc_peri_clocks { diff --git a/include/configs/mx6q_arm2.h b/include/configs/mx6q_arm2.h index c9bff96..e21bfad 100644 --- a/include/configs/mx6q_arm2.h +++ b/include/configs/mx6q_arm2.h @@ -237,6 +237,32 @@ #define CONFIG_LIBATA #endif +/* + * GPMI Nand Configs + */ +/* #define CONFIG_CMD_NAND */ + +#ifdef CONFIG_CMD_NAND + #define CONFIG_NAND_GPMI + #define CONFIG_GPMI_NFC_SWAP_BLOCK_MARK + #define CONFIG_GPMI_NFC_V2 + + #define CONFIG_GPMI_REG_BASE GPMI_BASE_ADDR + #define CONFIG_BCH_REG_BASE BCH_BASE_ADDR + + #define NAND_MAX_CHIPS 8 + #define CONFIG_SYS_NAND_BASE 0x40000000 + #define CONFIG_SYS_MAX_NAND_DEVICE 1 + + #define CONFIG_DOS_PARTITION 1 + #define CONFIG_CMD_FAT 1 + #define CONFIG_CMD_EXT2 1 + + /* NAND is the unique module invoke APBH-DMA */ + #define CONFIG_APBH_DMA_V2 + #define CONFIG_MXS_DMA_REG_BASE ABPHDMA_BASE_ADDR +#endif + /*----------------------------------------------------------------------- * Stack sizes * @@ -260,6 +286,7 @@ /* Monitor at beginning of flash */ #define CONFIG_FSL_ENV_IN_MMC +/* #define CONFIG_FSL_ENV_IN_NAND */ /* #define CONFIG_FSL_ENV_IN_SATA */ #define CONFIG_ENV_SECT_SIZE (8 * 1024) |