diff options
| -rw-r--r-- | drivers/mtd/nand/nand_base.c | 17 | ||||
| -rw-r--r-- | nand_spl/nand_boot.c | 64 |
2 files changed, 71 insertions, 10 deletions
diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 151f535..2da1d46 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -931,7 +931,7 @@ static int nand_write_page (struct mtd_info *mtd, struct nand_chip *this, int pa for (i = 0; i < eccbytes; i++, eccidx++) oob_buf[oob_config[eccidx]] = ecc_code[i]; /* If the hardware ecc provides syndromes then - * the ecc code must be written immidiately after + * the ecc code must be written immediately after * the data bytes (words) */ if (this->options & NAND_HWECC_SYNDROME) this->write_buf(mtd, ecc_code, eccbytes); @@ -1299,7 +1299,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, for (i = 0, j = 0; j < mtd->oobavail; i++) { int from = oobsel->oobfree[i][0]; int num = oobsel->oobfree[i][1]; - memcpy(&oob_buf[oob], &oob_data[from], num); + memcpy(&oob_buf[oob+j], &oob_data[from], num); j+= num; } oob += mtd->oobavail; @@ -1644,8 +1644,10 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, this->select_chip(mtd, chipnr); /* Check, if it is write protected */ - if (nand_check_wp(mtd)) + if (nand_check_wp(mtd)) { + printk (KERN_NOTICE "nand_write_ecc: Device is write protected\n"); goto out; + } /* if oobsel is NULL, use chip defaults */ if (oobsel == NULL) @@ -2486,12 +2488,9 @@ int nand_scan (struct mtd_info *mtd, int maxchips) /* The number of bytes available for the filesystem to place fs dependend * oob data */ - if (this->options & NAND_BUSWIDTH_16) { - mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 2); - if (this->autooob->eccbytes & 0x01) - mtd->oobavail--; - } else - mtd->oobavail = mtd->oobsize - (this->autooob->eccbytes + 1); + mtd->oobavail = 0; + for (i=0; this->autooob->oobfree[i][1]; i++) + mtd->oobavail += this->autooob->oobfree[i][1]; /* * check ECC mode, default to software diff --git a/nand_spl/nand_boot.c b/nand_spl/nand_boot.c index e2147cb..bc57725 100644 --- a/nand_spl/nand_boot.c +++ b/nand_spl/nand_boot.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006-2007 + * (C) Copyright 2006-2008 * Stefan Roese, DENX Software Engineering, sr@denx.de. * * This program is free software; you can redistribute it and/or @@ -28,6 +28,10 @@ static int nand_ecc_pos[] = CFG_NAND_ECCPOS; extern void board_nand_init(struct nand_chip *nand); +#if (CFG_NAND_PAGE_SIZE <= 512) +/* + * NAND command for small page NAND devices (512) + */ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) { struct nand_chip *this = mtd->priv; @@ -65,6 +69,64 @@ static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 return 0; } +#else +/* + * NAND command for large page NAND devices (2k) + */ +static int nand_command(struct mtd_info *mtd, int block, int page, int offs, u8 cmd) +{ + struct nand_chip *this = mtd->priv; + int page_offs = offs; + int page_addr = page + block * CFG_NAND_PAGE_COUNT; + + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + /* Emulate NAND_CMD_READOOB */ + if (cmd == NAND_CMD_READOOB) { + page_offs += CFG_NAND_PAGE_SIZE; + cmd = NAND_CMD_READ0; + } + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + this->write_byte(mtd, cmd); + /* Set ALE and clear CLE to start address cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + this->hwcontrol(mtd, NAND_CTL_SETALE); + /* Column address */ + this->write_byte(mtd, page_offs & 0xff); /* A[7:0] */ + this->write_byte(mtd, (uchar)((page_offs >> 8) & 0xff)); /* A[11:9] */ + /* Row address */ + this->write_byte(mtd, (uchar)(page_addr & 0xff)); /* A[19:12] */ + this->write_byte(mtd, (uchar)((page_addr >> 8) & 0xff)); /* A[27:20] */ +#ifdef CFG_NAND_5_ADDR_CYCLE + /* One more address cycle for devices > 128MiB */ + this->write_byte(mtd, (uchar)((page_addr >> 16) & 0x0f)); /* A[xx:28] */ +#endif + /* Latch in address */ + this->hwcontrol(mtd, NAND_CTL_CLRALE); + + /* Begin command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_SETCLE); + /* Write out the start read command */ + this->write_byte(mtd, NAND_CMD_READSTART); + /* End command latch cycle */ + this->hwcontrol(mtd, NAND_CTL_CLRCLE); + + /* + * Wait a while for the data to be ready + */ + if (this->dev_ready) + this->dev_ready(mtd); + else + CFG_NAND_READ_DELAY; + + return 0; +} +#endif static int nand_is_bad_block(struct mtd_info *mtd, int block) { |