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authorBenoît Thébaudeau <benoit.thebaudeau@advansee.com>2013-01-30 11:19:16 +0000
committerStefano Babic <sbabic@denx.de>2013-02-12 13:52:31 +0100
commit1791b1f97f71bb4f110ca851ab10479640b7bc05 (patch)
tree01d05a71d77785352afd7c0e006f26b1effa0c19 /tools/netconsole
parentada02b84636242f5142f74016dbedb50889e93d0 (diff)
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imx: mx6q DDR3 init: Fix RST_to_CKE
MMDC1_MDOR.RST_to_CKE should be set to 500 µs according to the JEDEC specification for DDR3. With a cycle of 15.258 µs, this gives 33 cycles encoded as 0x23 for the bit-field MMDC1_MDOR[5:0]. Signed-off-by: Benoît Thébaudeau <benoit.thebaudeau@advansee.com>
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