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authorShaohui Xie <Shaohui.Xie@freescale.com>2011-12-02 09:38:12 +0800
committerKumar Gala <galak@kernel.crashing.org>2011-12-06 21:44:33 -0600
commit4497861ae7e52dda4dd13db860df4cc0fa7dd852 (patch)
tree524c634f0cf9c2430a39d4eef62b9d0ed0a3dd44 /tools/logos/esd.bmp
parentd194837fc3042d943ba088fcc221d534330b2872 (diff)
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p2041rdb: fix serdes clock map
Description of SerDes clock Bank2 setting in p2041 hardware specification is wrong, the clock map which based on it is wrong either, so fix the serdes clock map. wrong setting of SERDES Reference Clocks Bank2: SW2[5:6] = ON OFF =>100MHz for PCI mode SW2[5:6] = OFF ON =>125MHz for SGMII mode right setting of SERDES Reference Clocks Bank2: SW2[5:6] = OFF OFF =>100MHz for PCI mode SW2[5:6] = OFF ON =>125MHz for SGMII mode SW2[5:6] = ON OFF =>156.25MHZ Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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