tools: kwboot: Add support for UART boot mode patching for Armada XP/38x

Currently, kwboot only allows dynamic UART boot mode patching for SoCs
with header version 0 (Orion, Kirkwood). This patch now enables this "-p"
feature also for SoCs with header version 1 (Armada XP / 38x etc). With
this its possible now to use the UART boot mode without on images that
are generated for other boot devices, like SPI. So no need to change
BOOT_FROM to "uart" for UART xmodem booting any more.

Signed-off-by: Stefan Roese <sr@denx.de>
Tested-by: Kevin Smith <kevin.smith@elecsyscorp.com>
Cc: Luka Perkov <luka.perkov@sartura.hr>
Cc: Dirk Eibach <eibach@gdsys.de>

1 files changed, 98 insertions, 35 deletions

diff --git a/tools/kwbimage.h b/tools/kwbimage.h
index 8e4a4e2..9d2585c 100644
--- a/tools/kwbimage.h
+++ b/tools/kwbimage.h
@@ -29,57 +29,109 @@
 #define IBR_HDR_UART_ID			0x69
 #define IBR_DEF_ATTRIB	 		0x00
 
-enum kwbimage_cmd {
-	CMD_INVALID,
-	CMD_BOOT_FROM,
-	CMD_NAND_ECC_MODE,
-	CMD_NAND_PAGE_SIZE,
-	CMD_SATA_PIO_MODE,
-	CMD_DDR_INIT_DELAY,
-	CMD_DATA
-};
+#define ALIGN_SUP(x, a) (((x) + (a - 1)) & ~(a - 1))
 
-enum kwbimage_cmd_types {
-	CFG_INVALID = -1,
-	CFG_COMMAND,
-	CFG_DATA0,
-	CFG_DATA1
-};
-
-/* typedefs */
-typedef struct bhr_t {
-	uint8_t blockid;		/*0     */
-	uint8_t nandeccmode;		/*1     */
+/* Structure of the main header, version 0 (Kirkwood, Dove) */
+struct main_hdr_v0 {
+	uint8_t  blockid;		/*0     */
+	uint8_t  nandeccmode;		/*1     */
 	uint16_t nandpagesize;		/*2-3   */
 	uint32_t blocksize;		/*4-7   */
 	uint32_t rsvd1;			/*8-11  */
 	uint32_t srcaddr;		/*12-15 */
 	uint32_t destaddr;		/*16-19 */
 	uint32_t execaddr;		/*20-23 */
-	uint8_t satapiomode;		/*24    */
-	uint8_t rsvd3;			/*25    */
+	uint8_t  satapiomode;		/*24    */
+	uint8_t  rsvd3;			/*25    */
 	uint16_t ddrinitdelay;		/*26-27 */
 	uint16_t rsvd2;			/*28-29 */
-	uint8_t ext;			/*30    */
-	uint8_t checkSum;		/*31    */
-} bhr_t, *pbhr_t;
+	uint8_t  ext;			/*30    */
+	uint8_t  checksum;		/*31    */
+};
 
-struct reg_config {
+struct ext_hdr_v0_reg {
 	uint32_t raddr;
 	uint32_t rdata;
 };
 
-typedef struct extbhr_t {
-	uint32_t dramregsoffs;
-	uint8_t rsrvd1[0x20 - sizeof(uint32_t)];
-	struct reg_config rcfg[KWBIMAGE_MAX_CONFIG];
-	uint8_t rsrvd2[7];
-	uint8_t checkSum;
-} extbhr_t, *pextbhr_t;
+#define EXT_HDR_V0_REG_COUNT ((0x1dc - 0x20) / sizeof(struct ext_hdr_v0_reg))
+
+struct ext_hdr_v0 {
+	uint32_t              offset;
+	uint8_t               reserved[0x20 - sizeof(uint32_t)];
+	struct ext_hdr_v0_reg rcfg[EXT_HDR_V0_REG_COUNT];
+	uint8_t               reserved2[7];
+	uint8_t               checksum;
+};
 
 struct kwb_header {
-	bhr_t kwb_hdr;
-	extbhr_t kwb_exthdr;
+	struct main_hdr_v0	kwb_hdr;
+	struct ext_hdr_v0	kwb_exthdr;
+};
+
+/* Structure of the main header, version 1 (Armada 370, Armada XP) */
+struct main_hdr_v1 {
+	uint8_t  blockid;               /* 0 */
+	uint8_t  reserved1;             /* 1 */
+	uint16_t reserved2;             /* 2-3 */
+	uint32_t blocksize;             /* 4-7 */
+	uint8_t  version;               /* 8 */
+	uint8_t  headersz_msb;          /* 9 */
+	uint16_t headersz_lsb;          /* A-B */
+	uint32_t srcaddr;               /* C-F */
+	uint32_t destaddr;              /* 10-13 */
+	uint32_t execaddr;              /* 14-17 */
+	uint8_t  reserved3;             /* 18 */
+	uint8_t  nandblocksize;         /* 19 */
+	uint8_t  nandbadblklocation;    /* 1A */
+	uint8_t  reserved4;             /* 1B */
+	uint16_t reserved5;             /* 1C-1D */
+	uint8_t  ext;                   /* 1E */
+	uint8_t  checksum;              /* 1F */
+};
+
+/*
+ * Header for the optional headers, version 1 (Armada 370, Armada XP)
+ */
+struct opt_hdr_v1 {
+	uint8_t  headertype;
+	uint8_t  headersz_msb;
+	uint16_t headersz_lsb;
+	char     data[0];
+};
+
+/*
+ * Various values for the opt_hdr_v1->headertype field, describing the
+ * different types of optional headers. The "secure" header contains
+ * informations related to secure boot (encryption keys, etc.). The
+ * "binary" header contains ARM binary code to be executed prior to
+ * executing the main payload (usually the bootloader). This is
+ * typically used to execute DDR3 training code. The "register" header
+ * allows to describe a set of (address, value) tuples that are
+ * generally used to configure the DRAM controller.
+ */
+#define OPT_HDR_V1_SECURE_TYPE   0x1
+#define OPT_HDR_V1_BINARY_TYPE   0x2
+#define OPT_HDR_V1_REGISTER_TYPE 0x3
+
+#define KWBHEADER_V1_SIZE(hdr) \
+	(((hdr)->headersz_msb << 16) | (hdr)->headersz_lsb)
+
+enum kwbimage_cmd {
+	CMD_INVALID,
+	CMD_BOOT_FROM,
+	CMD_NAND_ECC_MODE,
+	CMD_NAND_PAGE_SIZE,
+	CMD_SATA_PIO_MODE,
+	CMD_DDR_INIT_DELAY,
+	CMD_DATA
+};
+
+enum kwbimage_cmd_types {
+	CFG_INVALID = -1,
+	CFG_COMMAND,
+	CFG_DATA0,
+	CFG_DATA1
 };
 
 /*
@@ -87,4 +139,15 @@ struct kwb_header {
  */
 void init_kwb_image_type (void);
 
+/*
+ * Byte 8 of the image header contains the version number. In the v0
+ * header, byte 8 was reserved, and always set to 0. In the v1 header,
+ * byte 8 has been changed to a proper field, set to 1.
+ */
+static inline unsigned int image_version(void *header)
+{
+	unsigned char *ptr = header;
+	return ptr[8];
+}
+
 #endif /* _KWBIMAGE_H_ */