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authorHao Zhang <hzhang@ti.com>2014-07-09 19:48:41 +0300
committerTom Rini <trini@ti.com>2014-07-25 16:26:09 -0400
commit101eec50f021a354487a511dc1f72691404b2b48 (patch)
tree3ce38417d6fa5b3131307167e075c18b8f47aa41 /tools/gpimage.c
parent0b868589563ab96384b9a817bc5b82d93c573ea5 (diff)
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keystone2: ddr: add DDR3 PHY configs updated for PG 2.0
Add DDR3 PHY configs updated for PG 2.0 Also add DDR3A PHY reset before init for PG2.0 SoCs. Acked-by: Murali Karicheri <m-maricheri2@ti.com> Signed-off-by: Hao Zhang <hzhang@ti.com> Signed-off-by: Ivan Khoronzhuk <ivan.khoronzhuk@ti.com>
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