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authorIlya Ledvich <ilya@compulab.co.il>2013-06-17 16:59:27 +0300
committerTom Rini <trini@ti.com>2013-07-02 09:21:16 -0400
commit58c86c7d1d8f1bde92211068f2a8a97779c48e99 (patch)
tree9467b18b3e8b77efce64de0339dbf6e083b70a6c /tools/buildman/board.py
parentb0857c45c1f535069acf90e671b5e4b6cf662caf (diff)
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am33xx: fix the ddr_cmdtctrl structure
Fix the wrong mapping between the DDR I/O control registers on AM33XX SoCs and the software representation in the SPL code. The most recent public TRM defines the following DDR I/O control registers offsets: * ddr_cmd0_ioctrl : offset 0x44E11404 * ddr_cmd1_ioctrl : offset 0x44E11408 * ddr_cmd2_ioctrl : offset 0x44E1140C * ddr_data0_ioctrl: offset 0x44E11440 * ddr_data1_ioctrl: offset 0x44E11444 While the struct ddr_cmdtctrl has also some reserved bits in the beginning. The struct is mapped to the address 0x44E11404. As a result "cm0ioctl" points to the ddr_cmd1_ioctrl register, "cm1ioctl" to the ddr_cmd2_ioctrl and etc. Registers ddr_cmd0_ioctrl and ddr_data0_ioctrl are never configured because of this mapping mismatch. Signed-off-by: Ilya Ledvich <ilya@compulab.co.il> Reviewed-by: Peter Korsgaard <jacmet@sunsite.dk>
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