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| author | York Sun <yorksun@freescale.com> | 2012-10-08 07:44:16 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-10-22 14:31:20 -0500 |
| commit | 379c5145ef8f3adbcfeb0a47503838627959cb67 (patch) | |
| tree | d3125ad2d838363ae8b4eb617a38620f19c6e12c /spl | |
| parent | d1001e3f0ce0059a55a870c42bac8aba2e4befec (diff) | |
| download | u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.zip u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.tar.gz u-boot-imx-379c5145ef8f3adbcfeb0a47503838627959cb67.tar.bz2 | |
powerpc/corenet2: fix mismatch DDR sync bit from RCW
Corenet 2nd generation Chassis doesn't have ddr_sync bit in RCW. Only
async mode is supported.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'spl')
0 files changed, 0 insertions, 0 deletions