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authorSiva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>2014-10-28 11:22:19 +0530
committerMichal Simek <michal.simek@xilinx.com>2015-01-26 08:55:57 +0100
commitf60c6fbbc658201f968a22addff7dd1acbe5eaca (patch)
tree36232fa5b868ef1572a9da4baebe235c84b5ac84 /scripts/Makefile.autoconf
parent3ad87ca18203f8b0de0e30b7c12d2ffadf2d8553 (diff)
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ARM: zynq: slcr: Dont modify the reserved bits
Set only the 0-3 bits of the FPGA_RST_CTRL register as other bits should not be set to 1. Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com> Reviewed-by: Nathan Rossi <nathan.rossi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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