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authorAndy Fleming <afleming@freescale.com>2007-02-24 01:16:45 -0600
committerAndrew Fleming-AFLEMING <afleming@freescale.com>2007-04-23 19:58:28 -0500
commit9343dbf85bc03033f2102d8e8543567c2c1ad2d2 (patch)
tree94edfc80e63eb36793f6feed2c46339e0cfb9cce /rtc/rs5c372.c
parent85e7c7a45e3dd9c7ce3e722352ba60f8df1a7a4b (diff)
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Tweak DDR ECC error counter
Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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