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authorStefan Roese <sr@denx.de>2007-10-31 20:51:10 +0100
committerStefan Roese <sr@denx.de>2007-10-31 21:21:47 +0100
commit3db93b8bedd32e914b38976141b3fdf4ea3ff738 (patch)
tree5b50d36fb3398a7a4e51b84f8763e5753dcd0cd8 /post/lib_ppc/cpu.c
parentf71b2888b4b3c870909a0341427b2a914246f81f (diff)
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ppc4xx: Enable CPU POST test for 4xx with dcache enabled
Now with caches enabled (i- and d-cache) on 44x, we need a chance to disable the cache for the CPU POST tests, since these tests consist of self modifying code. This is done via the new change_tlb() function. Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post/lib_ppc/cpu.c')
-rw-r--r--post/lib_ppc/cpu.c11
1 files changed, 11 insertions, 0 deletions
diff --git a/post/lib_ppc/cpu.c b/post/lib_ppc/cpu.c
index 1f2ded2..4ab6d2d 100644
--- a/post/lib_ppc/cpu.c
+++ b/post/lib_ppc/cpu.c
@@ -36,6 +36,7 @@
#include <watchdog.h>
#include <post.h>
+#include <asm/mmu.h>
#if CONFIG_POST & CFG_POST_CPU
@@ -59,6 +60,8 @@ extern int cpu_post_test_multi (void);
extern int cpu_post_test_string (void);
extern int cpu_post_test_complex (void);
+DECLARE_GLOBAL_DATA_PTR;
+
ulong cpu_post_makecr (long v)
{
ulong cr = 0;
@@ -81,6 +84,10 @@ int cpu_post_test (int flags)
WATCHDOG_RESET();
if (ic)
icache_disable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* disable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, TLB_WORD2_I_ENABLE);
+#endif
if (ret == 0)
ret = cpu_post_test_cmp ();
@@ -129,6 +136,10 @@ int cpu_post_test (int flags)
if (ic)
icache_enable ();
+#ifdef CONFIG_4xx_DCACHE
+ /* enable cache */
+ change_tlb(gd->bd->bi_memstart, gd->bd->bi_memsize, 0);
+#endif
WATCHDOG_RESET();