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authorYork Sun <yorksun@freescale.com>2010-09-28 15:20:31 -0700
committerWolfgang Denk <wd@denx.de>2010-10-19 22:28:59 +0200
commit284170309cab2006e7730c65454458680921b16a (patch)
treec62e0f7610edbca14e5ae5a1a964fc1ad00633de /post/drivers/memory.c
parent923527aacefc04d78003829c1e38f3985a334024 (diff)
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Expand POST memory test to support arch-depended implementation.
Add weak functions to enable architecture depended preparation, address advancing, cleaning up and error handling. These weak functions provides the framwork to implemente arch/platform dependent code for initializing/maintenance/restore the start address, size, physical address as well as memory mapping before/between/after memory test. arch_memory_failure_handle can also be implemented in case more care is needed for arch/platform. Signed-off-by: York Sun <yorksun@freescale.com>
Diffstat (limited to 'post/drivers/memory.c')
-rw-r--r--post/drivers/memory.c68
1 files changed, 52 insertions, 16 deletions
diff --git a/post/drivers/memory.c b/post/drivers/memory.c
index 0062360..3f47449 100644
--- a/post/drivers/memory.c
+++ b/post/drivers/memory.c
@@ -452,30 +452,66 @@ static int memory_post_tests (unsigned long start, unsigned long size)
return ret;
}
-int memory_post_test (int flags)
+__attribute__((weak))
+int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
{
- int ret = 0;
bd_t *bd = gd->bd;
- unsigned long memsize = (bd->bi_memsize >= 256 << 20 ?
- 256 << 20 : bd->bi_memsize) - (1 << 20);
+ *vstart = CONFIG_SYS_SDRAM_BASE;
+ *size = (bd->bi_memsize >= 256 << 20 ?
+ 256 << 20 : bd->bi_memsize) - (1 << 20);
/* Limit area to be tested with the board info struct */
- if (CONFIG_SYS_SDRAM_BASE + memsize > (ulong)bd)
- memsize = (ulong)bd - CONFIG_SYS_SDRAM_BASE;
+ if ((*vstart) + (*size) > (ulong)bd)
+ *size = (ulong)bd - *vstart;
+
+ return 0;
+}
- if (flags & POST_SLOWTEST) {
- ret = memory_post_tests (CONFIG_SYS_SDRAM_BASE, memsize);
- } else { /* POST_NORMAL */
+__attribute__((weak))
+int arch_memory_test_advance(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 1;
+}
- unsigned long i;
+__attribute__((weak))
+int arch_memory_test_cleanup(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
+{
+ return 0;
+}
- for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
- if (ret == 0)
- ret = memory_post_tests (i << 20, 0x800);
- if (ret == 0)
- ret = memory_post_tests ((i << 20) + 0xff800, 0x800);
+__attribute__((weak))
+void arch_memory_failure_handle(void)
+{
+ return;
+}
+
+int memory_post_test(int flags)
+{
+ int ret = 0;
+ phys_addr_t phys_offset = 0;
+ u32 memsize, vstart;
+
+ arch_memory_test_prepare(&vstart, &memsize, &phys_offset);
+
+ do {
+ if (flags & POST_SLOWTEST) {
+ ret = memory_post_tests(vstart, memsize);
+ } else { /* POST_NORMAL */
+ unsigned long i;
+ for (i = 0; i < (memsize >> 20) && ret == 0; i++) {
+ if (ret == 0)
+ ret = memory_post_tests(i << 20, 0x800);
+ if (ret == 0)
+ ret = memory_post_tests(
+ (i << 20) + 0xff800, 0x800);
+ }
}
- }
+ } while (!ret &&
+ !arch_memory_test_advance(&vstart, &memsize, &phys_offset));
+
+ arch_memory_test_cleanup(&vstart, &memsize, &phys_offset);
+ if (ret)
+ arch_memory_failure_handle();
return ret;
}