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| author | Lei Wen <[leiwen@marvell.com]> | 2011-11-01 16:25:56 +0530 |
|---|---|---|
| committer | Albert ARIBAUD <albert.u.boot@aribaud.net> | 2011-11-03 22:56:22 +0100 |
| commit | abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456 (patch) | |
| tree | b591517ea82849ff240017312972bfc0daf3fe42 /post/cpu | |
| parent | 0caac5f4155a1db6c5ce921c7f9294b6b46e7744 (diff) | |
| download | u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.zip u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.tar.gz u-boot-imx-abbbbdd7e1232cfe5ccde8da9d4cc1fa609f8456.tar.bz2 | |
armada100: define CONFIG_SYS_CACHELINE_SIZE
By default, on Armada100 SoC DCache Lnd ICache line
lengths are 32 bytes long
Signed-off-by: Lei Wen <leiwen@marvell.com>
Diffstat (limited to 'post/cpu')
0 files changed, 0 insertions, 0 deletions