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| author | Stefan Roese <sr@denx.de> | 2007-08-14 14:41:55 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-14 14:41:55 +0200 |
| commit | c5a172a5fd636c12467429e3f7910e53773979c6 (patch) | |
| tree | 72ed2b65b6a4caaef7a9365f1f75e5b1487c7651 /post/cpu/ppc4xx/ether.c | |
| parent | eb2b4010ae426245172988804ee8d9193fb41038 (diff) | |
| download | u-boot-imx-c5a172a5fd636c12467429e3f7910e53773979c6.zip u-boot-imx-c5a172a5fd636c12467429e3f7910e53773979c6.tar.gz u-boot-imx-c5a172a5fd636c12467429e3f7910e53773979c6.tar.bz2 | |
POST: Add option for external ethernet loopback test
When CFG_POST_ETHER_EXT_LOOPBACK is defined, the ethernet POST
is not done using an internal loopback connection, but by assuming
that an external loopback connector is plugged into the board.
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post/cpu/ppc4xx/ether.c')
| -rw-r--r-- | post/cpu/ppc4xx/ether.c | 9 |
1 files changed, 8 insertions, 1 deletions
diff --git a/post/cpu/ppc4xx/ether.c b/post/cpu/ppc4xx/ether.c index 391c815..ab23ca5 100644 --- a/post/cpu/ppc4xx/ether.c +++ b/post/cpu/ppc4xx/ether.c @@ -68,10 +68,10 @@ static char *rx_buf; static void ether_post_init (int devnum, int hw_addr) { int i; - unsigned mode_reg; #if defined(CONFIG_440GX) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) + unsigned mode_reg; sys_info_t sysinfo; #endif #if defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || defined(CONFIG_440SPE) @@ -185,10 +185,17 @@ static void ether_post_init (int devnum, int hw_addr) mtdcr (malrxcasr, (MAL_TXRX_CASR >> devnum)); /* set internal loopback mode */ +#ifdef CFG_POST_ETHER_EXT_LOOPBACK + out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | 0 | + EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | + EMAC_M1_MF_100MBPS | EMAC_M1_IST | + in32 (EMAC_M1)); +#else out32 (EMAC_M1 + hw_addr, EMAC_M1_FDE | EMAC_M1_ILE | EMAC_M1_RFS_4K | EMAC_M1_TX_FIFO_2K | EMAC_M1_MF_100MBPS | EMAC_M1_IST | in32 (EMAC_M1)); +#endif /* set transmit enable & receive enable */ out32 (EMAC_M0 + hw_addr, EMAC_M0_TXE | EMAC_M0_RXE); |