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| author | Stefan Roese <sr@denx.de> | 2007-08-14 14:39:44 +0200 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2007-08-14 14:39:44 +0200 |
| commit | eb2b4010ae426245172988804ee8d9193fb41038 (patch) | |
| tree | 474f6f1b65d42c698e37f0b48619b388e9969b33 /post/cpu/ppc4xx/cache_4xx.S | |
| parent | d4024bb72dd81695ec099b2199eda0d27c623e62 (diff) | |
| download | u-boot-imx-eb2b4010ae426245172988804ee8d9193fb41038.zip u-boot-imx-eb2b4010ae426245172988804ee8d9193fb41038.tar.gz u-boot-imx-eb2b4010ae426245172988804ee8d9193fb41038.tar.bz2 | |
POST: Add ppc405 support to cache and UART POST
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post/cpu/ppc4xx/cache_4xx.S')
| -rw-r--r-- | post/cpu/ppc4xx/cache_4xx.S | 44 |
1 files changed, 44 insertions, 0 deletions
diff --git a/post/cpu/ppc4xx/cache_4xx.S b/post/cpu/ppc4xx/cache_4xx.S index dddd76b..d5cb075 100644 --- a/post/cpu/ppc4xx/cache_4xx.S +++ b/post/cpu/ppc4xx/cache_4xx.S @@ -37,6 +37,13 @@ .text + /* + * All 44x variants deal with cache management differently + * because they have the address translation always enabled. + * The 40x ppc's don't use address translation in U-Boot at all, + * so we have to distinguish here between 40x and 44x. + */ +#ifdef CONFIG_440 /* void cache_post_disable (int tlb) */ cache_post_disable: @@ -68,6 +75,43 @@ cache_post_wb: sync isync blr +#else +/* void cache_post_disable (int tlb) + */ +cache_post_disable: + lis r0, 0x0000 + ori r0, r0, 0x0000 + mtdccr r0 + sync + isync + blr + +/* void cache_post_wt (int tlb) + */ +cache_post_wt: + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdccr r0 + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdcwr r0 + sync + isync + blr + +/* void cache_post_wb (int tlb) + */ +cache_post_wb: + lis r0, 0x8000 + ori r0, r0, 0x0000 + mtdccr r0 + lis r0, 0x0000 + ori r0, r0, 0x0000 + mtdcwr r0 + sync + isync + blr +#endif /* void cache_post_dinvalidate (void *p, int size) */ |