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| author | Stefan Roese <sr@denx.de> | 2008-02-19 22:01:57 +0100 |
|---|---|---|
| committer | Stefan Roese <sr@denx.de> | 2008-03-15 07:28:03 +0100 |
| commit | 84a999b6cdd0b02dc7de2cacc306eaa84afe2b46 (patch) | |
| tree | 7d7ab3c7fd14897ebcf028da9572d79614fb05e0 /post/cpu/ppc4xx/cache.c | |
| parent | c3307fa186af85771924c434997089b8104c0a46 (diff) | |
| download | u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.zip u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.tar.gz u-boot-imx-84a999b6cdd0b02dc7de2cacc306eaa84afe2b46.tar.bz2 | |
ppc4xx: program_tlb now uses 64bit physical addess
This patch changes the physical addess parameter from 32bit to 64bit.
This is needed for 36bit 4xx platforms to access areas located
beyond the 4GB border, like SoC peripherals (EBC etc.).
Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post/cpu/ppc4xx/cache.c')
| -rw-r--r-- | post/cpu/ppc4xx/cache.c | 2 |
1 files changed, 0 insertions, 2 deletions
diff --git a/post/cpu/ppc4xx/cache.c b/post/cpu/ppc4xx/cache.c index c86a150..466ca92 100644 --- a/post/cpu/ppc4xx/cache.c +++ b/post/cpu/ppc4xx/cache.c @@ -42,8 +42,6 @@ #define CACHE_POST_SIZE 1024 -void program_tlb(u32 phys_addr, u32 virt_addr, u32 size, u32 tlb_word2_i_value); - int cache_post_test1 (int tlb, void *p, int size); int cache_post_test2 (int tlb, void *p, int size); int cache_post_test3 (int tlb, void *p, int size); |