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| author | Thierry Reding <treding@nvidia.com> | 2014-12-09 22:25:26 -0700 |
|---|---|---|
| committer | Tom Warren <twarren@nvidia.com> | 2014-12-18 13:21:41 -0700 |
| commit | d58acdcbfb338abdb77cfea8ada500aea277decf (patch) | |
| tree | 1fe7b0b2032fedd7e5728146159c2e7c9d9eb153 /post/cpu/mpc8xx/cache_8xx.S | |
| parent | dad3ba0f0bb5ee2e87881c9f3a7ecfb8db384b2b (diff) | |
| download | u-boot-imx-d58acdcbfb338abdb77cfea8ada500aea277decf.zip u-boot-imx-d58acdcbfb338abdb77cfea8ada500aea277decf.tar.gz u-boot-imx-d58acdcbfb338abdb77cfea8ada500aea277decf.tar.bz2 | |
net: rtl8169: Use non-cached memory if available
To work around potential issues with explicit cache maintenance of the
RX and TX descriptor rings, allocate them from a pool of uncached memory
if the architecture supports it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Simon Glass <sjg@chromium.org>
Signed-off-by: Tom Warren <twarren@nvidia.com>
Diffstat (limited to 'post/cpu/mpc8xx/cache_8xx.S')
0 files changed, 0 insertions, 0 deletions