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authorMichal Simek <michal.simek@xilinx.com>2015-09-08 16:55:42 +0200
committerMichal Simek <michal.simek@xilinx.com>2015-11-19 14:03:05 +0100
commit242b15476c94752494670a3e419e639d2df08dfd (patch)
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net: zynq: Fix mdc clock division setting for 100Mbit/s
Using set and clear macro is incorrect because it is not overwritting origin mdc clock division setup. For example origin setup is 8(0b001) and new setup is 64(0b100) which means 0b101 is setup which is 96 divider. Using writel to rewrite all setting like for 1000Mbit/s case. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
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