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authorStefan Roese <sr@denx.de>2007-07-31 08:37:01 +0200
committerStefan Roese <sr@denx.de>2007-07-31 08:37:01 +0200
commitea9f6bce383cc9fbcdee28b5836109b1a6dba574 (patch)
treed9059c7f3842f92c0bcf047b86fab4c44863ea78 /post/board/lwmon5
parent27a528fb41433c4c1e2b5d6bd3fd8d78606fc724 (diff)
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ppc4xx: Update 440EPx lwmon5 board support
- Clear ECC status regs after ECC POST test - Set dcbz for ECC generation with caches enabled as default - Code cleanup Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'post/board/lwmon5')
-rw-r--r--post/board/lwmon5/ecc.c12
1 files changed, 11 insertions, 1 deletions
diff --git a/post/board/lwmon5/ecc.c b/post/board/lwmon5/ecc.c
index 7f04f9a..3fa3ba6 100644
--- a/post/board/lwmon5/ecc.c
+++ b/post/board/lwmon5/ecc.c
@@ -236,7 +236,6 @@ int ecc_post_test (int flags)
mfsdram(DDR0_00, value);
mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
-
/* enable full support of ECC */
mfsdram(DDR0_22, value);
mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK)
@@ -247,6 +246,17 @@ int ecc_post_test (int flags)
if (ret)
break;
}
+
+ /* clear error status */
+ mfsdram(DDR0_00, value);
+ mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL);
+
+ /*
+ * Clear possible errors resulting from ECC testing.
+ * If not done, then we could get an interrupt later on when
+ * exceptions are enabled.
+ */
+ set_mcsr(get_mcsr());
#endif
return ret;