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| author | Lily Zhang <r58066@freescale.com> | 2011-07-21 16:52:46 +0800 |
|---|---|---|
| committer | Xinyu Chen <xinyu.chen@freescale.com> | 2011-07-27 11:37:48 +0800 |
| commit | 820cfb872d92ac7c3ccf0eca351f6761ef86684f (patch) | |
| tree | 3109ed704dcf0e34b9e4846053642a7f0593a0d8 /onenand_ipl | |
| parent | 69c434e51c7711b8978af53264cd68902b91a0c5 (diff) | |
| download | u-boot-imx-820cfb872d92ac7c3ccf0eca351f6761ef86684f.zip u-boot-imx-820cfb872d92ac7c3ccf0eca351f6761ef86684f.tar.gz u-boot-imx-820cfb872d92ac7c3ccf0eca351f6761ef86684f.tar.bz2 | |
ENGR00151695 mx53 ddr3: update ESDREF and MR0
Updated mx53 ddr3 script according to MX53_TO2_DDR3_LCB_SMD_ARDb_v1.inc
from Michael J Kjar on July 8, 2011:
-change ESDREF[REF_SEL]=01 (for 32KHz), from incorrect setting of 00 (64KHz)
-change DDR3 MR0 write to "setmem /32 0x63fd901c = 0x052080b0" from
"0x092080b0". This chagned write recovery from 8 clocks to 6 clocks
(in line with ESDCFG1[tWR])
Signed-off-by: Lily Zhang <r58066@freescale.com>
Diffstat (limited to 'onenand_ipl')
0 files changed, 0 insertions, 0 deletions