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authorDave Liu <daveliu@freescale.com>2009-03-27 14:32:43 +0800
committerWolfgang Denk <wd@denx.de>2009-06-09 22:58:05 +0200
commit1b5291dddf5f16c7ae10e3cb165882fa96038b26 (patch)
tree7ac021abc9b1e6f08dc64de6128868a28cabd175 /nios_config.mk
parentf97db54d7e773a32100247ee002686b6a014a87d (diff)
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85xx: Fix the clock adjust of mpc8569mds board
Currently the clk_adj is 6 (3/4 cycle), The settings will cause the DDR controller hang at the data init. Change the clk_adj from 6 to 4 (1/2 cycle), make the memory system stable. Signed-off-by: Dave Liu <daveliu@freescale.com>
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