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| author | Gururaja Hebbar K R <gururajakr@sanyo.co.in> | 2008-08-25 11:11:34 +0200 |
|---|---|---|
| committer | Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> | 2008-08-25 13:00:03 +0200 |
| commit | e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6 (patch) | |
| tree | 5cc265595c6f75283f7e67e8d3a3ea5575afa868 /net | |
| parent | 535cfa4f3de86cf48d6c0af1daf33aebdca089f9 (diff) | |
| download | u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.zip u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.tar.gz u-boot-imx-e8f1207bbf2df6fb693ee1aa3329b2014c92e5e6.tar.bz2 | |
Correct ARM Versatile Timer Initialization
- According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271),
-- Timer Value Register @ TIMER Base + 4 is Read-only.
-- Prescale Value (Bits 3-2 of TIMER Control register)
can only be one of 00,01,10. 11 is undefined.
-- CFG_HZ for Versatile board is set to
#define CFG_HZ (1000000 / 256)
So Prescale bits is set to indicate
- 8 Stages of Prescale, Clock divided by 256
- The Timer Control Register has one Undefined/Shouldn't Use Bit
So we should do read/modify/write Operation
Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
Diffstat (limited to 'net')
0 files changed, 0 insertions, 0 deletions