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authorPaul Burton <paul.burton@imgtec.com>2014-04-07 16:41:47 +0100
committerTom Rini <trini@ti.com>2014-04-18 10:42:30 -0400
commita354ddc3d7412c6d7cc702de60be32e580ccf348 (patch)
treecf49a6530090852c02dab05228ebc358de25787a /net
parentf1ae382dfd3850f4fbf34d794a31b8a1d1a5c389 (diff)
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pcnet: align rx buffers for cache invalidation
The RX buffers are invalidated when a packet is received, however they were not suitably cache-line aligned. Allocate them seperately to the pcnet_priv structure and align to ARCH_DMA_MINALIGN in order to ensure suitable alignment for the cache invalidation, preventing anything else being placed in the same lines & lost. Signed-off-by: Paul Burton <paul.burton@imgtec.com>
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