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authorDaniel Gorsulowski <Daniel.Gorsulowski@esd.eu>2010-01-20 08:00:11 +0100
committerTom Rix <Tom.Rix@windriver.com>2010-01-21 17:20:10 -0600
commit69df282a781dfe7a1bfc62acf0605992d3ea6c52 (patch)
tree898b79aceceb0e978195e7714cb7f4eaa781494e /net/eth.c
parentd41768df35e857ca44d1941212d68a93ca6240fe (diff)
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at91: Enable slow master clock on meesc board
Normally the processor clock has a divisor of 2. In some cases this this needs to be set to 4. Check the user has set environment mdiv to 4 to change the divisor. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
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