diff options
| author | Laurence Withers <lwithers@guralp.com> | 2011-09-26 16:02:30 +0000 |
|---|---|---|
| committer | Scott Wood <scottwood@freescale.com> | 2011-10-10 15:28:05 -0500 |
| commit | 60161943719c4054453f6932ad2bd5fe2285bf1b (patch) | |
| tree | 84e782cd83a6a2a3807d718fb080c8053fb2fa1b /nand_spl | |
| parent | 0841ca90f22d73b0ea4642ef1ce33d879bb2f3ff (diff) | |
| download | u-boot-imx-60161943719c4054453f6932ad2bd5fe2285bf1b.zip u-boot-imx-60161943719c4054453f6932ad2bd5fe2285bf1b.tar.gz u-boot-imx-60161943719c4054453f6932ad2bd5fe2285bf1b.tar.bz2 | |
NAND: davinci: choose correct 1-bit h/w ECC reg
In nand_davinci_readecc(), select the correct NANDF<n>ECC register based
on CONFIG_SYS_NAND_CS rather than hardcoding the choice of NANDF1ECC.
This allows 1-bit hardware ECC to work with chip select other than CS2.
Note this now matches the usage in nand_davinci_enable_hwecc(), which
already had the correct handling, and allows refactoring to a single
function encapsulating the register read.
Without this fix, writing NAND pages to a chip not wired to CS2 would
result in in the ECC calculation always returning FFFFFF for each
512-byte segment, and reading back a correctly written page (one with
ECC intact) would always fail. With this fix, the ECC is written and
verified correctly.
Signed-off-by: Laurence Withers <lwithers@guralp.com>
Signed-off-by: Scott Wood <scottwood@freescale.com>
Diffstat (limited to 'nand_spl')
0 files changed, 0 insertions, 0 deletions