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| author | York Sun <yorksun@freescale.com> | 2013-03-25 07:33:19 +0000 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2013-05-14 16:00:27 -0500 |
| commit | 054dfd9b9d9fedac87bffdbde72683e8e678eecc (patch) | |
| tree | 4bc2a6de51e662a1234814a7a1ce6622aaa1f7d0 /nand_spl | |
| parent | f9772444a0fe326f7c986884df6c0b39d19fef06 (diff) | |
| download | u-boot-imx-054dfd9b9d9fedac87bffdbde72683e8e678eecc.zip u-boot-imx-054dfd9b9d9fedac87bffdbde72683e8e678eecc.tar.gz u-boot-imx-054dfd9b9d9fedac87bffdbde72683e8e678eecc.tar.bz2 | |
powerpc/t4240qds: Update DDR timing table
Update the timing table to support more rank density, based on the theory
that similar density DIMMs have similar clock adjust and write level start
timing. Update the timing for 1600 and 1866 MT/s. Tested with Micron
MT18JSF1G72AZ-1G9E1 DIMMs, iDIMM M3CN-4GMJ3C0C-M92.
Signed-off-by: York Sun <yorksun@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl')
0 files changed, 0 insertions, 0 deletions