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| author | Andy Fleming <afleming@freescale.com> | 2012-10-23 19:03:46 -0500 |
|---|---|---|
| committer | Andy Fleming <afleming@freescale.com> | 2012-11-27 17:45:17 -0600 |
| commit | e76cd5d4cf311da7d40adc5d6e9b425509cf0205 (patch) | |
| tree | 36c37082482ef310e6419ce57b1b352edccdb29d /nand_spl/board | |
| parent | 66dc452bfe13b0e276adddf3997b9c5abc00115d (diff) | |
| download | u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.zip u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.tar.gz u-boot-imx-e76cd5d4cf311da7d40adc5d6e9b425509cf0205.tar.bz2 | |
8xxx: Change all 8*xx_DDR addresses to 8xxx
There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.
This patch does:
s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g
All 85xx, 86xx, and 83xx have been built with this change.
Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>
Diffstat (limited to 'nand_spl/board')
| -rw-r--r-- | nand_spl/board/freescale/p1010rdb/nand_boot.c | 2 | ||||
| -rw-r--r-- | nand_spl/board/freescale/p1023rds/nand_boot.c | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index 9c35690..3c7bc2b 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -35,7 +35,7 @@ unsigned long ddr_freq_mhz; void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c index 89e339d..d6756fb 100644 --- a/nand_spl/board/freescale/p1023rds/nand_boot.c +++ b/nand_spl/board/freescale/p1023rds/nand_boot.c @@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR; /* Fixed sdram init -- doesn't use serial presence detect. */ void sdram_init(void) { - ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR; + ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR; set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1); |