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authorMatthew McClintock <msm@freescale.com>2012-08-13 08:10:39 +0000
committerAndy Fleming <afleming@freescale.com>2012-08-23 10:24:17 -0500
commitabbe536ebc3ee974593b115de716705f0091344a (patch)
tree9b41f2c417dd6ef6f5fed26f0773de4ea4737390 /nand_spl/board/freescale
parentc8f9802a72030e783152040b07c3c7694f953dd3 (diff)
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powerpc/p1010rdb: nandboot: compare SVR properly
We were not comparing the SVRs properly previously. This comparison will properly shift the SVR and mask off the E bit This fixes the boot output to show the correct DDR bus width: 512 MiB (DDR3, 16-bit, CL=5, ECC off) instead of 512 MiB (DDR3, 32-bit, CL=5, ECC off) Signed-off-by: Matthew McClintock <msm@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl/board/freescale')
-rw-r--r--nand_spl/board/freescale/p1010rdb/nand_boot.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 1f89ab5..f5294d0 100644
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -35,7 +35,8 @@ unsigned long ddr_freq_mhz;
void sdram_init(void)
{
ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
- u32 svr = mfspr(SPRN_SVR);
+ /* mask off E bit */
+ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE);
out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);