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author | Matthew McClintock <msm@freescale.com> | 2012-08-13 08:10:42 +0000 |
---|---|---|
committer | Andy Fleming <afleming@freescale.com> | 2012-08-23 10:24:17 -0500 |
commit | ae6beb24d7589f1b8b7aa3519afb3c7cdf8e66e5 (patch) | |
tree | 52381b535873eb38846efb0f11f6315b9018705f /nand_spl/board/freescale/p1010rdb | |
parent | 02ea538ce9fa8325f7d15c69cf87c950c5fe1f57 (diff) | |
download | u-boot-imx-ae6beb24d7589f1b8b7aa3519afb3c7cdf8e66e5.zip u-boot-imx-ae6beb24d7589f1b8b7aa3519afb3c7cdf8e66e5.tar.gz u-boot-imx-ae6beb24d7589f1b8b7aa3519afb3c7cdf8e66e5.tar.bz2 |
nand_spl: change out_be32 to raw_writel and depend on subsequent sync
This change reduces the SPL size by removing the redundant syncs produced
by out_be32 and just replies on one final sync
Done with:
sed -r '/in_be32/b; s/(out_be32)\(([^,]*),\s+(.*)\)/__raw_writel(\3, \2)/g' -i `git grep --name-only sdram_init nand_spl/`
Signed-off-by: Matthew McClintock <msm@freescale.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Andy Fleming <afleming@freescale.com>
Diffstat (limited to 'nand_spl/board/freescale/p1010rdb')
-rw-r--r-- | nand_spl/board/freescale/p1010rdb/nand_boot.c | 54 |
1 files changed, 26 insertions, 28 deletions
diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c index a075509..9c35690 100644 --- a/nand_spl/board/freescale/p1010rdb/nand_boot.c +++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c @@ -39,39 +39,37 @@ void sdram_init(void) /* mask off E bit */ u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR)); - out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE); - out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS); - out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG); - out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_CONTROL_2); - out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT); + __raw_writel(CONFIG_SYS_DDR_CONTROL | SDRAM_CFG_32_BE, &ddr->sdram_cfg); + __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds); + __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config); + __raw_writel(CONFIG_SYS_DDR_CONTROL_2, &ddr->sdram_cfg_2); + __raw_writel(CONFIG_SYS_DDR_DATA_INIT, &ddr->sdram_data_init); if (ddr_freq_mhz < 700) { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_667); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_667); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_667); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_667); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_667); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_667); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_667); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_667); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_667); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_667, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_667, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_667, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_667, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_667, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_667, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_667, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_667, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_667, &ddr->ddr_wrlvl_cntl); } else { - out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3_800); - out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0_800); - out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1_800); - out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2_800); - out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_MODE_1_800); - out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_MODE_2_800); - out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_INTERVAL_800); - out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CTRL_800); - out_be32(&ddr->ddr_wrlvl_cntl, - CONFIG_SYS_DDR_WRLVL_CONTROL_800); + __raw_writel(CONFIG_SYS_DDR_TIMING_3_800, &ddr->timing_cfg_3); + __raw_writel(CONFIG_SYS_DDR_TIMING_0_800, &ddr->timing_cfg_0); + __raw_writel(CONFIG_SYS_DDR_TIMING_1_800, &ddr->timing_cfg_1); + __raw_writel(CONFIG_SYS_DDR_TIMING_2_800, &ddr->timing_cfg_2); + __raw_writel(CONFIG_SYS_DDR_MODE_1_800, &ddr->sdram_mode); + __raw_writel(CONFIG_SYS_DDR_MODE_2_800, &ddr->sdram_mode_2); + __raw_writel(CONFIG_SYS_DDR_INTERVAL_800, &ddr->sdram_interval); + __raw_writel(CONFIG_SYS_DDR_CLK_CTRL_800, &ddr->sdram_clk_cntl); + __raw_writel(CONFIG_SYS_DDR_WRLVL_CONTROL_800, &ddr->ddr_wrlvl_cntl); } - out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4); - out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5); - out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CONTROL); + __raw_writel(CONFIG_SYS_DDR_TIMING_4, &ddr->timing_cfg_4); + __raw_writel(CONFIG_SYS_DDR_TIMING_5, &ddr->timing_cfg_5); + __raw_writel(CONFIG_SYS_DDR_ZQ_CONTROL, &ddr->ddr_zq_cntl); /* P1014 and it's derivatives support max 16bit DDR width */ if (svr == SVR_P1014) { |