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authorStefan Roese <sr@denx.de>2008-04-30 14:51:36 +0200
committerStefan Roese <sr@denx.de>2008-04-30 14:51:36 +0200
commit4f27098e5b0736989b13cd61d7bca94b3574cf5f (patch)
tree8c4ba5b95d63c12bb7768f613385b003796c9df2 /nand_spl/board/amcc/canyonlands
parentea9202a659dc75996facf1475f1866a19a9d3129 (diff)
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ppc4xx: Adapt Canyonlands fixed DDR2 setup to new DIMM module
This patch changes the Canyonlands/Glacier fixed DDR2 controller setup used for NAND booting to match the values needed for the new 512MB DIMM modules shipped with the productions boards: Crucial: CT6464AC667.8FB Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'nand_spl/board/amcc/canyonlands')
-rw-r--r--nand_spl/board/amcc/canyonlands/ddr2_fixed.c12
1 files changed, 7 insertions, 5 deletions
diff --git a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
index 79f3b0f..9010fca 100644
--- a/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
+++ b/nand_spl/board/amcc/canyonlands/ddr2_fixed.c
@@ -49,20 +49,21 @@ long int initdram(int board_type)
* enabled. This will only work for the same memory
* configuration as used here:
*
- * Crucial CT6464AC53E.4FE - 512MB SO-DIMM
+ * Crucial CT6464AC667.8FB - 512MB SO-DIMM
*
*/
mtsdram(SDRAM_MCOPT2, 0x00000000);
- mtsdram(SDRAM_MCOPT1, 0x05322000);
+ mtsdram(SDRAM_MCOPT1, 0x05122000);
mtsdram(SDRAM_MODT0, 0x01000000);
- mtsdram(SDRAM_CODT, 0x00800021);
+ mtsdram(SDRAM_CODT, 0x02800021);
mtsdram(SDRAM_WRDTR, 0x82000823);
mtsdram(SDRAM_CLKTR, 0x40000000);
mtsdram(SDRAM_MB0CF, 0x00000201);
+ mtsdram(SDRAM_MB1CF, 0x00000201);
mtsdram(SDRAM_RTR, 0x06180000);
mtsdram(SDRAM_SDTR1, 0x80201000);
mtsdram(SDRAM_SDTR2, 0x42103243);
- mtsdram(SDRAM_SDTR3, 0x0A0D0D1A);
+ mtsdram(SDRAM_SDTR3, 0x0A0D0D16);
mtsdram(SDRAM_MMODE, 0x00000632);
mtsdram(SDRAM_MEMODE, 0x00000040);
mtsdram(SDRAM_INITPLR0, 0xB5380000);
@@ -86,7 +87,8 @@ long int initdram(int board_type)
wait_init_complete();
- mtdcr(SDRAM_R0BAS, 0x0000F000); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R0BAS, 0x0000F800); /* MQ0_B0BAS */
+ mtdcr(SDRAM_R1BAS, 0x0400F800); /* MQ0_B1BAS */
mtsdram(SDRAM_RDCC, 0x40000000);
mtsdram(SDRAM_RQDC, 0x80000038);