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authorWolfgang Denk <wd@fifi.denx.de>2006-06-16 16:57:18 +0200
committerWolfgang Denk <wd@fifi.denx.de>2006-06-16 16:57:18 +0200
commit30a43cc2aeb84dfd96a411fb2da2ff4ab10dcd5a (patch)
treeedaf73ade1f4ae3fb1b764498d62715f68bd88f6 /mips_config.mk
parent10af6d53bcf068b91c1b6ce6aa0fad5d89b36f81 (diff)
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Bugfix in I2C initialisation on S3C2400.
If the bus is blocked because of a previously interrupted transfer, up to eleven clocks are generated on the I2CSCL line to complete the transfer and to free the bus. With this fix pin I2CSCL (PG6) is really configured as GPIO so the clock pulses are really generated. Patch by Martin Krause, 04 Apr 2006
Diffstat (limited to 'mips_config.mk')
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