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| author | Nishanth Menon <nm@ti.com> | 2009-11-09 09:29:34 -0500 |
|---|---|---|
| committer | Tom Rix <Tom.Rix@windriver.com> | 2009-11-27 16:26:17 -0600 |
| commit | d414aae552bc229dafcad92028effb4a8306c7a5 (patch) | |
| tree | 61893df2fd2a1685b47fb28fd7411b8afd288049 /lib_ppc/ppccache.S | |
| parent | 30563a04bff73fd4fbd840b846f4b6459759a839 (diff) | |
| download | u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.zip u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.tar.gz u-boot-imx-d414aae552bc229dafcad92028effb4a8306c7a5.tar.bz2 | |
OMAP3: Fix SDRC init
Defaults are for Infineon DDR timings.
Since none of the supported boards currently do
XIP boot, these seem to be faulty. fix the values
as per the calculations(ACTIMA,B), conf
the sdrc power with pwdnen and wakeupproc bits
Signed-off-by: Nishanth Menon <nm@ti.com>
Diffstat (limited to 'lib_ppc/ppccache.S')
0 files changed, 0 insertions, 0 deletions