rename CFG_ macros to CONFIG_SYS

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>

3 files changed, 23 insertions, 23 deletions

diff --git a/lib_nios2/board.c b/lib_nios2/board.c
index 7ffb3f0..d759f0f 100644
--- a/lib_nios2/board.c
+++ b/lib_nios2/board.c
@@ -31,7 +31,7 @@
 #ifdef CONFIG_STATUS_LED
 #include <status_led.h>
 #endif
-#if defined(CFG_NIOS_EPCSBASE)
+#if defined(CONFIG_SYS_NIOS_EPCSBASE)
 #include <nios2-epcs.h>
 #endif
 
@@ -66,8 +66,8 @@ static	ulong	mem_malloc_brk	 = 0;
  */
 static void mem_malloc_init (void)
 {
-	mem_malloc_start = CFG_MALLOC_BASE;
-	mem_malloc_end = mem_malloc_start + CFG_MALLOC_LEN;
+	mem_malloc_start = CONFIG_SYS_MALLOC_BASE;
+	mem_malloc_end = mem_malloc_start + CONFIG_SYS_MALLOC_LEN;
 	mem_malloc_brk = mem_malloc_start;
 	memset ((void *) mem_malloc_start,
 		0,
@@ -96,7 +96,7 @@ init_fnc_t *init_sequence[] = {
 #if defined(CONFIG_BOARD_EARLY_INIT_F)
 	board_early_init_f,	/* Call board-specific init code early.*/
 #endif
-#if defined(CFG_NIOS_EPCSBASE)
+#if defined(CONFIG_SYS_NIOS_EPCSBASE)
 	epcs_reset,
 #endif
 
@@ -119,25 +119,25 @@ void board_init (void)
 	int i;
 
 	/* Pointer is writable since we allocated a register for it.
-	 * Nios treats CFG_GBL_DATA_OFFSET as an address.
+	 * Nios treats CONFIG_SYS_GBL_DATA_OFFSET as an address.
 	 */
-	gd = (gd_t *)CFG_GBL_DATA_OFFSET;
+	gd = (gd_t *)CONFIG_SYS_GBL_DATA_OFFSET;
 	/* compiler optimization barrier needed for GCC >= 3.4 */
 	__asm__ __volatile__("": : :"memory");
 
-	memset( gd, 0, CFG_GBL_DATA_SIZE );
+	memset( gd, 0, CONFIG_SYS_GBL_DATA_SIZE );
 
 	gd->bd = (bd_t *)(gd+1);	/* At end of global data */
 	gd->baudrate = CONFIG_BAUDRATE;
 	gd->cpu_clk = CONFIG_SYS_CLK_FREQ;
 
 	bd = gd->bd;
-	bd->bi_memstart	= CFG_SDRAM_BASE;
-	bd->bi_memsize = CFG_SDRAM_SIZE;
-	bd->bi_flashstart = CFG_FLASH_BASE;
-#if	defined(CFG_SRAM_BASE) && defined(CFG_SRAM_SIZE)
-	bd->bi_sramstart= CFG_SRAM_BASE;
-	bd->bi_sramsize	= CFG_SRAM_SIZE;
+	bd->bi_memstart	= CONFIG_SYS_SDRAM_BASE;
+	bd->bi_memsize = CONFIG_SYS_SDRAM_SIZE;
+	bd->bi_flashstart = CONFIG_SYS_FLASH_BASE;
+#if	defined(CONFIG_SYS_SRAM_BASE) && defined(CONFIG_SYS_SRAM_SIZE)
+	bd->bi_sramstart= CONFIG_SYS_SRAM_BASE;
+	bd->bi_sramsize	= CONFIG_SYS_SRAM_SIZE;
 #endif
 	bd->bi_baudrate	= CONFIG_BAUDRATE;
 
diff --git a/lib_nios2/cache.S b/lib_nios2/cache.S
index eb7735a..ee3b4b7 100644
--- a/lib_nios2/cache.S
+++ b/lib_nios2/cache.S
@@ -29,8 +29,8 @@
 
 flush_dcache:
 	add	r5, r5, r4
-	movhi	r8, %hi(CFG_DCACHELINE_SIZE)
-	ori	r8, r8, %lo(CFG_DCACHELINE_SIZE)
+	movhi	r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+	ori	r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
 0:	flushd	0(r4)
 	add	r4, r4, r8
 	bltu	r4, r5, 0b
@@ -41,8 +41,8 @@ flush_dcache:
 
 flush_icache:
 	add	r5, r5, r4
-	movhi	r8, %hi(CFG_ICACHELINE_SIZE)
-	ori	r8, r8, %lo(CFG_ICACHELINE_SIZE)
+	movhi	r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
+	ori	r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
 1:	flushi	r4
 	add	r4, r4, r8
 	bltu	r4, r5, 1b
@@ -55,16 +55,16 @@ flush_cache:
 	mov	r9, r4
 	mov	r10, r5
 
-	movhi	r8, %hi(CFG_DCACHELINE_SIZE)
-	ori	r8, r8, %lo(CFG_DCACHELINE_SIZE)
+	movhi	r8, %hi(CONFIG_SYS_DCACHELINE_SIZE)
+	ori	r8, r8, %lo(CONFIG_SYS_DCACHELINE_SIZE)
 0:	flushd	0(r4)
 	add	r4, r4, r8
 	bltu	r4, r5, 0b
 
 	mov	r4, r9
 	mov	r5, r10
-	movhi	r8, %hi(CFG_ICACHELINE_SIZE)
-	ori	r8, r8, %lo(CFG_ICACHELINE_SIZE)
+	movhi	r8, %hi(CONFIG_SYS_ICACHELINE_SIZE)
+	ori	r8, r8, %lo(CONFIG_SYS_ICACHELINE_SIZE)
 1:	flushi	r4
 	add	r4, r4, r8
 	bltu	r4, r5, 1b
diff --git a/lib_nios2/mult.c b/lib_nios2/mult.c
index 66bb64d..ec8139e 100644
--- a/lib_nios2/mult.c
+++ b/lib_nios2/mult.c
@@ -20,7 +20,7 @@
 
 #include <common.h>
 
-#if !defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP)
+#if !defined(CONFIG_SYS_NIOS_MULT_HW) && !defined(CONFIG_SYS_NIOS_MULT_MSTEP)
 
 #include "math.h"
 
@@ -53,4 +53,4 @@ UHItype __mulhi3 (UHItype a, UHItype b)
 	return c;
 }
 
-#endif /*!defined(CFG_NIOS_MULT_HW) && !defined(CFG_NIOS_MULT_MSTEP) */
+#endif /*!defined(CONFIG_SYS_NIOS_MULT_HW) && !defined(CONFIG_SYS_NIOS_MULT_MSTEP) */