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authorAnson Huang <b20788@freescale.com>2012-12-05 13:58:34 -0500
committerAnson Huang <b20788@freescale.com>2012-12-13 14:34:43 -0500
commitb7c5badf94ffbe6cd0845efbb75e16e05e3af404 (patch)
tree9583c97f389b54a04940dcd047caf64406e42722 /lib_microblaze
parentd31df11541ea0d1a0bf1ed7463fd30a25b65f98c (diff)
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ENGR00235821 mx6: correct work flow of PFDs
PFDs need to be gate/ungate after PLL lock to reset PFDs to right state. Otherwise PFDs may lose correct state in state-machine, then no output clock. For i.MX6DL and i.MX6SL, ROM have taken care of PFD396 already since the bus clock needs it. Signed-off-by: Anson Huang <b20788@freescale.com>
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