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authorTerry <r65388@freescale.com>2011-03-17 16:18:38 +0800
committerTerry <r65388@freescale.com>2011-03-17 17:58:02 +0800
commit5f1d08aefc9adbf034a06b98eb7416c406057ee9 (patch)
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parenta7b2f005d5b8a96f8cb0bd3c87aa2dba69aef95a (diff)
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ENGR00140767: Improve mx5x DDR clock function
As now mx51 DDR frequency is derived from PLL1. We need to get DDR frequency from PLL1. Mx53 don't use PLL1 for ddr clock source, so just the precision is adjusted. Mx50 don't support clk command yet. DDR config function is modified according to mx50 spec, but not tested yet. Signed-off-by: Terry <r65388@freescale.com>
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