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author | stroese <stroese> | 2004-12-16 17:56:09 +0000 |
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committer | stroese <stroese> | 2004-12-16 17:56:09 +0000 |
commit | cd42deebd2d27dbefd91b757c852901351992e5a (patch) | |
tree | 945317b1f4aa9ee4124689cb9c6b27367ee3847d /lib_m68k | |
parent | e2c22d780e64e385e1c07b0e2203f164ca92f2c9 (diff) | |
download | u-boot-imx-cd42deebd2d27dbefd91b757c852901351992e5a.zip u-boot-imx-cd42deebd2d27dbefd91b757c852901351992e5a.tar.gz u-boot-imx-cd42deebd2d27dbefd91b757c852901351992e5a.tar.bz2 |
Coldfire MCF5249 support added
Diffstat (limited to 'lib_m68k')
-rw-r--r-- | lib_m68k/time.c | 86 |
1 files changed, 86 insertions, 0 deletions
diff --git a/lib_m68k/time.c b/lib_m68k/time.c index 6f73ba9..fb997b5 100644 --- a/lib_m68k/time.c +++ b/lib_m68k/time.c @@ -36,6 +36,11 @@ #include <asm/m5282.h> #endif +#ifdef CONFIG_M5249 +#include <asm/m5249.h> +#include <asm/immap_5249.h> +#endif + static ulong timestamp; #ifdef CONFIG_M5282 @@ -173,6 +178,87 @@ void wait_ticks (unsigned long ticks) #endif +#if defined(CONFIG_M5249) +/* + * We use timer 1 which is running with a period of 1 us + */ +void udelay(unsigned long usec) +{ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE1); + uint start, now, tmp; + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 1 as timebase clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + timerp->timer_tcn = 0; + /* set period to 1 us */ + /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ + timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_FREERUN | MCFTIMER_TMR_ENABLE; + + start = now = timerp->timer_tcn; + while (now < start + tmp) + now = timerp->timer_tcn; + } +} + +void mcf_timer_interrupt (void * not_used){ + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); + + /* check for timer 2 interrupts */ + if ((mbar_readLong(MCFSIM_IPR) & 0x00000400) == 0) { + return; + } + + /* reset timer */ + timerp->timer_ter = MCFTIMER_TER_CAP | MCFTIMER_TER_REF; + timestamp ++; +} + +void timer_init (void) { + volatile timer_t *timerp = (timer_t *) (CFG_MBAR + MCFTIMER_BASE2); + + timestamp = 0; + + /* Set up TIMER 2 as clock */ + timerp->timer_tmr = MCFTIMER_TMR_DISABLE; + + /* initialize and enable timer 2 interrupt */ + irq_install_handler (31, mcf_timer_interrupt, 0); + mbar_writeLong(MCFSIM_IMR, mbar_readLong(MCFSIM_IMR) & ~0x00000400); + mbar_writeByte(MCFSIM_TIMER2ICR, MCFSIM_ICR_AUTOVEC | MCFSIM_ICR_LEVEL7 | MCFSIM_ICR_PRI3); + + timerp->timer_tcn = 0; + timerp->timer_trr = 1000; /* Interrupt every ms */ + /* set a period of 1us, set timer mode to restart and enable timer and interrupt */ + /* on m5249 the system clock is (cpu_clk / 2) -> divide by 2000000 */ + timerp->timer_tmr = (((CFG_CLK / 2000000) - 1) << 8) | MCFTIMER_TMR_CLK1 | + MCFTIMER_TMR_RESTART | MCFTIMER_TMR_ENORI | MCFTIMER_TMR_ENABLE; +} + +void reset_timer (void) +{ + timestamp = 0; +} + +ulong get_timer (ulong base) +{ + return (timestamp - base); +} + +void set_timer (ulong t) +{ + timestamp = t; +} +#endif + + /* * This function is derived from PowerPC code (read timebase as long long). * On M68K it just returns the timer value. |