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author | Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | 2009-02-25 14:27:24 +0900 |
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committer | Wolfgang Denk <wd@denx.de> | 2009-04-28 00:18:10 +0200 |
commit | d4c02e6f5d49880123e7f584b88f857ffd874381 (patch) | |
tree | 40f22cb79ca2c973ffca60fb077d6b9c3dbe58f2 /lib_arm/_udivsi3.S | |
parent | 9c48a8ea383098a5b217aba91b6d44cefd5cbeeb (diff) | |
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rtl8169: fix cache coherency problem
Fix the problem that cannot access actual data when CPU data cache enabled.
Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com>
Tested-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
Acked-by: Ben Warren <biggerbadderben@gmail.com>
Diffstat (limited to 'lib_arm/_udivsi3.S')
0 files changed, 0 insertions, 0 deletions