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authorMarek Vasut <marex@denx.de>2015-08-11 00:49:09 +0200
committerMarek Vasut <marex@denx.de>2015-08-23 11:56:19 +0200
commita8535c306c68eb050ad0835845ea87a856b192f1 (patch)
tree9ffbad4eb997c0c7813a80bf35c7efa61f73fc15 /lib
parent35e47b7132fa515e32189077ec7b80090562c709 (diff)
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arm: socfpga: Fix delay in freeze controller
Based on observation, this udelay(20) was apparently too high and caused subsequent failure to calibrate DDR when U-Boot was compiled with certain toolchains. Lowering this delay fixed the problem. Instead of permanently lowering the delay, calculate the correct delay based on the original comment, that is, obtain EOSC1 frequency and use it to calculate the precise delay. Signed-off-by: Marek Vasut <marex@denx.de>
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